KR950010334A - Carrier Recovery Circuit of Digital Reception System - Google Patents

Carrier Recovery Circuit of Digital Reception System Download PDF

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Publication number
KR950010334A
KR950010334A KR1019930019514A KR930019514A KR950010334A KR 950010334 A KR950010334 A KR 950010334A KR 1019930019514 A KR1019930019514 A KR 1019930019514A KR 930019514 A KR930019514 A KR 930019514A KR 950010334 A KR950010334 A KR 950010334A
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KR
South Korea
Prior art keywords
output
detector
low pass
carrier
phase
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KR1019930019514A
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Korean (ko)
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KR100279585B1 (en
Inventor
김기현
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이헌조
주식회사 금성사
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Priority to KR1019930019514A priority Critical patent/KR100279585B1/en
Publication of KR950010334A publication Critical patent/KR950010334A/en
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Publication of KR100279585B1 publication Critical patent/KR100279585B1/en

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Abstract

본 발명은 디지탈 수신 시스템의 반송파 복구 회로에 관한 것으로, 종래에는 수신 신호를 복구할 때 초기 주파수 동기에 대한 반송파의 주파수 및 위상을 정확히 추정할 수 없음으로 직교 진폭 변조된 수신 신호의 복조 시간이 지연되는 문제점이 있었다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier recovery circuit of a digital reception system. In the related art, when demodulating a received signal, the demodulation time of a quadrature amplitude modulated received signal is delayed because the frequency and phase of the carrier cannot be accurately estimated for initial frequency synchronization. There was a problem.

이러한 점을 감안하여 본 발명에서는 직교 진폭 변조된 신호를 수신할 때 초기에 반송파의 주파수 및 위상 차를 검출하여 원래의 신호를 추정함에 따라 반송파의 주파수 및 위상을 신속 정확하게 동기시키게 된다.In view of this point, when the quadrature amplitude modulated signal is received, the frequency and phase of the carrier are initially detected to estimate the original signal to quickly and accurately synchronize the frequency and phase of the carrier.

따라서, 본 발명을 적용하면 초기에 반송파를 원래의 신호로 복조시킴으로써 초기의 동기 지연 시간을 줄일 수 있다.Therefore, by applying the present invention, the initial synchronization delay time can be reduced by demodulating the carrier with the original signal initially.

Description

디지탈 수신 시스템의 반송파 복구 회로Carrier Recovery Circuit of Digital Reception System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 반송파 복구 회로 블럭도,1 is a block diagram of a carrier recovery circuit of the present invention;

제2도는 16레벨 직교 변조 신호의 레벨 좌표를 보인 상태도.2 is a state diagram showing level coordinates of a 16-level orthogonal modulation signal.

Claims (2)

직교 진폭 변조 신호(5[t])를 동상과 직교 상으로 각기 복조시키는 믹서(1)(2)와, 이 믹서(1)(2)의 출력(DI))(DQ)을 연산함에 의해 특정 영역의, 신호 레벨인지 검출하는 영역 검출기(4)와, 상기 믹서(1)(2)의 출력(DI)(DQ)을 연산하여 수신 반송파와 복조 반송파간의 위상 차를 검출하는 위상 차 검출기(3)와, 이 위상 오차 검출기(3)의 출력(Ep)을 점검하여 동기 상태 주파수인지 검출하는 주파수 동기 검출부(5)와, 이 주파수 동기 검출부(5)의 출력(Ps)에 따라 상기 영역 검출기(4)의 출력(Dr)을 스위칭하는 스위치(6)와, 이 스위치(6)의 출력에 따라 상기 위상 오차 검출기(3)의 출력(EP)을 홀딩하는 홀더(7)와, 이 홀더(7)의 출력을 입력받아 저역만을 통과시키는 저역 통과 필터(8)와, 이 저역 통과필터(8)의 출력에 제어되어 동기된 발진 주파수를 상기 믹서(1)로 출력하는 국부 발진기(9)와, 이 국부 발진기(9)의 출력을 90°시프트시켜 상기 믹서(2)에 출력하는 위상 시프터(10)로 구성함을 특징으로 하는 디지탈 수신 시스템의 반송파 복구 회로.By calculating the mixer 1, 2 for demodulating the quadrature amplitude modulated signal 5 [t] in phase and quadrature, respectively, and the output DI of the mixer 1, 2, DQ is specified. An area detector 4 for detecting whether a signal is in the signal level, and a phase difference detector 3 for calculating a phase difference between a reception carrier and a demodulation carrier by calculating an output DI (DQ) of the mixer 1 and 2. ), A frequency synchronization detector 5 which checks the output Ep of the phase error detector 3 and detects whether it is a synchronous state frequency, and the area detector (3) according to the output Ps of the frequency synchronization detector 5. A switch 6 for switching the output Dr of 4), a holder 7 for holding the output EP of the phase error detector 3 according to the output of the switch 6, and the holder 7 A low pass filter (8) for receiving the output of the low pass only and a local part for controlling the output of the low pass filter (8) and outputting a synchronized oscillation frequency to the mixer (1). Oscillator 9 and the local oscillator 9 outputs a 90 ° shift to the carrier recovery circuit of the digital receiving system, it characterized in that a phase shifter (10) for the output to the mixer (2). 제1항에 있어서, 주파수 동기 검출부(5)는 위상오차 검출기(3)의 출력(EP)중 저역을 통과사키는 저역 통과필터(23)와, 이 저역 통과 필터(23)의 출력과 고 레벨 임계값(Th)을 비교하는 비교기 (24)와, 상기 저역 통과 필터(23)의 출력과 저 레벨 임계값(T1)을 비교하는 비교기(25)와, 상기 비교기(24)(25)의 출력을 앤딩하여 스위치(6)를 제어하기 위한 신호(Ps)를 출력하는 앤드 게이트(26)로 구성함을 특징으로 하는 디지탈 수신 시스템의 반송파 복구 회로.2. The frequency synchronization detector (5) according to claim 1, wherein the frequency synchronization detector (5) includes a low pass filter (23) which passes through low frequencies among the output (EP) of the phase error detector (3), and an output and a high level of the low pass filter (23). Comparator 24 for comparing threshold Th, comparator 25 for comparing output of low pass filter 23 and low level threshold T1, and outputs of comparators 24 and 25 And an end gate (26) for outputting a signal (Ps) for controlling the switch (6) by ending the operation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930019514A 1993-09-23 1993-09-23 Carrier Recovery Circuit of Digital Receiving System KR100279585B1 (en)

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KR1019930019514A KR100279585B1 (en) 1993-09-23 1993-09-23 Carrier Recovery Circuit of Digital Receiving System

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Application Number Priority Date Filing Date Title
KR1019930019514A KR100279585B1 (en) 1993-09-23 1993-09-23 Carrier Recovery Circuit of Digital Receiving System

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KR950010334A true KR950010334A (en) 1995-04-28
KR100279585B1 KR100279585B1 (en) 2001-02-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100245330B1 (en) * 1997-06-26 2000-02-15 전주범 Phase and frequency detector of digital communication system
KR100266629B1 (en) * 1997-09-26 2000-09-15 김영환 Stream encipher and decipher apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100245330B1 (en) * 1997-06-26 2000-02-15 전주범 Phase and frequency detector of digital communication system
KR100266629B1 (en) * 1997-09-26 2000-09-15 김영환 Stream encipher and decipher apparatus

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