KR950009430B1 - The processing time delay method ina real-time multiprocessing system - Google Patents

Abstract

The method comprises the steps of informing a user that an error is generated if delay requirement parameters are not accurate; informing the user whether an original discriminator of timer is generated or not; informing the user whether the time management data structure is generated or not; and dispatching and completing the above operations.

Description

Time Delay Method for Parallel Processing Process in Real-time Operation System

1 is a block diagram of hardware to which the present invention is applied.

2 is an overall flowchart of a time manager to which the present invention is applied.

3 is a detailed flowchart of the present invention.

4 is a flow diagram of a time delay reaction of the present invention.

* Explanation of symbols for main parts of the drawings

1: Central Processing Unit Board (MPMA)

2: Process communication control board (PCCA)

3: Redundant Operation Control Board (DCCA)

4: input / output interface board (IOIA)

5: Mass Storage Board (MISA)

6: Bootroom (BROM)

7 Central Processing Unit (CPU)

8: storage device

10: Multifunction Peripheral Control Chip (MFP)

The present invention relates to a time delay method of a parallel processing process in a large real-time multiprocessing system such as an electronic exchanger.

The electronic switching system to which the real-time operating system is applied generally has a distributed system structure according to functions, and each function is implemented by software (hereinafter referred to as a user program) in accordance with this structure.

Each of these user programs is responsible for call processing, operations management, and maintenance, which may require typical relative and absolute sleep.

In case of relative time delay, the user process is stopped for the desired time interval and has a tolerance of 40 ms. The absolute time delay stops the execution of the user process to the specified start time and can be requested within the tolerance of seconds. For example, a software timer with year, month, day, hour, minute, second, and millisecond values is placed in a TOD (Time Of Day) table. In addition, by managing the unique identifier and management table for each parallel processing process requiring a delay in a time manager with a multi-link structure, it is possible to time delay for the parallel processing process and to satisfy accuracy and real time. It is characterized by one.

In the conventional electronic switching system, such a function was required, but the time delay for the parallel processing process was not implemented. Therefore, the user programs had to simulate the parallel processing process to implement the time delay. The complexity of the system was high and it was difficult to satisfy real time.

Accordingly, an object of the present invention is to provide a time delay method of a primitive parallel processing process in a real time operating system operating a real time multiprocessing system.

In order to achieve the above object, the present invention provides an electronic switch comprising a central processing unit, a storage unit, a system status register, a storage management unit and an input / output unit and a timer (hereinafter referred to as RTC), and then a multifunction peripheral control chip. It is applied to the central processing unit board (MPMA) of the parallel processing process characterized in that it manages the unique identifier and management table of the parallel processing process.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a high-level process (MPH) of the electronic switching system, which is the hardware to which the present invention is applied, (a) is a block diagram of the entire hardware, and (b) is a block diagram of the central processing unit board (MPMA). .

In the drawing, (1) is a central processing unit board (MPMA), (2) is a processor communication control board (PCCA), (3) is a redundant operation board (DCCA), (4) is an input / output interface board (IOIA), (5 ) Is the mass storage board (MSIA), (6) is the boot ROM (BROM), (7) is the central processing unit (CPU), (8) is the memory, and (9) is the multifunction peripheral control chip (MFP). Indicates.

As shown in the figure, the upper processor hardware (MPH) to which the present invention is applied has a memory board (5) of the central processing unit board (1) and the central processing unit board (1) in which the software of the present invention is mounted and operated. MPMA), a processor communication control board (PCCA) that is in charge of communication with other processors under the control of the MPMA (1), and a redundant operation control board in charge of D-channel and C-channel control in relation to redundancy ( 3: DCCA) is connected to the system main bus.

The central processing unit board (1) is basically composed of a central processing unit (7), a storage unit (8) and a multifunction peripheral control chip (9) connected by a system bus. The storage unit includes a vector table and a task control table. An internal I / O device and a timer (hereinafter referred to as RTC) are provided inside the multifunction peripheral control chip. Such a configuration is a configuration of a general distributed system, but such a configuration must be provided to execute the exchange software and the operating system. In connection with the present invention, the RTC of the multifunction peripheral chip (MFP) in the central processing unit board is driven to manage the time management table based on a 40 millisecond interrupt.

2 is an overall flowchart of a time manager of an electronic switch operating system (OS) to which the present invention is applied.

When the initialization request of the time manager is received when the initialization of the operating system is started (20), the RTC is set to 0 and an initial memory for time management is allocated to initialize the time manager (21). When the timer is allowed to interrupt and system-wide initialization is complete, it is in a state of waiting for an RTC interrupt or a time-delay request from the parallel process (22).

If an interrupt is generated from the RTC (23), an interrupt service to be performed for each RTC is called (24). If there is a time delay request for the parallel processing process from the user program (25), it checks whether the relative time delay request or the absolute time delay request is required (26), and if it is absolute time, converts it to the relative time interval value (27) and registers it in the time manager. (28) If the relative time is registered with the time manager (28). Whenever the RTC interrupt occurs, the time value is decreased. When this value is 0, it is received from the interrupt handler that the registered process should be reacted (29). At this time, the task state is recorded as a sleeping in the task control table stored in the memory 8 to cancel the registration, the unique identification value given by the time manager is recorded, and the scheduler is called to register the process to be reactivated as ready state. After (30) go to the standby state (22).

3 is a detailed flowchart of the present invention, which corresponds to steps 25 to 28 in FIG.

Upon receiving the time delay request for the parallel processing process from the user program (40), it is determined whether the time delay request parameters are reasonable (41). If not, it notifies the user program of the user error (51) and terminates to prevent malfunction due to the error. If appropriate, a timer unique identifier to be registered in the time manager is generated (42). It is determined whether the generation of the timer unique identifier succeeds (43). If the generation fails, the user is notified of the reason for the failure (52), and if it is successful, it is determined whether the requested time value is an absolute time (TOD) (44). This timer identifier is an instance of the process to be registered. If the time value of the process requiring time delay is an absolute time, it is converted into a relative time interval value that can be managed in the system (45), and a time management data structure is generated (46).

After determining that the step 46 is successful (47) and failing, after notifying the user of the failure reason that the data structure of time management is no longer or cannot be recreated due to lack of system memory, 52) When it finishes, if it succeeds, it writes the type of time management in the data structure as a time delay request and writes a timer unique identifier necessary for wakeup (48), which constitutes a registered parallel process management table. . Finally, after registering the time delay request generated in the time manager with the time delay generated in the multi-link structure (49), dispatching with the status of this process as the time delay state and ending (50). do.

4 is a flow chart of a process of reacting the time delayed process of the present invention, which corresponds to the steps of (23), (24), (29) and (300) of FIG.

When the RTC interrupt is processed by the time manager (60), when the RTC interrupt is received (60), the value of milliseconds is accumulated for each RTC interrupt, and when it is determined that the value exceeds 1 second (61), the TOD related values (year, Month, day, hour, minute, second) and determine if there is a time delayed process (63). At this time, if there is a time-delayed process, the time delay request value of the process is reduced (64), and the time delay request value has elapsed, that is, it is determined whether the time value of the process requesting the time delay is zero (65). If the delay request time has not elapsed, the flow returns to the wait state 22 in the entire flowchart of FIG. 2, and if the delay request time has elapsed, the registered process is removed from the management table of the time manager (66) and registered with the scheduler (67). Thereby making the transition to the ready state.

Therefore, the effect of the present invention made of the above-described processing procedure is as follows.

By implementing the time delay processing for the parallel processing process as a primitive, users can increase the reliability by reducing the possibility of redundancy design and execution error, and the maintenance of the communication protocol can be simplified by using the present invention to facilitate maintenance. It has the advantage that it can be used especially when synchronization is required. And various applications that require time delay of the parallel processing process are possible.

Claims (1)

Central processing unit board of an electronic switching system comprising a boot ROM (6), a central processing unit (7), a storage unit (8), and a multifunction peripheral control chip (9) having an input / output unit and a timer (hereinafter referred to as RTC). (1: MPMA) is a method for delaying a parallel processing process, comprising: a first step of determining whether delay request parameters are correct if there is a delay request for the parallel processing process, and notifying the user that an error is not satisfied and ending; 40, 41, 51) and if the delay request parameters for the parallel process are valid during execution of the first step (40, 41, 51), a timer unique identifier to be registered in the time manager is generated and it is determined whether the generation was successful. If the generation fails, the second step (42, 43, 51) of notifying the user of the reason and ending, and the time value required if the unique identification and generation is successful during the second step (42, 43, 51) This Determine whether it is a large time and convert it to a relative period interval value that can be managed internally in the system, create a time management data structure, determine whether to create a time management data structure, and notify the user why it failed. During the completion of the third steps 44 to 47 and 51 and the third steps 44 to 47 and 51, if a data structure is generated, the type of time management is written in the generated structure as a delay request and reoperated. a fourth step (48 to 50) for writing a timer unique identifier required for wakeup and registering a delay request generated in a time manager having a multilink structure and dispatching and terminating the process state as a delay state. Time delay method for a parallel processing process, characterized in that carried out.