KR950008255B1 - Making method of high electron mobility transistor - Google Patents
Making method of high electron mobility transistor Download PDFInfo
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- KR950008255B1 KR950008255B1 KR1019920023356A KR920023356A KR950008255B1 KR 950008255 B1 KR950008255 B1 KR 950008255B1 KR 1019920023356 A KR1019920023356 A KR 1019920023356A KR 920023356 A KR920023356 A KR 920023356A KR 950008255 B1 KR950008255 B1 KR 950008255B1
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- gate electrode
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- -1 gallium arsenide compound Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
제1도의 (a)∼(g)는 본 발명의 제조공정을 나타낸 단면도.(A)-(g) is sectional drawing which showed the manufacturing process of this invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판(Substrate) 2 : 완충층(Buffer Layer)1 Substrate 2 Buffer Layer
3 : 2차원 전자개스(Two dimensional Electron Gas : 2DEG)3: Two dimensional Electron Gas (2DEG)
4 : 공간층(Spacer) 5 : 소오스층(Source Layer)4: Spacer 5: Source Layer
6 : 캡층(Cap Layer) 7 : 감광막(Photoresistor)6 Cap Layer 7 Photoresistor
8 : 게이트 금속층(Gate Metal Layer)8: Gate Metal Layer
9 : 소오스 및 드레인 오믹 금속층(Source and Drain Metal Layer)9: source and drain metal layer
본 발명은 갈륨비소 화합물 반도체의 고전자 이동도 트랜지스터(High Electron Mobility Transistor : HEMT)를 제조하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a high electron mobility transistor (HEMT) of a gallium arsenide compound semiconductor.
지금까지 연구 결과들은 갈륨비소 고전자 이동도 트랜지스터가 실리콘 소자나 갈륨비소 MESFET(Metal Semiconductor Field Effect Transistor)에 비해 주파수 특성이 우수한 고주파 및 고속용 소자임을 보여주고 있다. 고전자 이동도 트랜지스터는 도핑되고 넓은 밴드 갭을 갖는 알루미늄 갈륨비소 소오스층과 도핑을 하지 않은 갈륨비소 완충층의 경계에서 형성되는 이차원 전자개스(Two Dimensional Electron Gas)의 높은 전자이동도를 이용하므로 고전자 이동도 트랜지스터를 초고주파용 소자로 만들 경우 높은 차단 주파수 및 최대진동 주파수를 갖는 이상적인 소자가 된다. 하지만 위와 같은 장점에도 불구하고, 실제 고전자 이동도 트랜지스터는 아주 짧은 채널을 사용하여야 하며 여러가지 기생저항(예를들면, 게이트 전극과 소오스 전극 사이의 간격이 클때 생기는 높은 소오스 저항)이나 커패시터를 가능한 줄여야 하는 어려운 점이 있다.So far, the results show that gallium arsenide high electron mobility transistors are high-frequency and high-speed devices with better frequency characteristics than silicon devices or gallium arsenide MESFETs (Metal Semiconductor Field Effect Transistors). The high electron mobility transistor uses high electron mobility of two dimensional electron gas formed at the boundary between the doped and wide band gap aluminum gallium arsenide source layer and the undoped gallium arsenide buffer layer. Making a mobility transistor an ultra-high frequency device makes it an ideal device with high cutoff frequency and maximum vibration frequency. Despite the above advantages, however, the actual high electron mobility transistors must use very short channels and reduce as many parasitic resistances as possible (eg, high source resistance due to the large gap between the gate and source electrodes) or capacitors. There is a difficulty.
이러한 단점을 극복하기 위하여 여러방법의 자기정열(self-alignment) 전극형성 방법들이 이미 개발되어, 게이트와 소오스 전극의 간격을 최소화 시킴으로써 소오스 저항을 감소시킬 수 있었다. 하지만 짧은 채널의 게이트를 형성하기 위하여는 전자선 리소그래피(electron beam lithography)를 사용하여야 하는 문제가 있다. 전자선 리소그래피는 0.5~1μm 이하의 미세패턴을 형성하는데 아주 훌륭한 공정이지만 전자선의 스캐닝 속도가 느리기 때문에 공정의 진행속도가 아주 느리며, 리프트 오프(lift-off) 공정시 특수한 포토레지스트를 사용하여야 하고 게이트 저항을 감소하기 위한 T자형의 게이트를 형성할때 다층의 포토레지스터 공정이 필요하게 되는 단점이 있다.In order to overcome this drawback, several methods of forming self-alignment electrodes have already been developed, which can reduce the source resistance by minimizing the gap between the gate and the source electrode. However, there is a problem in that electron beam lithography must be used to form a gate of short channel. Electron lithography is a very good process for forming micropatterns of 0.5 ~ 1μm or less, but the process is very slow due to the slow scanning speed of electron beams, and special photoresist should be used in the lift-off process and gate resistance There is a disadvantage in that a multi-layer photoresist process is required when forming a T-shaped gate to reduce the voltage.
본 발명의 목적은 짧은 채널길이를 갖는 게이트를 간단히 형성시킬 수 있고 소자의 전기적 특성을 개선시킬 수 있는 고전자 이동도 트랜지스터(MEMT) 소자의 제조방법을 제공하는 것이다.It is an object of the present invention to provide a method of manufacturing a high electron mobility transistor (MEMT) device which can easily form a gate having a short channel length and improve the electrical characteristics of the device.
상기한 목적을 달성하기 위해 본 발명에서는 맨윗층의 캡층(cap layer)의 두께를 제외하고는 통상 사용되는 고전자 이동도 트랜지스터와 거의 같은 구조를 분자선 에피성장(MBE) 방법에 의해 알루미늄 갈륨비소/갈륨비소(AlGaAs/GaAs)층을 성장시킨 기판에 전자선 리소그래피를 사용하지 않고 MESA 식각만으로 아주 짧은 게이트 길이를 정의한 후, 소오스 및 드레인 오믹접촉 영역을 자기정열시켜 고성능 HEMT소자를 제조한다.In order to achieve the above object, in the present invention, except for the thickness of the cap layer of the uppermost layer, aluminum gallium arsenide / MBM is formed by the molecular beam epitaxial growth (MBE) method. After defining a very short gate length by MESA etching without using electron beam lithography on a substrate on which a gallium arsenide (AlGaAs / GaAs) layer is grown, a high performance HEMT device is manufactured by self-aligning the source and drain ohmic contact regions.
이제부터 첨부된 도면에 의거하여 본 발명에 대해 상세히 기술하겠다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도의 (a)도는 반절연 갈륨비소 티판(1)의에 성장된 HEMT 구조의 단면도로서, 기판(1)위에 MBE 방법에 의해 도핑되지 않은 GaAs 완충층(2)이 약 6,000Å 정도의 두께로 형성되고, 그위에 25Å 정도의 두께로 도핑되지 않은 AlGaAs 공간층(4)과 250∼500Å 두께의 n+AlGaAs 소오스층(5)을 순차로 형성시키면 완충층(2)과 공간층(4)사이에 2차원 전자개스(3)가 형성된다. 계속하여 소오스층(5)위에 약 1μm 두께의 n+GaAs 캡층(6)이 순차로 형성된 구조를 갖고 있다. 여기서 주목할 사항은 캡층(6)의 두께가 1μm 정도로서 통상의 HEMT 구조(1,000Å 이하)와 비하여 굉장히 두껍다는 저이다. 이후에 수행될 게이트 MESA 식각에 따라 최종 형성되는 게이트 길이는 캡층(6)의 두께에 반비례하므로 이 캡층(6)의 두께는 게이트 길이를 결정하는데 중요한 역할을 한다.FIG. 1 (a) is a cross-sectional view of the HEMT structure grown on the semi-insulating gallium arsenide titanium plate 1, wherein the undoped GaAs buffer layer 2 on the substrate 1 is about 6,000 로 thick. Formed, and a undoped AlGaAs spacer layer 4 having a thickness of about 25 GPa and an n + AlGaAs source layer 5 having a thickness of 250 to 500 GPa are sequentially formed between the buffer layer 2 and the spacer layer 4. The two-dimensional electron gas 3 is formed. Subsequently, the n + GaAs cap layer 6 having a thickness of about 1 μm is sequentially formed on the source layer 5. It is noteworthy here that the thickness of the cap layer 6 is about 1 μm, which is very thick as compared with a conventional HEMT structure (1,000 mm 3 or less). The thickness of the cap layer 6 plays an important role in determining the gate length since the gate length finally formed according to the gate MESA etching to be performed later is inversely proportional to the thickness of the cap layer 6.
(b)도는 습식식각을 통하여 기판(1)이 식각된 상태 즉. 소자분리 공정후 에피층의 단면도를 나타낸 것이다.(b) is a state in which the substrate 1 is etched through wet etching. A cross-sectional view of the epi layer after the device isolation process is shown.
(c)도는 게이트를 정의하기 위하여 두꺼운 포토레지스트(7)를 도포한 후 습식 MESA 식각을 이용하여 두꺼운 캡층(6)을 식각한 단면도이다. 이때 식각 각도는 약 60°이며 소오스층(5)에서 흑은 조금 더 깊은곳에서 식각을 멈추어야 한다. 이때 마스크 상의 게이트 길이가 약 1.5μm 이면, 실제 소오스층(5) 위에 형성되는 게이트 길이는 0.5μm 이하가 가능하다.(c) is a sectional view of the thick cap layer 6 etched using wet MESA etching after applying the thick photoresist 7 to define the gate. At this time, the etching angle is about 60 ° and black in the source layer 5 should stop the etching a little deeper. In this case, when the gate length on the mask is about 1.5 μm, the gate length formed on the actual source layer 5 may be 0.5 μm or less.
(d)도는 식각된 에피층 위에 게이트 전극을 형성하기 위해 바로 게이트 금속(8)을 증착한 상태를 나타낸 단면도이다.(d) is a cross-sectional view showing a state in which the gate metal 8 is directly deposited to form a gate electrode on the etched epi layer.
(e)도는 게이트 전극 형성후 포토레지스터(7) 위의 필요없는 금속층을 리프트 오프 방법으로 제거하고 두꺼운 캡층(6)을 약 1,000Å 정도까지 균일하게 식각한 예피층의 단면도이다. 여기서 게이트 전극의 형상이 V자 형태를 가지고 있기 때문에 소자제조후 짧은 게이트 길이에도 불구하고 게이트 저항을 감소시킬 수 있는 장점이 있다.(e) is a cross-sectional view of the epitaxial layer in which the unnecessary metal layer on the photoresist 7 is removed by the lift-off method after the gate electrode is formed, and the thick cap layer 6 is uniformly etched to about 1,000 kPa. Since the gate electrode has a V-shape, there is an advantage that the gate resistance can be reduced despite the short gate length after device fabrication.
(f)도에서 V자형 게이트 전극을 자기정열 마스크로 이용하여 소오스 및 드레인 오믹접촉 금속층(9)을 형성한 단면도를 보여주고 있다.FIG. 6 (f) shows a cross-sectional view of the source and drain ohmic contact metal layer 9 formed using a V-shaped gate electrode as a self alignment mask.
마지막으로 오믹접촉 금속층 형성후 게이트 전극(8)과 오믹전극(9) 사이에 연결되어 있는 1,000Å 정도의 갈륨비소 캡층(6)을 CCl2F2와 He을 이용한 ECR(electron cyclotron resonance) 건식식각 방법으로 아래에 있는 소오스층(5)에는 전혀 손상을 입히지 않고 식각한 후의 최종 소자의 단면도가 (g)에 나타나 있다.Finally, after forming the ohmic contact metal layer, the gallium arsenide cap layer 6 connected between the gate electrode 8 and the ohmic electrode 9 has an electron cyclotron resonance (ECR) dry etching process using CCl 2 F 2 and He. The cross-sectional view of the final element after etching without damaging the source layer 5 below by the method is shown in (g).
이로써 고속, 고주파, 저잡음 고전자 이동도 트랜지스터의 제조가 가능하게 된다.This makes it possible to manufacture high speed, high frequency and low noise high electron mobility transistors.
아울러 위의 제작공정은 MESFET의 게이트나 이종접합 바이폴라 트랜지스터(heterojunction bipolar transistor : HBT)의 에미터 전극 제조시도 그 응용이 가능하다.In addition, the above manufacturing process can be applied to the manufacture of emitter electrodes of MESFET gates or heterojunction bipolar transistors (HBTs).
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920023356A KR950008255B1 (en) | 1992-12-04 | 1992-12-04 | Making method of high electron mobility transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019920023356A KR950008255B1 (en) | 1992-12-04 | 1992-12-04 | Making method of high electron mobility transistor |
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| Publication Number | Publication Date |
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| KR940016890A KR940016890A (en) | 1994-07-25 |
| KR950008255B1 true KR950008255B1 (en) | 1995-07-26 |
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| KR1019920023356A KR950008255B1 (en) | 1992-12-04 | 1992-12-04 | Making method of high electron mobility transistor |
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