KR950007035A - Manufacturing method of semiconductor device with reduced junction capacity - Google Patents

Manufacturing method of semiconductor device with reduced junction capacity Download PDF

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Publication number
KR950007035A
KR950007035A KR1019940021739A KR19940021739A KR950007035A KR 950007035 A KR950007035 A KR 950007035A KR 1019940021739 A KR1019940021739 A KR 1019940021739A KR 19940021739 A KR19940021739 A KR 19940021739A KR 950007035 A KR950007035 A KR 950007035A
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film
forming
insulating film
semiconductor substrate
annular
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KR1019940021739A
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KR0139596B1 (en
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찌히로 오가와
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세끼모또 다다히로
니뽄 덴끼 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명의 반도체 장치의 제조방법에서, 개구(9)는 반도체 기판(1,2,3)에 놓여진 절연막(7) 내에 형성되고 리소그래피로 얻어지는 최소폭보다 더 좁은 환형 홈(12)은 자기정합 방식으로 개구를 따라 반도체 기판내에 형성된다. 이 제조방법은 반도체 기판(1,2,3)의 주면 상에 제1절연막(7)을 형성하는 단계; 제1절연막에 개구(9)를 형성하는 단계; 개구내부의 측벽을 따라 환형 막(10)을 형성하는 단계; 환형막으로 둘러싸인 반도체 기판의 표면에 제2절연막(11)을 형성하는 단계; 반도체 기판이 환형으로 노출되도록 환형막을 제거하는 단계; 반도체 기판의 노출된 영역을 에칭하므로써, 환형홈(12)을 형성하는 단계; 환형 홈의 내부를 포함하는 반도체 기판의 주면 전체에 대해 적어도 제3절연막(13)을 포함하는 막층을 형성하는 단계로 구성된다.In the method of manufacturing a semiconductor device of the present invention, the opening 9 is formed in the insulating film 7 placed on the semiconductor substrates 1, 2, 3 and the annular groove 12 narrower than the minimum width obtained by lithography is a self-aligning method. Is formed in the semiconductor substrate along the opening. This manufacturing method comprises the steps of forming a first insulating film (7) on the main surface of the semiconductor substrate (1, 2, 3); Forming an opening 9 in the first insulating film; Forming an annular film 10 along sidewalls within the opening; Forming a second insulating film 11 on the surface of the semiconductor substrate surrounded by the annular film; Removing the annular film to expose the semiconductor substrate in an annular shape; Forming an annular groove 12 by etching the exposed area of the semiconductor substrate; And forming a film layer including at least a third insulating film 13 on the entire main surface of the semiconductor substrate including the inside of the annular groove.

Description

감소된 접합용량의 반도체 장치 제조방법Manufacturing method of semiconductor device with reduced junction capacity

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A도 및 제3B도는 본 발명의 제1실시예에 따른 반도체 장치를 설명하는 도면으로서,3A and 3B are diagrams illustrating a semiconductor device according to a first embodiment of the present invention.

제3A도는 평면도이고,3A is a plan view,

제3B도는 제3A도의 3B-3B선 단면도,3B is a cross-sectional view taken along line 3B-3B of FIG. 3A;

제4A도 및 제4B도는 본 발명의 제2실시예에 따른 반도체 장치를 설명하는 도면으로서,4A and 4B are diagrams illustrating a semiconductor device according to a second embodiment of the present invention.

제4A도는 평면도이고,4A is a plan view,

제4B도는 제4A도는 제4B-4B선 단면도.4B is a cross-sectional view taken along line 4B-4B of FIG. 4A.

Claims (8)

반도체 장치의 제조방법에 있어서, (ㄱ)반도체 기판(1,2,3)의 주면 상에 제1절연막(7)을 형성하는 제1절연막 형성단계; (ㄴ) 포토레지스트(photoresist)를 마스크로 사용해서 제1절연막을 에칭하므로써 상기 제1절연막에 개구(9)를 형성하는 개구 형성단계; (ㄷ)상기 개구내주의 측벽을 따라 노출된 상기 반도체 기판의 상면과 함께 환형막(10)을 형성하는 환형막 형성단계; (ㄹ)상기 환형막(10)에 의해 둘러싸인 상기 반도체 기판의 노출된 표면 상에 제2절연막(11)을 형성하는 제2절연막 형성단계; (ㅁ)상기 반도체 기판의 표면이 환형으로 노출되도록 상기 환형막을 에칭하는 환형막 에칭단계; (ㅂ)환형 홈(12)을 형성하기 위해 포토레지스트를 마스크로 사용해서 상기 반도체 기판의 환형 노출부를 에칭하는 환형 노출부 에칭단계; (ㅅ)상기 환형 홈(12)의 내부를 포함하는 상기 반도체 기판의 주면 전체에 대해 적어도 제3절연막(13)을을 포함하는 막층(13,14)을 형성하는 막층 형성단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.A method of manufacturing a semiconductor device, comprising: (a) forming a first insulating film (7) on a main surface of a semiconductor substrate (1, 2, 3); (B) an opening forming step of forming an opening (9) in the first insulating film by etching the first insulating film using a photoresist as a mask; (C) an annular film forming step of forming an annular film 10 together with an upper surface of the semiconductor substrate exposed along sidewalls of the opening inner circumference; (D) forming a second insulating film (11) on the exposed surface of the semiconductor substrate surrounded by the annular film (10); An annular film etching step of etching the annular film to expose the surface of the semiconductor substrate in an annular shape; (Iii) an annular exposed portion etching step of etching an annular exposed portion of the semiconductor substrate using a photoresist as a mask to form an annular groove 12; (G) a film layer forming step of forming film layers 13 and 14 including at least a third insulating film 13 on the entire main surface of the semiconductor substrate including the inside of the annular groove 12. A manufacturing method of a semiconductor device. 제1항에 있어서, 반도체 기판은 하부 영역으로 실리콘 기판(1), 상부 영역으로 매립영역(2)과 에피택셜(epitaxial)영역(3)에 의해 형성되고, 상기 매립영역은 실리콘 기판과 에피택셜 영역 사이에 끼워지고, 상기 제1절연막(7)은 이산화 실리콘막에 의해 형성되고, 상기 환형 막(10)은 질화실리콘 막에 의해 형성되고, 상기 제2절연막(11)은 이산화실리콘 막에 의해 형성되고, 상기 막층내에 있는 상기 제3절연막(13)은 이산화실리콘 막에 의해 형성되는 것을 특징으로 하는 반도체 장치의 제조방법.The semiconductor substrate of claim 1, wherein the semiconductor substrate is formed by a silicon substrate 1 as a lower region and a buried region 2 and an epitaxial region 3 as an upper region, wherein the buried region is epitaxial with the silicon substrate. Sandwiched between regions, the first insulating film 7 is formed by a silicon dioxide film, the annular film 10 is formed by a silicon nitride film, and the second insulating film 11 is formed by a silicon dioxide film. And the third insulating film (13) in the film layer is formed of a silicon dioxide film. 제2항에 있어서, 상기 환형 홈(12)은 상기 반도체 장치의 상기 매립영역(2)의 상면에 도달하도록 형성되어 있는 것을 특징으로 하는 반도체 장치의 제조방법.The method according to claim 2, wherein the annular groove (12) is formed so as to reach an upper surface of the buried region (2) of the semiconductor device. 제1항에 있어서, 제1절연막 형성단계(ㄱ)에 앞서 상기 막층 형성단계(ㅅ)에서 형성되고, 절연막(5)과 매설물(6)로 채워진 소자분리홈(4)을 포토레지스트를 마스크로 사용해서 형성하는 단계를 부가로 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.The photoresist of claim 1, wherein the device isolation groove 4 formed in the film layer forming step (S) and filled with the insulating film 5 and the buried material 6 is formed before the first insulating film forming step (a). A method for manufacturing a semiconductor device, comprising the step of forming by use. 제4항에 있어서, 콜렉터 주입부(15)를 형성하기 위해 상기 개구(9)와 상기 소자 분리홈(4)으로 둘러싸인 상기 제1절연막(7)을 에칭하는 단계; 콜렉터 영역을 형성하기 위해 이온주입으로 콜렉터 불순물 주입부 아래의 상기 에피택셜 영역(3)으로 불순물을 주입하는 단계; 콜렉터 영역내의 상기 불순물을 매립영역(2)으로 확산시키기 위해 열처리를 행하는 단계; 베이스 폴리실리콘부(17)를 형성하기 위해 주입된 불순물과 함께 상기 개구(9)에 대해 폴리실리콘을 퇴적하는 단계; 반도체 장치 전체에 대해 이산화 실리콘 막을 형성하는 단계; 에미터 개구(19)를 형성하기 위해 상기 이산화 실리콘막(18)과 상기 베이스 폴리실리콘부(17)를 이방성으로 에칭하는 단계; 고유의 베이스 영역(21)을 형성하기 위해 상기 에미터 개구(19)를 통해 상기 반도체 기판으로 불순물을 주입하는 단계; 에미터 측벽(22)과 에미터 폴리실콘부(23)를 형성하는 단계; 에미터 영역(24)을 형성하기 위해 열처리를 행하고 동시에 외부 베이스 영역(20)을 형성하기 위해 상기 에피택셜영역(3)에 상기 베이스 폴리실리콘부(17)에 포함된 불순물을 주입하는 단계; 상기 이산화 실리콘 막(44,18)내에 이산화 실리콘막(44)과 배선 컨택트 호울(25;wiring contact hole)을 형성하는 단계; 알루미늄이 반도체 장치의 전체 표면에 대해 퇴적된 후 패터닝 하므로써 알루미늄 배선(27)을 형성하는 단계를 부가로 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.Etching the first insulating film (7) surrounded by the opening (9) and the device isolation groove (4) to form a collector injection portion (15); Implanting impurities into the epitaxial region (3) below the collector impurity implantation portion by ion implantation to form a collector region; Performing heat treatment to diffuse the impurities in the collector region into the buried region (2); Depositing polysilicon over the opening (9) with impurities implanted to form a base polysilicon portion (17); Forming a silicon dioxide film over the entire semiconductor device; Anisotropically etching the silicon dioxide film (18) and the base polysilicon portion (17) to form an emitter opening (19); Implanting impurities into the semiconductor substrate through the emitter opening (19) to form a unique base region (21); Forming an emitter sidewall 22 and an emitter polysilicon portion 23; Heat treatment to form the emitter region 24 and implanting impurities contained in the base polysilicon portion 17 into the epitaxial region 3 to form the outer base region 20 at the same time; Forming a wiring contact hole (25) and a silicon dioxide film (44) in the silicon dioxide films (44,18); And forming aluminum wirings (27) by patterning the aluminum after it is deposited over the entire surface of the semiconductor device. 제4항에 있어서, 리소그래피(lithography)에 사용되는 상기 포토레지스트의 마스크 패턴이 선택적으로 변경됨으로서 상기 환형 홈(12)은 상기 소자 분리홈(4)의 세변을 따라 중첩되는 것을 특징으로 하는 반도체 장치의 제조방법.The semiconductor device according to claim 4, wherein the annular groove 12 overlaps three sides of the device isolation groove 4 by selectively changing a mask pattern of the photoresist used for lithography. Manufacturing method. 제1항에 있어서, 상기 막층(13,14)을 에치 백하는 단계; 열산화로 게이트 절연막(37)을 형성하는 단계; 상기 게이트 절연막 상에 게이트 전극(38)을 형성하기 위해 소자에 대해 폴리실리콘을 퇴적하고 패터닝하는 단계; 소스 영역(35)과 드레인 영역(36)을 형성하도록 상기 게이트 전극을 마스크로 사용해서 상기 반도체 기판으로 불순물을 주입하는 단계를 부가로 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 1, further comprising: etching back the membrane layers (13,14); Forming a gate insulating film 37 by thermal oxidation; Depositing and patterning polysilicon over the device to form a gate electrode (38) on the gate insulating film; And implanting impurities into the semiconductor substrate using the gate electrode as a mask to form a source region (35) and a drain region (36). 제1항에 있어서, 상기 반도체 기판이 저항 폴리실리콘 아래의 제1부분과 상기 제1부분과 다른 제2부분으로 절연 분리되도록, 상기 반도체 기판에 놓여진 상기 막층(13,14)상에 저항 폴리실리콘부(39)를 형성하는 단계를 부가로 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.2. The resistive polysilicon of claim 1, wherein the semiconductor substrate is insulated and separated into a first portion under the resistive polysilicon and a second portion different from the first portion. And forming a portion (39). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940021739A 1993-08-28 1994-08-27 Method for manufacturing semiconductor device with reduced junction capacitance KR0139596B1 (en)

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JP5235379A JP2914117B2 (en) 1993-08-28 1993-08-28 Method for manufacturing semiconductor device
JP93-235379 1993-08-28

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JP2914117B2 (en) 1999-06-28

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