KR950006920Y1 - Programable key matrix alternative circuit - Google Patents

Programable key matrix alternative circuit Download PDF

Info

Publication number
KR950006920Y1
KR950006920Y1 KR2019930001320U KR930001320U KR950006920Y1 KR 950006920 Y1 KR950006920 Y1 KR 950006920Y1 KR 2019930001320 U KR2019930001320 U KR 2019930001320U KR 930001320 U KR930001320 U KR 930001320U KR 950006920 Y1 KR950006920 Y1 KR 950006920Y1
Authority
KR
South Korea
Prior art keywords
connector
input
terminal
output
multiplexer
Prior art date
Application number
KR2019930001320U
Other languages
Korean (ko)
Other versions
KR940021109U (en
Inventor
이수원
Original Assignee
대우전자 주식회사
배순훈
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 대우전자 주식회사, 배순훈 filed Critical 대우전자 주식회사
Priority to KR2019930001320U priority Critical patent/KR950006920Y1/en
Publication of KR940021109U publication Critical patent/KR940021109U/en
Application granted granted Critical
Publication of KR950006920Y1 publication Critical patent/KR950006920Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/02—Input arrangements using manually operated switches, e.g. using keyboards or dials
    • G06F3/023—Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
    • G06F3/0238—Programmable keyboards
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

내용 없음.No content.

Description

피씨비(PCB) 자동조정기의 프로그래머블 키이 매트릭스(KEY MATRIX) 절환회로Programmable KEY MATRIX Switching Circuit for PCB Automatic Regulators

제1도는 본고안의 회로도.1 is a circuit diagram of this article.

제2도는 본고안에 따른 진리치표.Figure 2 is the truth table according to this proposal.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 컴퓨터 2 : 포트확장기1: Computer 2: Port Expander

3 : 코넥터 4 : 디코더3: connector 4: decoder

5 : 입력코넥터 6-13 : 멀티플렉서5: Input Connector 6-13: Multiplexer

14 : 출력코넥터 15 : 키이매트릭스 절환회로14: output connector 15: key matrix switching circuit

본 고안은 PCB자동조정기에서 특히 PCB 어셈블리(ASSEMBLY)의 동작을 제어하는데 있어서 컴퓨터에 의해 자동으로 키이(KEY) 조작을 할수 있도록 한 피씨비자동조정기의 프로그래머블 키이매트릭스 절환 회로에 관한 것이다.The present invention relates to a programmable key matrix switching circuit of a PPC controller that enables automatic key manipulation by a computer in controlling the operation of the PCB assembly (ASSEMBLY).

종래에는 PCB 어셈블리의 동작에는 제어하기 위해서는 리모콘이나 PCB 어셈블리의 측면판넬에 있는 조작키이를 수동으로 사람이 직접 조작을 해야 했으므로 작업시간이 많이 소요되고 조작 키이를 잘못 눌러 PCB 어셈블리의 동작상태를 잘못 체크(CHECK)하는 등의 문제점이 발생되었던 것이다.Conventionally, in order to control the operation of the PCB assembly, manipulating the operation keys on the remote control panel or the side panel of the PCB assembly manually requires a lot of work time and incorrectly checking the operation state of the PCB assembly by pressing the operation keys incorrectly. Problems such as (CHECK) occurred.

따라서 본 고안은 상기와 같은 제반 결점을 해소하기 위하여 안출한 것으로서 그 목적으로는 PCB 어셈블리의 키이입력회로에서 테스트포인트(T.P)점을 추출하여 컴퓨터의 제어에 의해 자동으로 키이조작을 하여 입력할 수 있는 매트릭스회로를 제공하는데 있다.Therefore, the present invention was devised to solve the above-mentioned shortcomings, and for this purpose, the test point (TP) point is extracted from the key input circuit of the PCB assembly, and the key operation can be automatically performed by the control of the computer. To provide a matrix circuit.

이와 같은 목적을 가진 본 고안의 구성을 첨부된 도면에 의거하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings the configuration of the subject innovation having such a purpose as follows.

컴퓨터(1)에 프로그램된 8비트데이트가 포트확장기(2)를 통해 코넥터(3)에 입력되면 상기 코넥터(3)의 1,2,3비트를 키이매트릭스절환회로(15)의 멀티플렉서(6-13) A,B,C단으로 입력되게하고 코넥터(3)의 4,5,6비트를 디코더(4)를 A,B,C단으로 입력하고 디코더(4)의 출력단을 멀티플렉서(6-13)의 INH단에 연결하고 입력 코넥터(5)를 멀티플렉서(6-13)을 통해 출력코넥터(14)에 접속하여서된 피씨비자동조정기의 프로그래머블 키이매트릭스절환회로인 것이다.When the 8-bit data programmed in the computer 1 is input to the connector 3 through the port expander 2, the 1, 2, 3 bits of the connector 3 are multiplexed by the key matrix switching circuit 15 (6-). 13) Inputs 4, 5, and 6 bits of the connector 3 to the A, B, and C stages, and inputs the decoder 4 to the A, B, and C stages, and outputs the decoder 4 a multiplexer (6-13). It is a programmable key matrix switching circuit of a PCB automatic controller connected to the INH terminal of the CPC) and the input connector 5 connected to the output connector 14 through the multiplexer 6-13.

이하 첨부된 도면에 의해 본고안의 작용 및 효과를 설명하면 다음과 같다.Referring to the operation and effects of the present invention by the accompanying drawings as follows.

컴퓨터(1)에 프로그램된 8비트데이트가 포트확장기(2)를 통해 확장된 후 코넥터(3)에 입력되면 그중 1,2,3비트는 키이매트릭스절환회로(15)의 멀티플렉서(6-13) A,B,C단으로 입력되고 4,5,6비트는 디코더(4)의 A,B,C단으로 입력하고 디코더(4)의 0부터 7번까지의 출력단은 멀티플렉서(6-13)의 INH단에 연결되는데 입력 코넥터(5)의 출력코넥터(14)의 각 비트수는 8개씩 있으므로 8 8=64가 되어 64가지를 얻을 수 있는데 그 일례로서 몇가지 예를 들어 설명하기로 한다.When the 8-bit data programmed in the computer 1 is expanded through the port expander 2 and input to the connector 3, 1, 2, 3 bits of the multiplexer 6-13 of the key matrix switching circuit 15 are input. Inputs A, B, and C are input, and 4, 5, and 6 bits are input to the A, B, and C terminals of the decoder 4, and output terminals 0 through 7 of the decoder 4 are input to the multiplexer 6-13. The number of bits of the output connector 14 of the input connector 5, which is connected to the INH stage, is 8, so that 8 8 = 64 can be obtained 64. Some examples will be described.

먼저 입력코넥터(5)의 IN1와 출력코넥터(14)의 OUT1가 연결되려면 컴퓨터(1)에서 프로그램된 8비트데이타가 포트확장기(2)를 통해 콘넥터(3)에 입력되어 이의 출력단인 1,2,3,4,5,6비트에 000, 000가 주어지면 코넥터(3)의 1,2,3비트는 키이매트릭스절환회로(15)의 각 멀티플렉서(6-13)의 A,B,C단에 입력디어 멀티플렉서(6-13) 모두에 X0가 선택되어지고 코넥터(3)의 4,5,6비티는 디코더(4)의 A,B,C단에 입력되어 이의 출력단0에서 로우(LOW)신호가 출력됨과 동시에 멀티플렉스(6)의 INH에 "로우"신호가 입력되어 상기 멀티플렉서(6)가 작동(ACTIVE)되고 나머지 멀티플렉서(7-13)는 억제(INHIBIT)되므로 입력코넥터(5)의 IN1단자와 출력코넥터(14)의 OUT1단자가 연결된다.First, in order for IN 1 of the input connector 5 and OUT 1 of the output connector 14 to be connected, 8-bit data programmed in the computer 1 is input to the connector 3 through the port expander 2 so that its output terminal 1 is 1. When 2,3,4,5,6 bits are given 000, 000, the 1, 2, 3 bits of the connector (3) represent A, B, and A of the multiplexer (6-13) of the key matrix switching circuit (15). X 0 is selected on both the input demultiplexers (6-13) at the C stage, and 4, 5, 6 bits of the connector (3) are inputted at the A, B, C stages of the decoder (4), and low at the output stage 0 thereof. (LOW) signal is output and at the same time the "low" signal is input to the INH of the multiplex 6, the multiplexer 6 is activated (ACTIVE) and the remaining multiplexer (7-13) is suppressed (INHIBIT) input connector ( the OUT 1 terminal of the iN 1 terminal and the output connector 14 of 5) are connected.

또한 입력코넥터(5)의 IN1와 출력코넥터(14)의 OUT7가 연결되려면 코넥터(3)출력단자에 000,011이 되어 1,2,3비트는 멀티 플렉서(6-13)의 A,B,C단에 입력되어 멀티플렉서(6-13) 모두에 X0가 선택되어지고 코넥터(3)의 4,5,6비트는 디코더(4)의 A,B,C단에 입력되어 이의 출력단6에서 "로우"신호가 출력됨과 동시에 멀티플렉스(12)의 INH에 "로우"신호가 입력되어 상기 멀티플렉서(6)가 작동되고 나머지 멀티플렉서(6-11)(13)는 억제되므로 입력코넥터(5)의 IN1단자와 출력코넥터(14)의 OUT7단자가 연결된다.In addition, when IN 1 of the input connector 5 and OUT 7 of the output connector 14 are connected, the output terminal of the connector 3 is 000,011, and 1, 2, 3 bits are A, B of the multiplexer 6-13. Is inputted at the C terminal, and X 0 is selected at all the multiplexers 6-13, and 4, 5, and 6 bits of the connector 3 are inputted at the A, B, and C terminals of the decoder 4, and at the output terminal 6 thereof. The "low" signal is output and the "low" signal is input to the INH of the multiplex 12 so that the multiplexer 6 is activated and the remaining multiplexers 6-11 and 13 are suppressed. The IN 1 terminal and the OUT 7 terminal of the output connector 14 are connected.

또한 입력코넥터(5)의 IN4단자와 출력코넥터(14)의 OUT2단자를 연결하려면 코넥터(3) 출력단자에 110,100가 되어 이의 1,2,3비트는 멀티플렉서(6-13)의 A,B,C에 입력되어 상기 멀티플렉서(6-13) 모두에 X1이 선택되어지고 코넥터(3)의 4,5,6비트는 디코더(4)의 A,B,C단에 입력되어 이의 출력단 1에서 "로우"신호가 출력됨과 동시에 멀티플렉서(7)의 INH 단자에 "로우"신호가 입력되어 상기 멀티플렉서(7)가 작동되고 나머지 멀티플렉서(6)(8-13)는 억제되므로 입력코넥터(5)의 IN4단자와 출력코넥터(14)의 PUT2단자가 연결된다. 또한 입력코넥터(5)의 IN8단자와 출력코넥터(14)의 OUT8을 연결하려면 코넥터(3) 출력단자에 111,111가 되어 이의 1,2,3비트는 멀티플렉서(6-13)의 A,B,C에 입력되어 상기 멀티플렉서(6-13) 모두에 X7이 선택되어지고 코넥터(3)의 4,5,6비트는 디코더(4) A,B,C단에 입력되어 이의 출력단 7에서 "로우"신호가 출력됨과 동시에 멀티플렉서(13)의 INH에 "로우"신호가 입력되어 상기 멀티플렉서(13)가 작동되고 나머지 멀티플렉서(6-12)는 억제되므로 입력코넥터(5)의 IN8단자와 출력코넥터(14)의 OUT8단자가 연결된다.In addition, in order to connect the IN 4 terminal of the input connector 5 and the OUT 2 terminal of the output connector 14, the output terminal of the connector 3 is 110,100, and the 1, 2, 3 bits thereof are the A, X 1 is selected in both the multiplexers 6-13, and 4, 5, and 6 bits of the connector 3 are inputted to the A, B, and C terminals of the decoder 4, and the output terminal 1 thereof is inputted to B and C. At the same time the "low" signal is outputted at the same time the "low" signal is input to the INH terminal of the multiplexer 7 to operate the multiplexer 7 and the remaining multiplexer (6) (8-13) is suppressed input connector (5) IN 4 terminal of the connector and PUT 2 terminal of the output connector 14 are connected. In addition, to connect the IN 8 terminal of the input connector 5 and the OUT 8 of the output connector 14, it is 111,111 at the output terminal of the connector 3, and the 1, 2, 3 bits thereof are A, B of the multiplexer 6-13. , X 7 is selected for all the multiplexers 6-13, and 4, 5, and 6 bits of the connector 3 are inputted to the decoders A, B, and C terminals, and the output terminal 7 of the multiplexer 6-13 is selected. A low signal is output to the INH of the multiplexer 13 so that the multiplexer 13 is operated and the remaining multiplexers 6-12 are suppressed, so that the IN 8 terminal and the output of the input connector 5 are suppressed. The OUT 8 terminal of the connector 14 is connected.

또한 입력코넥터(5)의 IN5단자와 출력코넥터(14)의 OUT3번 단자를 연결하고자 하면 코넥터(3)의 출력단자에 001,010가 되어 이의 1,2,3비트는 멀티플렉서(6-13)의 A,B,C에 입력되어 상기 멀티플렉서(6-13) 모두에 X4가 선택되고 코넥터(3)의 4,5,6비트는 디코더(4)의 A,B,C단에 입력되어 이의 출력단 2에서 "로우"신호가 출력됨과 동시에 멀티플렉서(8)의 INH 단자에 "로우" 신호가 입력되어 상기 멀티플렉서(8)가 작동되고 나머지 멀티플렉서(6)(7)(9-13)는 억제되므로 입력코넥터(5)의 IN5단자와 출력코넥터(14)의 OUT3번 단자가 연결된다.In addition, if you want to connect IN 5 terminal of input connector 5 and OUT 3 terminal of output connector 14, it becomes 001,010 to the output terminal of connector 3, and 1,2,3 bits thereof are multiplexer (6-13). X 4 is selected in all of the multiplexers 6-13, and 4 , 5, and 6 bits of the connector 3 are inputted to the A, B, and C stages of the decoder 4 so that Since the "low" signal is output at the output terminal 2 and the "low" signal is input to the INH terminal of the multiplexer 8, the multiplexer 8 is operated and the remaining multiplexers 6, 7, 9-13 are suppressed. The IN 5 terminal of the input connector 5 and the OUT 3 terminal of the output connector 14 are connected.

상술한 바와 같이 본고안은 입력코넥터와 출력코넥터의 각 단자를 연결하는데 있어서 디코더와 8개의 멀티플렉서로된 키이매트릭스절환회로를 사용하여 컴퓨터에 입력된 프로그램에 의해 자유자재로 연결하여 64라인을 연결할 수 있으며 수동으로 키이조작하던 것을 자동으로 절환하므로서 작업능률상승 및 작업자에 의해 오조작 키이 입력을 방지하고 컴퓨터에 의한 제어를 하므로 조작이 간편하고 생산성을 향상시킬수 있는 유익한 고안이다.As described above, this paper uses a key matrix switching circuit composed of a decoder and eight multiplexers to connect each terminal of the input connector and the output connector. In addition, by automatically switching the key operation manually, it is an advantageous design to increase the work efficiency and prevent mis-operation key input by the operator and control by the computer, so that the operation is simple and the productivity can be improved.

Claims (1)

입력코넥터(5)의 입력단자 IN1-IN8와 출력코넥터(14)의 출력단자 OUT1-OUT|8를 연결하는 통상의 피씨비자동조정기의 키이입력 회로에 있어서, 테스트포인트점을 추출하여 키이매트릭스절환회로(15)의 디코더(4)와 멀티플렉서(6-13)로 절환하여 컴퓨터(1)제어에 의해 자동으로 키이조작을 할수 있는 것을 특징으로 하는 피씨비자동조정기의 프로그래머블키이 매트릭스 절환회로.Input terminal IN 1 -IN 8 of the input connector 5 and output terminal OUT 1 -OUT | of the output connector 14 | In the key input circuit of the ordinary PCB automatic controller connecting 8 , the test point is extracted and switched to the decoder 4 and the multiplexer 6-13 of the key matrix switching circuit 15 to control the computer 1. Programmable key matrix switching circuit of the PCB automatic regulator, characterized in that the key operation can be performed automatically.
KR2019930001320U 1993-02-03 1993-02-03 Programable key matrix alternative circuit KR950006920Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019930001320U KR950006920Y1 (en) 1993-02-03 1993-02-03 Programable key matrix alternative circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019930001320U KR950006920Y1 (en) 1993-02-03 1993-02-03 Programable key matrix alternative circuit

Publications (2)

Publication Number Publication Date
KR940021109U KR940021109U (en) 1994-09-24
KR950006920Y1 true KR950006920Y1 (en) 1995-08-23

Family

ID=19350247

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019930001320U KR950006920Y1 (en) 1993-02-03 1993-02-03 Programable key matrix alternative circuit

Country Status (1)

Country Link
KR (1) KR950006920Y1 (en)

Also Published As

Publication number Publication date
KR940021109U (en) 1994-09-24

Similar Documents

Publication Publication Date Title
KR950016231A (en) Video jack automatic recognition circuit
KR970049302A (en) Power control device and method for computer peripherals
WO1999038064A3 (en) Multiperson tactual virtual environment
KR950006920Y1 (en) Programable key matrix alternative circuit
ATE57803T1 (en) PROGRAMMABLE CIRCUIT ARRANGEMENT.
TW366470B (en) IC card control circuit and the IC card control system
JPH0282894A (en) Diagnostic circuit
CA2035391A1 (en) Call status recognition in a broadband private automatic branch exchange
JPS61193219A (en) Power supply application system
JPH10143298A (en) Signal input/output circuit
KR930004900Y1 (en) Video-output selecting circuit for p.c.
AU5333286A (en) Dual connecting circuits
JPH1169478A (en) Audio circuit
GB2234104A (en) Computer workstation network
TW364271B (en) Memory circuit
IT1259027B (en) Modular base element for a multistage connection network of ATM technique, able to inhibit the transmission of cells from the elements of the upstream stages
KR20010029354A (en) Input-output port auto connection apparatus using a memory port connection system
JPS6225301A (en) Sequence controller
JPH0345059A (en) Station state display data selection system
JPH0355941A (en) Key telephone set
KR19980023506A (en) I / O terminal switching device of A / V equipment
JPH09244916A (en) Controller and inspection device therefor
JPS5771753A (en) Machine tool system controlled by speech response
JPH07250357A (en) Data configuration method for electronic exchange
KR950006475A (en) Key matrix key switch drive control circuit

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20011009

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee