KR950003936B1 - Insulated gate type fet and making method thereof - Google Patents
Insulated gate type fet and making method thereof Download PDFInfo
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- 125000006850 spacer group Chemical group 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 2
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- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- -1 phosphorus ion Chemical class 0.000 description 2
- 108010001779 Ancrod Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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Abstract
내용 없음.No content.
Description
제1도는 종래의 LDD(Lightly Doped Drain) 구조를 나타낸 단면도.1 is a cross-sectional view showing a conventional lightly doped drain (LDD) structure.
제2도의 (a)∼(d)는 본 발명에 의한 LDD구조의 제조공정을 나타낸 단면도.(A)-(d) is sectional drawing which shows the manufacturing process of the LDD structure by this invention.
제3도의 (a),(b)는 I-V 특성 비교 그래프.(A), (b) of FIG. 3 is an I-V characteristic comparison graph.
본 발명은 고집적도를 갖는 집접회로에 형성되는 절연게이트형 전계효과 트랜지스터(Insulated Gate Field Effect Transistor, 이하 IGFET)에 관한 것으로, 특히 채널과 소오스, 드레인 영역 사이에 저농도영역을 형성시켜 디바이스 내부의 전계강도를 완화시킨 LDD구조를 가지는 IG FET와 그 제조방법에 관한 것이다.The present invention relates to an Insulated Gate Field Effect Transistor (IGFET) formed in an integrated circuit having a high density. In particular, the present invention relates to an electric field inside a device by forming a low concentration region between a channel, a source, and a drain region. An IG FET having an LDD structure with reduced strength and a method of manufacturing the same.
IG FET의 대표적인 형태인 MOS(Metal Oxide Semiconductor) FET에 있어서 디바이스의 고속화, 고집적화를 위해 디바이스의 미세화를 위한 스케일링이 급속히 진전되어 왔으나, 전원전압이 일정하게 유지되는 가운데 채널 길이가 축소되어 디바이스 내부의 전계강도가 증대되어 FET 특성에 각종 악영향을 끼치고 있다.In MOS (Metal Oxide Semiconductor) FET, which is a typical form of IG FET, scaling for the miniaturization of the device has been rapidly progressed for high speed and high integration of the device, but the channel length is reduced while the power supply voltage is kept constant. As the electric field strength is increased, it adversely affects the FET characteristics.
즉, 채널길이에 큰 의존성을 갖는 스레시홀드 전압이 채널길이의 감소와 더불어 미세한 채널길이 변화에 대하여도 크게 변동됨으로써 회로의 동작 마진이 작아지거나 불량율이 늘어나는 요인이 되었고 이러한 스레시홀드 전압의 저하를 방지하거나 변동폭을 줄이기 위해 기판의 불순물 농도를 높이거나, 소오스, 드레인 확산층을 엷게 만드는 방식이 일반적으로 유효하게 행하여 지고 있다.That is, the threshold voltage having a large dependence on the channel length fluctuates with the decrease of the channel length and also with the small change in the channel length, thereby reducing the operating margin of the circuit and increasing the defective rate. In order to prevent or reduce the variation, a method of increasing the impurity concentration of the substrate or making the source and drain diffusion layers thin is generally performed effectively.
또한 MOS FET의 미세화에 따라 드레인 전압에 의한 드레인 공핍층의 확대와 소오스영역으로의 침투에 의해 소오스-기판간의 장벽전위를 감소시켜 서브- 스레시홀드 특성을 열화시키고 소오스, 드레인 간의 펀치스루(Punchthrough)에 의한 리크 전류의 증대를 가져와 소자의 미세 동작에 악영향을 주고 있으며, 이러한 펀치스루를 방지하기 위해 채널 하부에 불순물을 주입하는 것이 유효하게 적용되어 왔다.In addition, as the MOS FET becomes smaller, the barrier potential between the source and the substrate is reduced by the expansion of the drain depletion layer due to the drain voltage and the penetration into the source region, thereby degrading the sub-threshold characteristics, and punch-through between the source and the drain. Increasing the leakage current caused by) causes adverse effects on the microscopic operation of the device. In order to prevent such punchthrough, injecting impurities into the lower portion of the channel has been effectively applied.
그러나 무엇보다도 디바이스의 미세화에 따라 드레인 공핍층에 나타난 고전계에 의한 소위 '핫 케리어 효과(Hot-Carrier effects)'가 문제가 되고 있다.However, above all, as the device becomes smaller, so-called 'hot-carrier effects' caused by high electric fields appearing in the drain depletion layer become a problem.
즉, 채널중의 캐리어가 드레인 부근의 고전계에 의해 가속되어 실리콘의 에너지 밴드의 갭을 넘는 에너지를 얻게되고 충돌전리에 의해 새로운 전자, 정공을 형성시킨다. 이들 전자의 대부분은 드레인에 흡입되지만 일부는 게이트 절연막에 주입되며, 생성된 정공은 기판내로 흘러 기판전류로 되거나 일부는 게이트 절연막으로 주입된다. 게이트 절연막에 주입된 전자, 정공은 절연막에 포획되어, 결국 실리콘-절연막 계면에 준위를 생성시켜 스레시홀드 전압을 변화시키고 상호 콘덕턴스를 저하시키게 된다.That is, carriers in the channel are accelerated by the high electric field near the drain to obtain energy beyond the gap of the energy band of silicon and form new electrons and holes by collision ionization. Most of these electrons are sucked into the drain, but some are injected into the gate insulating film, and the generated holes flow into the substrate to become a substrate current or some are injected into the gate insulating film. The electrons and holes injected into the gate insulating film are trapped by the insulating film, thereby generating a level at the silicon-insulating film interface, thereby changing the threshold voltage and lowering the mutual conductance.
따라서 이러한 핫 캐리어 효과에 의한 문제점을 해결하기 위하여 제안된 것이, 디바이스 내의 전계강도를 완화시키기 위해 저농도의 드레인 영역을 형성시켜주는 LDD(lightly doped drain) 구조이다.Therefore, what is proposed to solve the problem caused by the hot carrier effect is a lightly doped drain (LDD) structure that forms a low concentration drain region to mitigate the electric field strength in the device.
일반적인 종래의 LDD구조를 갖는 절연 게이트형 전계효과 트랜지스터의 부분 단면도를 보면 제1도와 같다. 제1도를 참조하여 그 제조공정을 N채널 MOS구조에 대하여 살펴보면 아래와 같다.A partial cross-sectional view of an insulated gate field effect transistor having a general conventional LDD structure is shown in FIG. 1. Referring to FIG. 1, the manufacturing process of the N-channel MOS structure is as follows.
P형 반도체 기판(11)상에 게이트 산화막(12)이 형성되고, 그 위에 폴리 실리콘층(13)이 형성되어 일반적인 사진식각기술에 의해 패터닝된다. 다음에 비교적 저가속 전압과 저 농도로 인이온(P+) 또는 비소이온(As+)이 게이트전극(13)을 마스크로 하여 이온주입되어 n-영역(14)이 자체 정렬적으로 형성된다. 이어서 SiO2산화막층을 CVD방법으로 증착한 후 반응성 이온식각(RIE)에 의해 이방성 식각을 행하여 게이트전극(13) 측벽에 산화막 스페이서(15)를 형성시킨다. 이어서 고가속전압과 고농도로 비소이온(As+)이 게이트전극(13)과 산화막 스페이서(15)를 마스크로 하여 이온주입되어 n+영역(16)이 자체 정렬적으로 형성되어 n-영역(14)을 포함한 소오스, 드레인 영역이 형성된다. 상술한 LDD구조에서 드레인 영역을 향해 이동하는 캐리어 전자들은 P형기판(11)과 n-영역(14)간의 P-n-접합과 n-영역(14)과 n+영역(16)간의 n--n+전압과 마주침에 따라 동일한 드레인 전압에 대해 접합표면 근처의 전제강도가 n-영역이 없는 종래의 절연 게이트형 FET에 비해 현저히 감소한다.A gate oxide film 12 is formed on the P-type semiconductor substrate 11, and a polysilicon layer 13 is formed thereon and patterned by a general photolithography technique. Subsequently, phosphorus ion (P +) or arsenic ion (As +) is ion-implanted using the gate electrode 13 as a mask at a relatively low speed voltage and low concentration, so that the n-region 14 is formed in a self-aligned manner. Subsequently, the SiO 2 oxide layer is deposited by CVD, and then anisotropic etching is performed by reactive ion etching (RIE) to form the oxide spacer 15 on the sidewall of the gate electrode 13. Subsequently, at high acceleration voltage and high concentration, arsenic ions (As + ) are ion-implanted using the gate electrode 13 and the oxide spacer 15 as a mask so that the n + regions 16 are self-aligned to form n − regions 14. A source and a drain region including) are formed. To move towards the drain region in the above-described LDD structure, carrier electrons are P-type substrate 11 and n-n between the region 14 and the n + region 16-region 14 between the Pn-junction and the n -n As a result of encountering the positive voltage, the overall strength near the junction surface for the same drain voltage is significantly reduced compared to conventional insulated gate FETs without the n − region.
그러나 일반적으로 LDD구조는 제조공정이 복잡한 뿐만아니라 저농도 영역에 의한 기생저항이 증가하여 드레인 전류의 감소를 가져오기 때문에 일정한 전압을 유지하기 위해 많은 전력이 소비되는 단점이 있다. 또한 증가된 전류특성을 얻기 위하여 채널의 길이를 축소시켜 가지만 펀치스루의 발생의 위험이 있을 뿐만 아니라 실리콘 기판 표면에서의 게이트 전극에 의한 수직방향 전제가 증대되어 반전층내의 캐리어가 산란을 일으켜 캐리어의 이동도가 저하되거나 속도 포화 현상에 의해 전류구동력은 크게 향상되지 않는다. 또한 상기의 종래 기술에 의하면 산화막으로 게이트 스페이서 및 게이트 절연막을 사용함에 따라 트랜지스터의 저체 캐퍼시턴스가 낮아 전류구동력도 저하되거 반응성이온 식각시 실리콘에 대한 산화막의 에칭선택비가 낮아 실리콘 기판 표면에 데미지(damage)를 주는 등 많은 문제점을 내포하고 있는 것이 사실이다.However, in general, the LDD structure is not only complicated in the manufacturing process but also has a disadvantage in that a lot of power is consumed to maintain a constant voltage because parasitic resistance due to the low concentration region is increased, resulting in a decrease in the drain current. In addition, the length of the channel is reduced to obtain the increased current characteristics, but there is a risk of punch-through, and the vertical premise by the gate electrode on the surface of the silicon substrate is increased, causing carriers in the inversion layer to scatter and The current driving force is not greatly improved by the mobility decrease or the speed saturation phenomenon. In addition, according to the related art, as the gate spacer and the gate insulating film are used as the oxide film, the low capacitance of the transistor decreases the current driving power, and the etching selectivity of the oxide film to silicon during the reactive ion etching is low. It is true that there are many problems such as damage.
채널길이가 1k㎛에서 1㎛에 이르는 미세 MOS FET에서의 전류 구동력에 관한 스케일링에 관하여, 오오사카 대학의 야마다 오카에 의해 발표된 'Physical Limitations of ultra small MOSFETS'(『solid state Devices and Materials』Part II. 1990.pp 825∼828)에도 잘나타나 있지만, 일반적으로 인핸스먼트형(enhancement)MOS FET에 있어서 드레인 전류는 다음과 같이 주어진다.On the scaling of the current driving force in micro MOS FETs with channel lengths from 1 k to 1 μm, the Physical Limitations of ultra small MOSFETS (Solid State Devices and Materials) published by Yamada Oka of the University of Osaka (Part II) 1990.pp 825 to 828), but in general, for an enhancement MOS FET, the drain current is given by
i) 비포화 영역i) unsaturated region
ll) 포화영역ll) Saturation Zone
Ids : 드레인 포화전류Ids: Drain Saturation Current
(Ref. 『Microdelectronics』.JACOB MILLMAN.ARVIN GRABEL. 1979. Ch4)(Ref.``Microdelectronics ''. JACOB MILLMAN.ARVIN GRABEL. 1979. Ch4)
여기서, 드레인 전류는 MOS FET의 구조가 미세화됨에 따라 게이트 절연막에 의한 캐퍼시턴스에 크게 영향을 받는다는 것을 알 수 있다.Here, it can be seen that the drain current is greatly influenced by the capacitance caused by the gate insulating film as the structure of the MOS FET is miniaturized.
캐퍼시턴스는 캐퍼시터의 한쪽 전극상의 전하량을 두 전극간의 전위차로 나눈 값으로서 거리(두께)와 관련된 구조와 유전율과 관련된 재로에 의해 정하여 진다.Capacitance is the amount of charge on one electrode of the capacitor divided by the potential difference between the two electrodes, which is determined by the structure associated with the distance (thickness) and the material associated with the permittivity.
따라서 본 발명의 목적은 산화막을 게이트 절연막으로 사용한 종래의 LDD구조에 있어서 게이트절연막의 구조를 개선함으로써 게이트전극과 반도체기판간의 캐퍼시턴스를 증가시켜 트랜지스터의 전류구동력을 향상시키고 기판의 손상을 방지하여 신뢰성이 높은 절연 게이트형 전계효과 트랜지스터 및 그 제조방법을 제공함에 있다.Therefore, an object of the present invention is to improve the current driving force of the transistor by preventing the damage of the substrate by increasing the capacitance between the gate electrode and the semiconductor substrate by improving the structure of the gate insulating film in the conventional LDD structure using the oxide film as a gate insulating film The present invention provides a highly reliable insulated gate field effect transistor and a method of manufacturing the same.
상기의 목적을 달성하기 위하여, 본 발명은 반도체기판의 표면 근방에 형성된 소오스, 드레인 영역으로부터 채널영역쪽으로 엷게 도프된 저농도 영역이 형성되어 있는 절연 게이트형 전계효과 트랜지스터에 있어서, 상기 반도체기판과 게이트전극 사이에 형성되는 게이트 절연막의 구조를 게이트 전극 하부 중앙부근에서는 제1산화막, 제1유전체막, 제2산화막으로 형성시키고, 게이트 전극 하부 중앙부에서 소정의 거리만큼 떨어진 지점으로부터 게이트 전극 측벽에 형성된 제2유전체막, 산화막스페이서의 끝 부분까지는 제1산화막, 제1유전체막, 제2유전체막으로 형성시킴으로써 달성된다.In order to achieve the above object, the present invention provides an insulated gate field effect transistor having a lightly doped low concentration region formed from a source and a drain region formed near the surface of a semiconductor substrate toward a channel region, wherein the semiconductor substrate and the gate electrode are formed. A second insulating film is formed between the first oxide film, the first dielectric film, and the second oxide film near the center of the lower gate electrode, and is formed on the sidewall of the gate electrode from a point separated by a predetermined distance from the center of the lower gate electrode. The end portion of the dielectric film and the oxide film spacer is achieved by forming the first oxide film, the first dielectric film, and the second dielectric film.
이하, 본 발명의 원리가 구체화된 실시예를 첨부한 도면 제2도의 (A)∼(D)를 참조하여 상세히 설명하겠다.DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to (A) to (D) of the accompanying drawings.
(A)도는 반도체기판(21)상에 실리콘 산화막(22)을 얇게 증착시킨 후, 실리콘산화막보다 유전율이 큰 실리콘나이트라이드, 폴리실리콘등의 유전체막(23)을 형성시키고, 다시 실리콘산화막(24)을 증착시키고, 그 위에 폴리실리콘층을 형성시킨 뒤, 일반적인 사진식각기술에 의해 포토레지스트층(26)을 이용하여 게이트전극(25)를 형성시킨 것을 나타낸 단면도이다. 게이트 절연막의 구조를 유전율이 큰 유전체막을 사이에 둔 샌드위치 구조를 형성시킴으로서 게이트전극(25)과 반도체기판(21)간의 캐패시턴스가 증가하게 되는 효과가있다.(A), after a thin deposition of the silicon oxide film 22 on the semiconductor substrate 21, a dielectric film 23 such as silicon nitride and polysilicon having a higher dielectric constant than the silicon oxide film is formed, and then the silicon oxide film 24 ), A polysilicon layer is formed thereon, and a cross-sectional view showing the formation of the gate electrode 25 using the photoresist layer 26 by a general photolithography technique. The capacitance between the gate electrode 25 and the semiconductor substrate 21 is increased by forming a sandwich structure having a dielectric film having a high dielectric constant between the structure of the gate insulating film.
또한 상기 반도체기판(2l)은 NMOS의 경우 P형 기판을 사용하며 PMOS의 경우 N형기판을 사용하게 되며, 웰(Wel1) 구조를 수반하는 CMOS, BiCMOS등에는 웰이 형성된 반도체기판을 사용함은 물론이다. 또한 폴리실리콘층 형성후 산화막을 소정두께 만큼 형성시킨 뒤 사진식각 기술에 위해 게이트전극(25)을 형성시킬 수도 있다. 이것은 후속되는 이온주입 공정시 블록킹의 역할을 강화시키기 위함이다.In addition, the semiconductor substrate 2l uses a P-type substrate in the case of an NMOS and an N-type substrate in the case of a PMOS, and a semiconductor substrate in which a well is formed is used in a CMOS, BiCMOS, etc., which has a well structure. to be. In addition, after the polysilicon layer is formed, an oxide film may be formed by a predetermined thickness, and then the gate electrode 25 may be formed for a photolithography technique. This is to enhance the role of blocking in the subsequent ion implantation process.
(B)도는 (A)도의 공정 후 이온주입을 실시하여 N-영역(27) 혹은 P-영역이 형성된 것이다.(B) shows the formation of the N-region 27 or the P-region by ion implantation after the process of (A).
(C)도는 N-영역(27) 형성후 7:1 SBOE로 실리콘 산화막(24)를 습식에칭한 것을 나타낸 도면이다.(C) shows the wet etching of the silicon oxide film 24 with 7: 1 SBOE after the formation of the N-region 27.
이때 게이트전극(25)의 엣지 부분에서 실리콘 산화막(24)이 언더컷되며 게이트전극(25)이 들리지 않을 정도로 충분히 언더컷 시킨다. 또한, 유전체막(23)은 에칭스트퍼로서의 역할을 한다.At this time, the silicon oxide film 24 is undercut at the edge portion of the gate electrode 25 and sufficiently undercut so that the gate electrode 25 is not lifted. In addition, the dielectric film 23 serves as an etching stripper.
(D)도는 실리콘 산화막(24)을 언더컷 시킨후 폴리실리콘, 실리콘 나이트라이드 등의 유전체층(29)을 언더컷된 부분이 완전히 메워지도록 충분히 데표지션한 후, 산화막을 충분히 데포지션한 후, 반응성 이온식각(Reaction Ion Etchiug)에 의해 게이트전극 측벽에 산화막 스페이서(30)을 형성시키고, 이온주입을 실시하여 N+영역(28) 혹은 P+영역이 형성된 것을 나타낸 것이다. 이때 산화막의 두께에 따라 산화막스페이서(30)의 폭을 원하는 수준으로 조절하며, 단화막스페이서(30) 형성을 위한 에칭시 실리콘에 대한 산화막의 에칭선택비가 6:1정도로 낮기 때문에 실리콘기판 표면에 대한 데미지가 에칭선택비가 높은 유전체층의 존재로 그 만큼 감소된다. 또한 (C)도의 실리콘산화막(24) 언더컷 공정 후 얇은 산화막을 형성시켜 줄 수도있다.(D) shows that after the undercut of the silicon oxide film 24, the dielectric layer 29, such as polysilicon and silicon nitride, is sufficiently labeled so that the undercut portion is completely filled, and then the oxide film is sufficiently deposited, followed by reactive ions. The oxide spacer 30 is formed on the sidewalls of the gate electrode by etching (Ion Etchiug), and ion implantation is performed to form the N + region 28 or the P + region. At this time, the width of the oxide film spacer 30 is adjusted to a desired level according to the thickness of the oxide film, and the etching selectivity of the oxide film to silicon during the etching for the formation of the shoe film spacer 30 is about 6: 1, which is low. Damage is reduced by the presence of a dielectric layer having a high etching selectivity. In addition, a thin oxide film may be formed after the silicon oxide film 24 undercut process shown in (C).
이것은 유전체층(29) 증착 후 게이트 폴리 실리콘의 도펀트가 유전체층(29)으로 확산되는 것을 방지하는 역할을 한다.This serves to prevent diffusion of the gate polysilicon dopant into the dielectric layer 29 after the dielectric layer 29 is deposited.
또한 언더컷 공정 후 얇은 산화막을 형성시킨 후 소정의 시간이 경과한 후 제거함으로써 폴리실리콘층으로 확장된 산화막이 같이 제거되기 때문에 언더컷된 부위의 두께를 증가시켜 핫 캐리어 효과를 감소시킬 수있다.In addition, since a thin oxide film is formed after the undercut process and then removed after a predetermined time, the oxide film expanded to the polysilicon layer is removed together, thereby increasing the thickness of the undercut portion, thereby reducing the hot carrier effect.
제3도의 (A),(B) 그래프는 본 발명에 의하여 게이트 전극의 길이가 1.1㎛이고, 스페이서 길이가 0.2㎛이며, 언더컷된 부위의 길이가 0.3㎛, 두께가 50Å인 NMOS의 전류구동력을 종래의 방법에 의해 형성된 것과 비교한 그래프이다.The graphs (A) and (B) of FIG. 3 illustrate the current driving force of an NMOS having a gate electrode length of 1.1 μm, a spacer length of 0.2 μm, a length of an undercut portion of 0.3 μm, and a thickness of 50 mA according to the present invention. It is a graph compared with the thing formed by the conventional method.
이상의 실시예에서 나타난 듯이 본 발명은 게이트절연막의 구조를 개선하고 유전율이 높은 재료를 사용함으로써, 게이트 전압에 따른 전계효과가 액티브영역의 넓은 범위까지 작용하고, 또한 캐퍼시턴스의 증가에 의해 트랜지스터의 온-오프특성이 향상될 뿐만 아니라 높은 전류구동력을 얻을 수 있다.As shown in the above embodiment, the present invention improves the structure of the gate insulating film and uses a high dielectric constant material so that the field effect according to the gate voltage acts over a wide range of the active region, and the capacitance of the transistor is increased by increasing the capacitance. Not only the on-off characteristic is improved but also a high current driving force can be obtained.
Claims (14)
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