KR950003796Y1 - Apparatus for buffering luminance signal - Google Patents

Abstract

No content.

Description

Luminance signal buffer circuit

1 is a conventional luminance signal buffer circuit diagram.

2 is a luminance signal buffer circuit diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10: V / C processing circuit 20: matrix circuit

11, 12, 14: first to third buffer section 13: blanking signal processing section

15: clipping section TR1 to TR6: transistor

R1 to R13: resistor D1: diode

ZD1 to ZD3: Zener Diode C1: Capacitor

a: blanking signal input terminal

The present invention relates to a video signal processing system such as a television or a video tape recorder, and more particularly, a luminance signal that improves the resolution by configuring a buffer circuit for preventing deterioration of the luminance signal at the cathode ray tube (CRT) drive front end. It relates to a buffer circuit.

FIG. 1 shows a conventional luminance signal buffer circuit, and a video / chroma which makes a composite video signal into color difference signals RY, GY, BY and luminance signal Y (hereinafter referred to as “V / C”). The luminance signal (-Y) inverted from the processing circuit 10 is matrixed with the color difference signals RY, GY, and BY in the matrix circuit 20 via the buffer transistor TR1, and R ( Outputs Red, G (Green), B (Blue) signals.

However, at this time, in the process of supplying the luminance signal to the matrix circuit 20, the luminance signal corresponding to the color difference signals RY, GY, and BY for matrixing should be sent from the transistor TR1. Becomes weak.

That is, since a signal must be sent from one driving stage to three driving stages, the signal level applied to each driving stage is lowered.

Therefore, since the attenuation of the Y signal applied to the matrix circuit 20 was inevitable, there was also a problem that the resolution also decreased.

The object of the present invention is to solve the above problems, and an object of the present invention is to construct a buffer circuit for preventing the luminance signal attenuation deterioration at the CRT driving stage, thereby preventing the degradation of the luminance signal and improving the resolution. In providing a circuit.

A feature of this invention for achieving this object is a V / C processing circuit which converts a composite video signal into a luminance signal and a color difference signal, and matrixes the color difference signal and the luminance signal from the V / C processing circuit to R, G. In the video signal processing system comprising a matrix circuit for generating a B-color signal, the first and second buffers for buffering the luminance signal applied from the V / C processing circuit, and the blanking signal input terminal is connected to the blanking A blanking signal processing unit which is driven when a signal is input to control an operation of the second buffer unit and processes a blanking signal, and is connected to the second buffer unit to correspond to the matrixing of the matrix circuit according to the operation of the second buffer unit A third buffer portion for buffering a signal, and a clipping portion connected to the third buffer portion for limiting unnecessary noise components or signal components higher than the synchronization tip level. It has the property that the luminance signal buffer circuit.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a luminance signal buffer circuit according to the present invention, wherein the first and second buffer units 11 buffer the luminance signals in the V / C processing circuit 10 that makes the composite video signal into the luminance signal and the color difference signal. , (12).

A blanking signal processor 13 is connected between the first and second buffer units 11 and 12 and the blanking signal input terminal a to operate the second buffer unit 12 according to application of a blanking signal. Control and process the blanking signal.

In addition, the second buffer unit 12 and the voltage source B + are connected to a third buffer unit 14 which buffers a luminance signal according to the operation of the second buffer unit 12 and supplies it to the matrix circuit 20. Let's do it.

The third buffer portion 13 is coupled to a clipping portion 15 of zener diodes ZD1 to ZD3 in which unnecessary noise higher than the synchronous front end level limits the signal of the level.

On the other hand, the first buffer unit 11 is a resistor (R3) connected to the base and the voltage source (B +) connected to the bias and voltage distribution resistor (R1), (R2) connected to the V / C processing circuit 10 A buffer transistor C1 connected to the buffer buffer C1, wherein the second buffer unit 12 has a base side connected to an emitter side of the transistor TR1 and a collector side connected to a voltage source B +. It is composed of

The blanking signal applying unit 13 is connected to a base side via bias and voltage distribution resistors R5 and R6 connected to a blanking signal input terminal a. The first and second buffer units 11, And a switching transistor TR3 connected to the collector side via a reverse voltage prevention diode D1 to a resistor R4 connected between the plurality of transistors 12.

In addition, the third buffer portion 14 has a base side connected to the voltage source B + with its resistors R8 to R10 respectively, and according to the operation of the transistor TR2, the color difference signals RY and GY. ), (BY) and luminance signal buffer transistors TR4 to TR6 for supplying luminance signals for matrixing in the matrix circuit 20.

The effect of this invention configured as described above is as follows.

First, the V / C processing circuit 10 outputs the inverted luminance signal (-Y) in order to easily generate the R, G, and B color signals in the matrix circuit 20, and the blanking signal is not applied to the circuit operation. The description will be divided into cases and cases where they are authorized.

1) When the level of the luminance signal applied from the V / C circuit 10 is high without the blanking signal applied.

In this case, since the transistor TR1 is of PNP type, the transistor TR2 is not turned on, and the transistor TR2 is turned on. Accordingly, each of the transistors TR4 to TR6 of the PNP type located in the third buffer portion 14 is not turned on. The voltage from the voltage source B + is supplied to the matrix circuit 20 by dividing the voltage only by the resistors R1 to R13. The high level signal is limited and supplied.

In this case, the matrix circuit 20 obtains R, G, and B color signals by matrixing RY-(-Y), BY-(-Y), and GY-(-Y), respectively, and the reason why the -Y signal is used is V. This is because the luminance signal (-Y) inverted by the / C processing circuit 10 is output.

2) When the luminance signal level applied from the V / C processing circuit 10 is low without a blanking signal being input.

In this case, as the transistor TR1 is turned on, the transistor TR2 is turned off, and each of the transistors TR4 to TR6 is turned on so that all the power from the voltage source B + flows to ground. The voltage level applied to is gradually stored than in the case of 1). In this case, R, G, and B colors are output by the same matrix as in the case of 1), but the output level is gradually attenuated.

3) When a blanking signal is applied.

Since the transistor TR3 is turned on when the blanking signal is applied, the transistors TR2 are turned off regardless of whether the transistor TR1 is turned on or off. Thus, the transistors TR4 to TR6 are turned on to form the matrix circuit 20. No voltage is applied and there is no output.

That is, the input of the blanking signal is a blanking period, so that the image is lowered below the hog level, thereby suppressing the application of voltage to the matrix circuit 20 to be effective blanking.

As described above, the present invention configures each of the buffer units 11, 12, and 14 at the emitter stage of the matrixing transistor to effectively prevent the attenuation of the luminance signal of the CRT driving stage. By restricting unnecessary noise and signal components beyond the synchronous front end, decay deterioration of the luminance signal applied to the matrix circuit 20 is prevented.

As described above, this design has the effect of improving the resolution by constructing a buffer circuit at the CRT driving stage to buffer the luminance signal to prevent deterioration of the luminance signal.

Claims (6)

Matrix for producing R, G, and B color signals by matrixing the color difference signal and the luminance signal from the V / C processing circuit 10 and the V / C processing circuit 10 that converts the composite video signal into a luminance signal and a color difference signal. A video signal processing system including a circuit (20), comprising: first and second buffer parts (11) and (12) for buffering a luminance signal applied from the V / C processing circuit (10); It is connected to a blanking signal input terminal (a) and driven when a blanking signal is input to control the operation of the second buffer unit 12 and to process a blanking signal to the blanking signal processor 13 and the second buffer unit 12 A third buffer unit 14 connected to the third buffer unit 14 to buffer the luminance signal corresponding to the matrixing of the matrix circuit 20 according to the operation of the second buffer unit 12. And a clipping unit 15 for limiting unnecessary signal components higher than the synchronous tip level. A luminance signal buffer circuit. According to claim 1, The first buffer unit 11 is connected to the bias and voltage distribution resistors (R1), (R2) connected to the V / C processing circuit 10, the base side is connected to a predetermined voltage source ( A luminance signal buffer circuit comprising a buffer transistor (TR1) having an emitter side connected to a resistor (R3) connected to B +) and a buffer capacitor (C1) connected to a resistor (R3). 2. The buffer circuit of claim 1, wherein the second buffer unit 12 includes a buffer transistor TR2 having a base side connected to an emitter side of the transistor TR1 and a collector side connected to a predetermined voltage source B +. A luminance signal buffer circuit. The blanking signal processor 13 of claim 1, wherein the biasing and voltage distribution resistors R5 and R6 connected to the blanking signal input terminal a, the first and second buffer units 11, A reverse voltage preventing diode D1 connected through a resistor R4 connected between the plurality of transistors 12 and a switch connected to the resistors R5, R6, and diode D1 and 'turned on' according to a blanking signal input. And a transistor TR3 for the luminance signal buffer. 2. The third buffer unit (14) according to claim 1, wherein the third buffer portion (14) has a base side connected to the resistors (R8) to (R10) so that the color difference in the matrix circuit (20) in accordance with the operation of the second buffer portion (13). And a buffer transistor (TR4) to (TR6) for buffering the luminance signal in correspondence with the matrixing of the signal. 2. The luminance canceling device according to claim 1, wherein the noise removing unit (15) comprises zener diodes (ZD1) to (ZD3) having an emitter side of the transistors (TR4) to (TR6) connected to a cathode side, respectively. Signal buffer circuit.