KR950003524B1 - Address filter unit for carrying out address filter processing among plurality of network and method thereof - Google Patents

Abstract

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Description

An address filter device and method, a relay device and a bridge device using the address filter device, and a memory circuit for use in the address filter device

1 is a system configuration diagram showing the configuration of a network system to which the present invention is applied.

2 is an explanatory diagram showing an outline of frame relay.

3 is a block diagram showing the configuration of a bridge device.

4 is an explanatory diagram showing an overview of the division and reassembly process.

5 is an explanatory diagram showing a configuration of a cell.

Explanatory drawing which showed the structure of the entry table of FIG.

7 is a circuit diagram of a hash circuit.

8 is a block diagram showing the configuration of a routing control section according to the first embodiment of the present invention.

9 is a state diagram showing the operation of the path controller.

10 is a timing diagram showing a pipeline operation of a hash circuit.

11 is a state diagram showing the operation of the hash circuit.

12 is a state diagram showing the operation of the search process.

13 is a state diagram showing the operation of the registration circuit.

14 is a timing diagram showing timing of updating an aging timer.

15 is a state diagram showing the operation of updating the aging timer.

16 is a system configuration diagram showing a configuration of a network system according to a second embodiment of the present invention.

Fig. 17 is an explanatory diagram showing the structure of the entry item table.

18 is a block diagram showing the configuration of a bridge device.

19 is a time difference art showing the operation of the D-RAM used in the memory circuit.

20 is a block diagram showing the structure of a database using a memory circuit.

21 is a time difference art showing the operation of the memory circuit.

22 is a state diagram showing the operation of the memory circuit.

23 is an explanatory diagram showing a field configuration of stored data.

Fig. 24 is a block diagram showing the construction of the memory circuit according to the third embodiment of the present invention.

25 is an explanatory diagram showing the operation principle of a memory circuit.

FIG. 26 is an explanatory diagram showing an example of a process of correcting memory data; FIG.

27 is a diagram showing chip division of a memory circuit.

28 is a block diagram showing a configuration of a bridge device.

* Explanation of symbols for main parts of the drawings

1 ~ 3: High Speed Relay LAN 5 ~ 8: FDDI

10: loop access portion 11-14: bridge device

111: relay control unit 112: FDDI control unit

114: path controller 1111: split controller

1112: reassembly control unit 1114, 2114: entry item table

1121: acceptance buffer 1125: transmission buffer

1115: bridge device processor 1137: hash sub circuit

11135: aging timer circuit 11136: state management circuit

11137: hash circuit 11138: search circuit

11139: Registration circuit

The present invention relates to an address filtering method and apparatus for use in a bridge device or the like for connecting a network.

Packet relaying is usually performed as follows. The bridge device includes a entry table for storing the position where the terminal is located. The bridge device refers to this entry table and the destination address of the incoming packet that determines whether the packet should be relayed or discarded. That is, the bridge device executes the address filter process.

More specifically, the packet is relayed when the destination terminal of the packet is in the direction of some other LAN or when the purpose of the packet is unknown, and the packet is discarded when the packet is in the introduction direction.

A method of dynamically learning the contents of the entry table has already been disclosed. As an example, the technique described in JP-A-64-39852 is known.

According to this technique, an introduction packet is mentioned, and its source address and terminal position are registered in the entry table for performing learning.

The entry table is periodically reviewed for the following purposes.

① prevents the entry table from being completely filled by learning, and

② It responds flexibly to the movement of terminal position.

The registration of the terminal that does not transmit or accept the packet is cleared from the entry table.

However, according to the above-mentioned prior art, the periods are separated, and the registration period of each terminal is stored by corresponding to the registration contents so that only terminals registered in the current period and the preceding period become valid, and terminals registered before the preceding period are Erased. Therefore, the registration of the terminal that has not performed transmission or acceptance of the packet is canceled. Therefore, the learning contents executed during the period before the preceding cycle are erased. As a result, there is a problem that the number of entries in the entry table is insufficient at the start of each cycle, leading to a decrease in the accumulation rate.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address filtering method and apparatus which can prevent the entry item table from being completely filled by learning without reducing the redundancy rate, and can flexibly cope with the movement of the terminal position.

Another object of the present invention is to provide an address filtering method and apparatus which can improve the processing efficiency of the address filter processing.

In order to achieve the above object, the present invention provides an address filter apparatus for performing address filter processing between a plurality of circuits by using address information extracted from an introduction information frame registered in a entry table. The address filter apparatus includes a timer provided in correspondence with each address information registration, a timer updating apparatus that sequentially and intermittently raises each timer value, and an address corresponding to the timer from the entry table when the timer value is greater than or equal to a predetermined value. It is composed of a device for deleting registration of information.

Further, in order to achieve the above object, the present invention provides an address filter apparatus for performing address filter processing between a plurality of circuits by using address information extracted from an introduction information frame registered in a entry item table. The address filter device includes a timer provided in correspondence with each address information registration, a timer update device that sequentially and intermittently raises each timer value, a starter that starts the timer update device at a predetermined cycle ΔT, and a time value is a predetermined value. And a device for canceling registration of address information corresponding to a timer from a write item table when it is larger or equal.

The present invention also provides an address filtering method for performing address filter processing between a plurality of networks by searching for address information extracted from an introduction information frame registered in the entry table. The address filtering method is a function of the destination address (a) taken out from the introduction information frame when retrieving the entry table or the source address taken out from the entry information frame when registering in the entry entry table (fi (a), i = 1 to 1). a first step of sequentially generating n) of the entry item table; a second step of determining whether address information of an address of the entry item table generated in the first step should be registered; and a entry item generated in the first step. And a third step of determining whether the address information registered in the address of the table is desired address information. The first, second and third stages operate as pipelines.

1) 논리 전송로 또는 물리적 전송로로 구성된 중계선 회로망 간에서 어드레스 필터 처리를 실행하는 어드레스 필터장치를 제공한다. 이 어드레스 필터장치는 분기선 LAN에서 기입항목표로 들어오는 어드레스 정보의 등록과 중계회로망이 N전송로에서 기입항목표로 들어오는 어드레스 정보의 등록 그리고 기입항목표로부터 어드레스 정보의 검색을 실행하는데 대하여 우선순위를 결정하는 우선순위 결정장치와, 결정의 결과에 따라 처리를 실행하는 실행장치로 구성된다.In addition, the present invention searches for branch information LAN and N (N

1) An address filter apparatus for performing address filter processing between a relay network consisting of a logical transmission path or a physical transmission path is provided. This address filter apparatus determines priority of registration of address information coming into the entry item table from the branch line LAN, registration of address information coming from the N transmission line into the entry item table, and retrieval of address information from the entry item table. A priority determining device and an execution device for executing a process in accordance with the result of the determination.

1) 논리전송로 또는 물리적 전송로로 구성된 중계선 회로망간에서 어드레스 필터처리를 실행하는 어드레스 필터장치를 제공한다. 이 어드레스 필터장치는 분기선 LAN에서 기입항목표로 들어오는 어드레스 정보의 등록과 중계 회로망의 N전송로에서 기입항목표로 들어오는 어드레스 정보의 등록 그리고 기입항목표로부터 어드레스 정보의 검색을 실행하기 위한 우선 순위를 결정하는 우선순위 결정장치와, 기입항목표에 등록할시에 도입정보 프레임으로부터 빼낸 소오스 어드레스 또는 기입항목표로부터 검색시에 도입정보프레임으로 빼낸 목적어드레스 (a)의 함수 (fi(a), i=1~n)를 기입항목표의 어드레스로 순차적으로 발생시키는 어드레스 발생장치와, 등록시에 기입항목표에서 어드레스 발생장치에 의해 순차적으로 발생한 어드레스들중에서 등록어드레스를 결정하는 등록어드레스 후보결정장치와, 기입항목표에서 어드레스 발생장치에 의해 발생된 어드레스로부터 원하는 어드레스 정보를 검색하는 검색장치와, 그리고 어드레스 발생장치에 의해 i번째 어드레스를 발생시키는 처리, 등록 어드레스 후보결정장치에 의해 i-1번째 어드레스를 결정하는 처리 또는 검색장치에 의해 i-1번째 어드레스를 검색하는 처리를 평행동작시키는 장치로 구성된다.In addition, in order to achieve the above-described object, the present invention provides branch line LAN and N (N) by retrieving address information extracted from an introduction information frame registered in the entry table to improve the processing efficiency of the address filter process.

1) An address filter apparatus for performing address filter processing between a trunk line network composed of a logical transmission path or a physical transmission path is provided. The address filter apparatus determines the priority for registering address information coming into the entry item table from the branch line LAN, registering the address information entering the entry item table from the N transmission path of the relay network and searching the address information from the entry item table. Function of the priority addressing device and the target address (a) extracted from the introduction information frame at the time of registration in the entry item table or the introduction address frame at the time of retrieval from the entry item table (fi (a), i = 1 an address generator for sequentially generating ˜n) to addresses in the write item table, a registration address candidate determining device for determining a registration address among addresses sequentially generated by the address generator in the write item table at registration, and a write item table From the address generated by the address generator A retrieval device for retrieving the source information, and a process for generating the i-th address by the address generator, a process for determining the i-1th address by the registration address candidate determination device, or a retrieval device for the i-1 address It is composed of an apparatus for parallel operation of the searching process.

In order to achieve the above-described object, the present invention provides a memory device, a comparator for determining a data generation mode according to data input from the outside and data read out from the memory device, and a data generation mode determined by the comparator. A data processing unit for generating data to be written at an address into which data is read from the memory element, and a condition determined from the relationship between input data and read data is 1 or less, and one of the predetermined conditions for reading data from the memory element is A memory circuit comprising an address generator that sequentially generates addresses in accordance with a predetermined rule is provided.

The bridge device in one embodiment of the present invention is described below.

First, a network system using the bridge device according to the present invention will be described.

1 shows the configuration of a network system.

In Fig. 1, reference numerals 1 to 3 designate norwoods connected to a high speed local area network (LAN) (600 Mbps to 2.4 Gbps, 150 Mbps 4 to 16 multiplex), and 5 to 8 are for example. Indicates fiber distributed data interfaces (FDDI) to accommodate 802 family LANs. Norwood 1 accommodates up to four ports using bridge arrangements 11-14 as ports.

As for the bridge device, for example, the bridge device 11 is connected to the FDDI 5 and the high speed relay LAN 4.

FDDI 5 is connected to 802 family LANs 51 and 52. That is, the network system according to the present embodiment is composed of three LAN layers. In this case, both the 802 family LANs 51 and 52 and the FIID 5 are branched LANs of the bridge device 11. When 802 family LANs are directly connected to the bridge device 11, these connected LANs are branch LANs.

The bridge devices 11 to 14 determine whether a frame received from the FDDI is to be discarded or relayed by finding a relay path. For the frames to be relayed, the bridge devices 11 to 14 convert these frames into the data format of the high speed relay LAN 4 and transmit the result. The bridge devices 11 to 14 convert the data received from the high-speed relay LAN 4 back to the original data by FDDI frames (reassembly processing) and transmit the result (hereinafter referred to as path processing).

An outline of route processing will be described below based on the bridge device 11 connecting the high speed relay LAN 4 and the FDDI 5.

The high-speed relay LAN 4 is a multiplex multiplex by adopting a fixed-length cell system using a broadband ISDN transmission mode corresponding to multi-media transmission and a statistical multiplex using a predetermined number of cells corresponding to the amount of information. To realize.

2 shows the frame flow from FDDI 5 to FDDI 8 through high-speed relay LAN 4.

The bridge devices 11 and 21 store (learn) the positions of the FDDI norms present in the entry item tables 1114 and 2114 and perform the route processing with reference to the stored positions.

The entry items tables 1114 and 2114 express the direction in which the FDDI Norwood exists using the bridge device number of the high-speed relay LAN 4. In this embodiment, the bridge device numbers A and B are assigned to the bridge devices 11 and 21, respectively.

By the above arrangement, the entry in entry item 11 consists of a set of FDDI weight arrival control (MAC) addresses and bridge device numbers.

The bridge device 11 converts the frame received from the FDDI 5 into a cell of the transmission data format of the high-speed relay LAN 4 (division processing).

More specifically, the bridge device 11 decomposes the received frame into fixed-length cell units, adds a header composed of a source bridge device number, a target bridge device number, and the like to the cell unit, and transmits the result to the high-speed relay LAN 4. do.

The destination bridge device 21 (B) is a bridge device having the destination FDDI norm 81 (b) under its control, and is obtained by referring to the entry item table 2114 using the destination FDDI MAC address as a key. .

On the other hand, the accommodating bridge device 21 receives the cell transmitted to this bridge device, reassembles the cell into a frame (reassembly processing), and relays the result to the FDDI 8 under the control of the accommodating bridge device.

The path information (FDDI MAC address and bridge device number) is learned as follows.

The transmission bridge device 11 registers the source address a and a set of its own bridge device numbers A of frames received from the FDDI 5 in the entry item table 1114.

The swimming bridge device 21 registers the source address (a) and a set of transmission bridge device numbers (A) based on the cells received from the high-speed LAN 4 in the entry item table 2114.

In this embodiment, the entries in the entry tables 1114 and 2114 are erased by the aging timer (range 10 to 10 ⁶ sec) based on the IEEE 802.1 adjustment.

The bridge device and the path processing will be described in detail below.

3 shows the configuration of the bridge device 11.

In FIG. 3, reference numeral 10 designates a fast relay LAN loop access part belonging to the norwood. Reference numeral 11 denotes a non-ridge device, 111 denotes a relay control unit, and 112 denotes an FDDI control unit. 1111 indicates a splitting control unit that decomposes the frame received by the FDDI control unit 112 from the FDDI ring into cells, and transmits the cell in the high-speed relay LAN 4, and 1112 assembles the frame received from the loop access unit 10 into a frame. Instructs the reassembly control unit to transmit to the FDDI control unit 112. 1113 indicates a path control unit for learning the position of the station and filtering the relay frame, and 1114 indicates a target entry target.

In order to perform relaying in the bridge device, data format conversion between FDDI and fast relay LAN 4 is performed as in the second diagram.

First, a division process for decomposing an FDDI frame into cells and a reassembly process for reassembling the cells into an original frame will be described.

The division control unit 111 decomposes the accommodation FDDI frame stored in the accommodation buffer 1121 of the FDDI control unit 112 into cells, and transfers the cells (FIG. 4 (1)) to the loop access unit 10.

In the segmentation process, a cell header including a destination virtual channel identifier (VCI itself) is applied to one cell device to form a cell as in the fifth degree, where VCI represents the bridge device number. This is composed of a nord address and a port (bridge device) address, and the destination VCI for accommodating the destination terminal is obtained from the entry item table 1114.

Then, following the reassembly process, the reassembly control unit 1112 reassembles the cell devices disassembled by the transmission bridge device into the original frame in the receiving bridge device (FIG. 4 (2)). The reassembled frame is transmitted to the transmission buffer 1125 of the FDDI controller 112.

Now, the determination of the relay / discard and path processing for transmitting the cell to the bridge device accommodating the target terminal will be described.

The segmentation control unit 1111 receives the frame on the connected FDDI, retrieves the entry item table 1114 under the control of the path control unit 1113 using the destination MAC address DA as a key, and accepts the entry item table 1114. To obtain the VCI.

Based on the result of the above process, relaying or discarding is judged as follows.

① If the target VCI is the same as the source VCI, the DA is subject to its own bridge device control. Therefore, the tone is discarded without being transmitted to the high speed LAN.

If the destination VCI is not the same as the source VCI, the DA is controlled by another bridge device. Therefore, the tone is relayed without being sent to the high-speed LAN.

If there is no VCI, the frame is broadcasted to all bridge devices of the high-speed LAN, and the relayed frame passes through all FDDIs. This frame is thus relayed by all other bridge devices to the connected FDDI of these bridge devices. As a result, the frame can reach the desired destination norwood.

The bridge device related to this embodiment does not perform filtering downward. A bridge device that receives a cell broadcasted by the transmitting bridge device or by specifying a destination VCI reassembles all the received cells and relays the result to the FDDI connected to the bridge device.

Since the bridge device for transmitting a cell transmits the cells to the bridge device designated to receive the cells in the direction by determining the position of the destination norm, there is clearly a destination node under the control of the receiving bridge device. It is also clear that the destination nord exists in the FDDI because only one FDDI is connected to the bridge device.

The bridge device of this embodiment learns from all cells, including destined for another bridge device. This means that any bridge device connected to the trunk line LAN must have the same entry table. The reason why no downward filtering is required has already been described above with respect to the case where the destination accepts a known cell. Based on the above premise that all bridge devices have the same entry table, now consider a cell broadcasting a cell whose destination is unknown. The source bridge device has no known destination. Therefore, in the case where broadcast relay is performed for all bridge devices, it can be seen that the bridge device does not know the destination without searching or searching the entry table. Therefore no down filtering is required.

Next, the learning which is the process of storing the information of a terminal position is demonstrated. The bridge device related to this embodiment executes learning from two directions, namely from a frame accommodated by FDDI and from a cell accommodated from high-speed intermediate LAN 4.

Learning from the upward direction is divided by registration in the entry item table 1114 of the set of source MAC addresses (SAs) and source VCIs located at the front of the frame under the control of the path control unit 1113 when the division control unit performs division. It is executed by the control unit. By this configuration, the bridge device learns the position of the terminal under its control. The path of this learning is shown by path a in FIG.

Learning from below is performed from the cell sent to its own bridge device and from all cells sent to the other bridge device. This path is represented by the acceptance pathway (Figure 3b) and the common learning pathway (Figure 3c).

Of the series of cells divided from the frame by the transmission bridge device, only the first cell contains the SA. The bridge device therefore learns from this original cell as learning from the cell accommodated by this bridge device. This learning is executed by the reassembly control unit 1112 via registration in the entry item table 1114 of the set of SA and source VCI in the information unit of the first cell under the control of the path control unit 1113.

For the purpose of improving the learning efficiency, learning from the common learning path (path in FIG. 3C) can be learned from cells transmitted to its own bridge device as well as cells transmitted to other bridge devices.

The transmission path of the high-speed relay LAN 4 is composed of 150 Mbps N (N = 4 to 6) logical highways, and the loop access unit 10 collects all of these lines to contain the learning information (first cell). Is sent to all bridge devices (up to four ports can be hostile) loaded on their Norwood. Each of the bridge devices 11 to 14 receives the cell and registers this cell in the entry item table in the same manner as the learning from the cell received by its bridge device to execute the learning.

The details of the entry item table 1114 will be described below.

6 shows the structure of the entry item table 1114. As shown in FIG.

As shown in FIG. 6, a write item is registered by writing in a 48-bit MAC address and a 12-bit VCI to indicate "use" in the use / nonuse indicator.

The position for writing entries is generated by using a hash function with strong random mapping and using the MAC address as a key.

The write item is erased by the timeout of the aging timer. The erasing is performed by updating the display of "used" to the display of "unused".

A fixed entry is also provided that is registered or erased by the bridge device processor and erased by the aging timer.

The bridge device processor 1115 registers its station FDDI MAC address as a fixed entry in advance in the entry item table 1114, for example. In other words, although its own bridge device also has an FDDI MAC address, a fixed entry is used when it cannot normally learn from the source address of a frame transmitted from its station to the FDDI ring.

The entry position is determined by the hash function for the following reasons. The capacity of 28 ⁴⁸ is required in the entry table to fix the entry of the 48-bit MAC address, but such a large capacity is difficult to realize in practice.

Therefore, it is necessary to reduce the entry position to be determined to 48 bits of the MAC address, for example, to about 16 bits (64 kilo entry). To reduce the probability of different MAC addresses colliding with the same entry, a function that is evenly distributed evenly within a 16-bit region is valid.

If a hash function is used, if a new entry is registered by taking the entry usage rate ρ, then the probability that MAC addresses will collide with the registered entry is ρ. The probability of ^nth registration after (n-1) collisions is ρ ^n-1 × (1-ρ). For example, when ρ = 50%, the probability of registration up to the 10th is 99.9%.

In order to be able to perform fast search / registration, the hash function is realized by hardware.

7 shows the configuration of the hardware.

As shown in Figure 7, the hash function was taken to be easily made by a simple circuit of FX-OR, addition and rotation.

The candidate position of entry registration by hash generation is determined by executing the hash n times (e.g. 10 times) with the corresponding MAC address as key by the following discrimination method:

(1) If there is an unused entry item, it can be registered in this entry item.

(2) If the registered entry is found by the corresponding MAC address, registration in this entry is possible.

(3) If candidates (1) or (2) are not found after n hashing, new entries are registered first. Therefore, data is written to the entry of the oldest timer value.

On the other hand, the MAC address is retrieved using the same hash function using the corresponding MAC address as a key.

Next, a path control section for realizing the registration processing of entry items into the entry item table 1114 and the retrieval process of entry items from the entry item table 1114 will be described.

8 shows the configuration of the path control unit 1113 shown in Article 3. As shown in FIG.

Referring to FIG. 8, reference numeral 1131 denotes an interface circuit for executing an interface with the division controller 1111, the bridge processor 1115, the reassembly controller 1112, and the common learning path c, respectively. 11135 indicates an aging timer circuit, 11136 indicates a state management circuit which executes state management and access control of the entry item table according to the state, and 11137 generates hash stitching from a 48-bit MAC address to generate the entry item table ( 1114) is a hash subcircuit for obtaining the write item position, 11138 is a search circuit for implementing the filtering function, and 11139 is a registration circuit for performing the learning function.

In the path control unit 1113, the filtering processing including the aging timer value update processing, the division search processing, the division registration processing, the acceptance path registration processing and the common learning path registration processing, and the learning processing are integrated.

Therefore, the above processes are executed in the following priority order.

(1) In order to improve the performance of the relay process, the highest priority is on upward filtering.

② Among the broadcasts due to unknown destinations, the most useless is the communication between the terminals under the control of their own bridge device. Therefore, to avoid this, higher priority is given to learning from an accepted FDDI frame under the control of its bridge device than in other learning.

(3) Low priority is given to learning from the learning path and common learning context, and registration data is held in the FIFOs 111331 and 111341 for a while until some spare time occurs during processing. The filtering and learning frequency is once for one frame or once for an average of eight cells in number of cells. Therefore, a reserve time occurs even when priority occurs in the ① and ② treatments. Thus, this process can be executed in this preliminary time. The updating of the aging timer value supplied in correspondence with each entry is executed intermittently for each entry and thus does not disturb other processing for a long time. Therefore, since the time interval for updating the aging timer value is long and the time required for this processing is short, the highest priority is on this processing.

9 illustrates a state change of the path control unit 1113.

As shown in FIG. 9, the path controller 1113 has three functions as follows:

① Update aging timer value

② Search Processing

③ Registration processing

The state management circuit 11136 determines the priority based on the request from the interface circuits 11131 to 11134 or from the aging timer circuit 1135 together with each of the other controllers. The state management circuit 11136 then manages the state of the path control unit, controls the state, and accesses the entry item table 1114 to realize the above function.

In the entry list 1114, at the time of retrieval and registration, the access address is generated by the hash circuit by using the MAC address as a key, and memory read and memory write are executed in units of 8 bytes and 4 bytes, respectively.

The operation of the hash sub circuit 11137 will be described below.

As an example, the operation of the hash circuit 11137 when there is a request for search / registration from the division control unit 1111 will be described.

10 shows the timing of the search / registration process.

As shown in FIG. 10, the operation 10 (a) of the first hash function h1, the generation 10 (b) of the disaster function h2 to hn, and the memory access 10 (c) are shown in FIG. It is executed by pipeline processing.

That is, the memory access / simultaneous occurrence determination of hi and the generation of the next hash string hi + 1 are executed in parallel. When the occurrence of h2 begins, the occurrence of the next request h1 begins.

11 is a state diagram of the hash circuit. The explanation starts from the occurrence of h1.

When there is a search or registration request from any one of the interface circuits 11131 to 11134 in the request waiting state, the MAC address is read out from the corresponding interface circuit based on the result of the priority determination by the state management circuit 1136 and h1 is based on. Read from the corresponding interface circuit and h1 is generated by using the MAC address as the key.

The occurrence of the next request h1 indicated by the state management circuit 11136 waits until the occurrence of h2 in the current processing starts.

The occurrence of h2 to hn is described below.

When generation of h1 is completed, h2 is generated based on h1, and h3 or more is sequentially generated. The entries of hi-1 are then accessed in parallel during the occurrence of hi.

hi generation treatment is terminated under the following conditions.

In the case of a search, hi generation processing is terminated when the retrieved circuit 11138 finds the desired MAC address or when the maximum hash hn (10 times) is reached.

In the case of registration, the hi generation process ends when the candidate of the registration entry item is determined by the registration circuit 11139 according to an algorithm for determining the candidate. The maximum hash hn is searched to determine the candidate.

Upon completion of the retrieval by the retrieval circuit 11138 or the registration by the equal width circuit 11139, when the generation of h1 is completed, the subcircuit 1137 generates the next h2.

Next, retrieval processing and registration processing using the access address generated by the hash subcircuit 1137 will be described.

First, the search process will be described.

The searching process is executed by the searching circuit 11138. In the search process, there is a request from the division control unit 1111 and a request from the bridge processor 1115 for the division process.

12 is a state change diagram for the searching process in the searching circuit 11138. FIG.

When there is a search request from the state management circuit 11136 in the idle state, the source MAC address SA is read out from the corresponding interface circuits 11131 and 11132, and generation of h1 by the hash circuit 11137 is waited. do. When h1 occurs, more than h2 entry items (high priority 8 bytes) are read sequentially from the entry item table 1114 starting at h1. Since the entry contains a high-order 8-byte MAC address, it is determined whether this MAC address occurs simultaneously with the MAC address that becomes the key. When these MAC addresses occur at the same time, hash generation and memory reading are stopped and only the remaining low-order 8 bytes of the read item are read. The entry is notified to the corresponding device and the aging timer value within the high rank 4 bytes is reset.

If no entries are found after hashing up to n times, no entries have been made. In this case, the division process is broadcast due to an unknown destination.

The registration circuit will now be described.

The registration process is executed by the registration circuit 11139. As already explained, there are requests from the following directions in the registration process.

① Registration (upward learning) from division controller

Registration from the receiving path (learning from the cell received by the negative negative port)

③ Registration from common learning path (learning from all downward lines)

13 is a state change diagram of the registration processing in the registration circuit 1139.

When there is a registration request from the state management circuit 11136 in the idle state, the destination MAC address DA is read out from the corresponding interface circuit, and generation of h1 by the hash circuit 11137 is awaited. When h1 is generated, entries (h8 or higher) of h2 or more are read sequentially from h1. The high order eight bytes contain information used to determine the candidate, namely use / non-use indication, dynamic / fixed indication and aging timer value. The candidate is determined according to the algorithm described above for determining the candidate. When hashing is performed up to n times, memory read is stopped and 16-byte registration data is written to the candidate write entry position four times (including four bytes each) by dividing the data by four. Processing then terminates.

Next, a timer value update process for an aging timer used for erasing a registration entry item will be described.

In this embodiment, in order to provide flexibility in the decomposition of the aging timer value, it is possible for the bridge processor 1115 to operate the timer to set the timer value unit to the time ΔT (decomposition). Update processing of the aging timer value is executed intermittently for all the entries, so that other processing is not disturbed.

14 is the timing for the aging timer value.

The timer circuit updates the timer values of all of the M write items (eg, 128K write items) within the ΔT (decomposition) time. For example, if the decomposition of the timer value is at least 1/2, in order to update all the write items, the time interval Δt for updating between the write items is as follows.

△ t = 1/2 ÷ 128K = 7.8㎲

That is, if the write items are updated sequentially at time intervals of 7.8 ms or less, it is possible to update all the write items within the decomposition time of the timer value. If the update for all entries is completed within that time, the update waits until the next [Delta] T end.

15 is a state diagram for updating the aging timer value.

As shown in Fig. 15, the end of the other processing currently executed is sequentially waited for DELTA t, and the update is executed as follows.

High-order 8 bytes of the entry table are read out. In the case of " used " and " dynamic " states, the timer value in the corresponding entry is incremented and updated in the use / non-use indication and the dynamic / fixed indication (high-order 4-byte write).

When the timer value expires, the usage / nonuse indication in the corresponding entry is rewritten as unused (high-order 4-byte write) and the entry is cleared.

In this embodiment, the bridge processor 1115 can directly access the entry item table and execute the following processing.

① Memory writing / reading test

The bridge processor 1115 issues a real address, writes it directly to the write item table, reads it out, and performs a memory check of the write item table.

② Valid Entry Item Search

The bridge processor 1115 issues a real address and reads the entry of the entry table directly to determine whether it is valid or invalid. That is, the bridge processor 1115 determines whether the entry item is used or not used. The bridge processor 1115 sequentially raises the memory address to find a valid write item.

Then, if it is desired to copy the externally stored learned terminal position information or the information of another bridge device, the bridge processor reads the searched valid write item and copies it.

③ Update Entry

The bridge processor registers the entry using the MAC address as a key.

This is the same as the registration process described above.

According to the first embodiment, the following effects are obtained.

It is possible to perform frame filtering and learn path information in the bridge device connected to the FDDI for transmission to the frame device and the high-speed relay LAN for transmission to the process length cell device.

② It is possible to execute fast filtering and learning by using the hardware hash algorithm for searching and registering in the entry table.

③ The deletion of the entry items in the entry items table is executed intermittently and sequentially by an aging timer provided corresponding to each entry item, thereby preventing the entry items table from being filled up by learning without deteriorating the hit rate.

In addition, since the aging timer value is updated intermittently by advancing the entry position, the aging timer process does not affect the performance of the search / registration process.

A bridge device according to a second embodiment of the present invention will be described.

6 shows the configuration of a network system using the bridge device according to the present embodiment.

As shown in FIG. 16, the bridge device 91 related to this embodiment is connected to a plurality of FDDIs. For simplicity, only two FDDIs are connected in FIG.

In the path in the bridge device 91 according to the second embodiment, the position of the MAC address is shown as a port number connected to the FDDI.

For example, the MAC address location is shown as port A and port B. Since two FDDIs are connected in this embodiment, there are two ports.

It is possible to perform address filtering by searching for a port number from the entry item table 9114 using the destination address as a key to determine whether the transport port number is determined or discarded. Learning is performed by registering a set of source addresses and introduction port numbers in the entry item table 9114.

FIG. 17 shows the structure of the entry item table 9114. As shown in FIG.

The direction of the source MAC address is shown as an FDDI port number, the other is the same as in the first embodiment described above.

18 shows the configuration of the bridge device 91.

In FIG. 18, reference numeral 91 designates a bridge device connected to the FDDI, and 911 designates a relay control unit. 912A to 912D indicate FDDI control units (ports A to D) corresponding to FDDI A to D, respectively. 9113 indicates a path control unit that performs learning of the station position and relayed frame filtering, and 9114 indicates a entry table.

The filtering and learning process is executed as follows.

For example, when frames are received from the FDDI A, the bridge processor 9115 retrieves DA and SA of the accommodation frames stored in the transmission / reception buffer 912A5 and transmits them to the path controller 9113.

In filtering, the path control unit 9113 retrieves the entry item table 9114 from the DA under the control of the path control unit, and obtains the port number of the port where the target terminal exists.

Then, a relay or discard decision is made based on the result of the operation as follows.

① If the destination port number is the same as the introduction port number, the frame is discarded.

② If the destination port number is not the same as the introduction port number, the frame is relayed. That is, the accommodating frame is copied to the transmitting and receiving buffer of the corresponding port and transmitted.

If the target port number is not found, the frame is sent to all ports.

Learning is executed by registering a set of SA and introduced port numbers in the entry item table 1114 under the control of the path control unit 9113.

Since the operation of the path control unit 9313 is the same as that of the first embodiment, it is omitted here.

According to the second embodiment, there are advantages as follows.

① It is possible to execute fast filtering and learning by using the hardware hash algorithm for searching and registering in the entry table.

(2) The erasing of the entry items in the entry item table is executed intermittently and sequentially by the etching timer purchased for each entry item, thereby preventing the entry item table from being completely filled by learning without lowering the hit ratio.

In addition, since the aging timer value is updated intermittently by advancing the entry position, the aging timer process does not affect the performance of the search / registration process.

As described above, according to the present invention, it is possible to provide a bridge device that can prevent the entry item table from being completely filled by learning without lowering the hit ratio and can flexibly cope with the movement of the terminal position. In addition, an address filter device capable of improving the processing efficiency of the address filtering process can be provided.

As described above, according to the address filter apparatus according to the present invention, a timer is provided corresponding to each address information registration, and the timer updating apparatus advances each timer value sequentially and intermittently. When the timer value is greater than or equal to the predetermined value, address information registration corresponding to the timer is erased from the entry table, thereby preventing the entry term target from being completely filled by learning without lowering the hit rate.

Further, according to the address filter device according to the present invention, when a timer is provided in correspondence with each address information registration, and the timer update device is started by the start device every certain period [Delta] T, the timer update device is applied to the registered address information. Therefore, each timer value advances sequentially and intermittently until the end. When the timer value reaches a predetermined value or more, registration of address information corresponding to this timer is collected from the entry item table, thereby preventing the entry item table from being completely filled by learning without lowering the hit rate.

Further, according to the address filter apparatus according to the present invention, in the first step, a function of a source address taken out from the introduction information frame at the time of registering in the entry item table or a target address taken out from the introduction information frame at the time of retrieval from the entry item table (fi (a), i = 1 to n) are sequentially generated to the address of the entry item table. In the second step, it is determined whether or not address information should be registered in the address generated in the first step of the entry table at the time of registration. In the third step, it is determined whether or not the address information registered in the address generated in the first step of the entry item table at the time of retrieval is desired information. By the above processing, the efficiency of using the entry item table can be improved. In addition, the efficiency of the address filter process can be improved by operating the first stage and the pipeline with the second stage or the third stage.

Further, according to the address filter apparatus according to the present invention, the introduction address information is registered in the entry item table from the branch LAN, the introduction address information from the N transmission path of the relay network is registered in the entry item table, and from the entry item table When at least two processes in the search for the address information of the contention contention with each other, the priority determinant value determines the priority. In the meantime, the execution device executes the processing based on the processing result. By such a configuration, the address filter process can be executed smoothly, and as a result, the process is improved. If a storage device for temporarily storing the introduction address information from the relay network is provided, during the period in which no other processing is performed, the execution device registers the address information stored in the storage device in the write item table. By this process, the system efficiency of the actual address filter process can be ensured.

Further, according to the address filter device according to the present invention, the priority determining device registers the introduction address information from the branch LAN in the entry item table, and the N point of the relay network is the introduction address information from the path in the entry item table. Since priority is determined between registering and retrieving address information from the entry table, the process with improved efficiency is smoothly executed. The address generator is a function of the source address extracted from the introduction information frame at the time of registering in the entry item table or the source address taken out from the entry term target or the target address taken out from the introduction information frame at the time of retrieval from the entry item table (fi (a). ), i = 1 to n) are generated sequentially in the address of the entry item table. At the time of registration, the registration address candidate determination device generates sequentially from the entry item table by the address generator. The registration address is determined at the time of registration, and the desired address information is retrieved from the address generated by the address generating device of the retrieval apparatus at the time of retrieval, thereby improving the utilization efficiency of the entry table. Further, the address generation processing for generating the i-th address with the address generator, the search processing for retrieving the i-1th address with the retrieval device, or the determination processing for determining the i-1th address with the registered address candidate deciding device are executed in parallel. To improve the processing efficiency.

In addition, according to the relay device according to the present invention, the address filter device performs an address filtering process. Based on the result of the address filtering process, the data format converter converts the information frame to be relayed to another network into the data format of the network to which the frame is to be relayed.

Further, according to the bridge device according to the present invention, the address filter device performs an address filtering process. Then, in the relay apparatus, based on the result of the address filter processing by the address filter apparatus, the reassembly apparatus converts the information frame to be relayed from the relay network to the branch LAN into the data format of the branch LAN. Based on the result of the address filter processing, the splitter converts the information frame to be relayed from the branch LAN to the relay network in the data format of the relay network. In the meantime, the LAN controller takes an interface with the branch LAN and enables information frames to be sent to and from the branch LAN.

In this bridge device, information frames on branch LANs, information frames transmitted to its own bridge device on the relay network, and information sent to other bridge devices other than information frames relayed to the relay network by at least one of its own bridge devices on the relay network. If an address filter apparatus is provided which registers address information in a write item table by extracting address information from a frame, it is preferable to relay all of them to the branch LAN without an address filter process to the information frames received from the relay network.

) 및 기입 항목표(1114,91114)의 구성이 조밀하고 고속형인 경우의 예에 대해서 설명한다.Now, the path control unit (in the first and second embodiments)

) And an example in which the configuration of the entry item tables 1114 and 91114 is compact and high speed.

A third embodiment of the present invention will be described below.

access memory)에 대해 설명한다.First, a D-RAM (dynamic) used as a memory element of a memory circuit (corresponding to a path controller and a write item table) related to this embodiment

access memory).

19 shows a high speed page mode read modify write cycle of the D-RAM.

)와 동시적으로 실행된다.As shown in Figure 19, the read-write write is written to the same address from Din because WE is negative, CAS is asserted, data is read from Dout, and then WE is asserted in the same cycle. . In this embodiment, the D-RAM is used in the fast page mode read modification write mode, which is a combination of the read modification write mode and the fast page mode. In this case, of course, updating the column address is a negative

Is executed concurrently with

The fast page mode is a mode in which data of the same row is continuously read by simply changing the open dress, and is widely used in commercial D-RAM and the like with the diary correction writing mode.

Next, an outline of the operation of the memory circuit according to this embodiment will be described.

The hash method is used in the retrieval / registration process of the memory circuit according to the present embodiment.

The hash method is a method of calculating a position where a data value is stored by performing a predetermined change to the data value.

That is, according to the hash method, the element which stores data is determined according to the data value contained in the data or a certain value K (referred to as a key). Therefore, the data retrieval can be completed only by checking these elements, and the processing is very efficient.

According to the hash method, h (k) = h (k ') may be used. Where K is different from K 'but in this case, re-hash hi (k) (i = 2 ~ n) is generated to avoid collisions.

In the retrieval / registration process, the value generated from the hash function, i.e., h (k), is used as the address of the memory element. That is, registration is made at the storage location indicated by h (k), or data is compared with data stored at the storage location indicated by h (k).

20 shows a database structure in which the memory circuit according to the present embodiment is used.

In FIG. 20, reference numeral 113 denotes a memory circuit corresponding to the path control unit 1113, etc., 1131 is a processor, and 1132 is an address generator. 114 denotes a storage element corresponding to the write item table 1114, and the like, and 115 denotes a processing unit corresponding to the bridge processor 1115 and the like. In this embodiment, the memory circuit 113 is a single chip integrated circuit.

The signal f indicates the function of instructing the processing of the memory circuit 113 by the processing device 115, and r indicates the processing result by the memory circuit 113. di indicates input data from the processing unit 115 and z indicates data to be written to the memory element 114. do denotes data read from the memory element 114, and k denotes a key value of the hash function h (k). The details of the function are described later.

The operation of the memory circuit 113 will be described based on the timing difference art in FIG.

First, the key K is taken out from the input data di of the data processing unit 1131, and the row address and column address are generated from the hash function h (k) of the address generator 1132 and put into the memory element 114.

Based on the read data do and the input data di read out from the address, the data processing unit 1131 processes the data to generate the write data z, and writes the data z into the memory element 114. Data processing is determined from the relationship between input data di and read data do.

The column address is incremented and the operation repeats until the termination condition determined from the relationship between the input data di and the read data do is satisfied.

That is, in the present embodiment, it is possible to use the fast page mode read-write write cycle of the D-RAM in which hi + 1 () = hi () + 1 is set, and the series of operations by the above-described disaster are 1 It is realized in the cycle.

The above operation will be described below in accordance with the state change of FIG. The address generator 1137 generates a row address and a column address from the first hash function h1 (k) of the key k, and the processor 1131 reads data from the corresponding address.

For illustrative purposes, assume that key k is a value contained in input data di.

The data processing unit 1131 generates the write data z from the input data di and the read data do according to the conditions of the function f and the read data do, and writes the data z at the same address. The column address continues to be generated from the function hi (i = 2 to n) in the event of a disaster until the end condition corresponding to each function is satisfied and the above processing is repeated. As described above, hi + 1 () = hi () + 1 was taken in this embodiment.

When the processing ends, the processing result r returns to the CPU 115.

Assuming that the DRAM has 4M bits and the data length is 64 bits, the maximum number of row addresses and column addresses is calculated as 4M bits / 64 bits = 65K write items. Therefore, if a disaster occurs up to 8 (n) times, the column address may be 0-7 and the row address may be 0-8k-1.

The functions described above will be described below.

The memory circuit related to this embodiment has the following functions: 1) search processing function 2) registration processing function 3) aging timer update processing.

The signal f (Fig. 20) indicates one of the functions and the memory circuit 113 executes processing based on the indicated function.

Each of the processes will be described in detail with reference to FIGS. 23, 24, 25, and 26. FIG.

23 is a field configuration of each write item of the memory element 114. In FIG. 23, the field consists of the key k, the entry e and the timer t.

24 is a detailed view of the memory circuit.

In Fig. 24, reference numeral 1131 denotes a processing unit for controlling data processing, and 11311 is a comparison circuit for comparing each of fields k, e and t of the input data di with fields k, e and t of the weather data do, respectively. 11312,11313, and 11314 show predetermined data of k, e and t of di and k, e and t of do according to the instructions 11f1,11f2 and 11f3 of the comparison circuit to generate the write data z (k, e, t). A data processing circuit that executes processing.

1132 is an address generator that generates an address to the memory element 114 in accordance with an instruction from the data processor 1131.

11321 is a state monitoring circuit, which receives the start instruction from the data processing unit 1131, controls the memo element access state by monitoring the state in accordance with the state change described later, and operates until the end instruction is received from the data processing unit 1131. Continue. 11322 is a hash generation circuit that generates a hash from key k. 11323 and 11324 are counter circuits that update row and column addresses, respectively, in accordance with instructions from the state monitoring circuit.

The processing of the memory circuit 113 receives an instruction by the CPU 115 which outputs data di to the memory circuit 113 and generates a function f.

Then, the CPU 115 waits until the processing is completed in the memory circuit 113.

First, the data processing unit 1131 in the memory circuit 113 will be described in detail.

25 and 26 show processing contents by the data processing unit 1131.

The comparing circuit 11311 decodes the function f received from the CPU 115 and transmits the key k to the address generating circuit 1132 to perform the following operations.

1) In the retrieval processing, the comparison circuit 11311 repeats the diary correction processing until the key k of the input data di coincides with the key k of the read data do.

If the keys do not occur simultaneously in the above processing, it is indicated in the processing circuits 11312 to 1314 that the read data do not change.

On the other hand, if the key is generated simultaneously in the above processing, the comparison circuit 11311 indicates to the processing circuit 1314 that the timer value t of the read data do is cleared, and the processing circuits 11312 and 11313 pass the data without processing. Is displayed.

Then, the end of the process is displayed in the state monitoring circuit 11321 (Fig. 26A).

After the hashing is repeated at the maximum number of hashing n, the process ends even if the keys do not occur simultaneously.

After the processing ends, the comparison circuit 11311 returns the processing result r (discovered / not found) to the CPU 115. The CPU 115 receives the result r, in the case of discovery, reads the read data do (desired data) and ends the search processing in the memory circuit 113.

(2) For the retrieval processing, the comparison circuit 11311 repeats the discovery process of the registerable position until di (k) coincides with do (k) or until a space where di (k) can be registered is found. do. If no space is found, the processing circuits 11312 to 11314 indicate that the read data do is not processed and the processing is repeated.

On the other hand, if a space is found, it indicates that the input data di is output to the processing circuits 11312 to 11313 and reports that the timer value is cleared to the processing circuit 1314.

Then, the end of the process is displayed on the state monitoring circuit 11321 (Fig. 26B). The condition for the registerable area is when the key data is generated at the same time (di (k) = do (k)) or when the key data is empty (do (k) = "").

If the registerable area cannot be found even after the hashing is repeated at the maximum hashing (n times), the process ends.

After the processing ends, the comparison circuit 11311 returns the processing result r (registered / non-registered) to the CPU 115. In response to the result r, the CPU 115 terminates the registration in the memory circuit 113.

(3) The update processing of the aging timer is executed as follows.

The update processing of the aging timer refers to a process of erasing write items that have not been used within a predetermined time.

In this process, no hash function is used to generate an address, the value of the key is made as a row address, and the column address is simply increased to repeat the process.

For data processing, it is indicated in the processing circuit 1314 (Z (t) = do (t) + 1) that the timer value of the read data is increased, and in the processing circuits 11312 and 11313 that the data is not processed. (Figure 26c).

When the timer expires, the key data at the corresponding position is invalid (for example, written as 0), and the data is erased (Fig. 26D).

The process ends when the hashing reaches the maximum number (n times).

If the function of the aging timer is not used, the processing unit 115 cannot exhibit this function.

In the above processes 1 to 3, the write data Z (k), Z (e) and Z (t) (FIG. 26) generated in the processing circuits 11312 to 11314 are stored in the main memory under the control of the address generator 1132. Write to element 114.

Next, the address generator 1132 will be described in detail. The state monitoring circuit 11321 starts operation based on the start instruction from the comparison circuit 11311, generates a timing signal 11321 in the memory element 114, and continues operation until there is an end instruction.

The hash generation circuit 11322 generates a row address from the key k obtained from the comparator circuit 11311 and loads the initial row address into the counter circuit 11323.

The counter circuits 11323 and 11324 hold the row address 11323a and the column address 11324a, respectively, and increase in accordance with the timings 11321a and 11321b indicated by the state monitoring circuit 11321.

As described above, according to the present embodiment, a database using the disaster recovery method can be realized, and in particular, the following effects are obtained.

1) The memory search or registration process can be executed in one cycle.

② The registration data that is not necessary for a predetermined period can be erased.

When data is controlled on a single chip, it can reduce read modification timing and increase processing speed.

In the above embodiment, the data processor, the address generator and the memory can be configured on a single chip. However, the chip can be divided as shown in Figs. 27 (a) to 27 (d) according to other conditions such as the memory capacity of the memory circuit.

More specifically, Fig. 27 (a) shows the case where the data processing unit 1131 and the address generator 1132 are integrated and only the DRAM 114 is separated. This configuration makes it possible to realize a database function by using a general DRAM.

27 (b) shows a case in which the data processing unit 1131, the address generator 1132, and the DRAM 114 are separated, and may have flexibility in the modification method and the hash method depending on the usage method.

FIG. 27 (c) shows a case where the data processing unit 1131 and the DRAM 114 are integrated and the address generating unit 1132 is separated, so that the hash method can be flexible and a memory for storing a continuous data processing function can be realized. Can be.

FIG. 27 (d) shows the case where the address generator 1132 and the DRAM 114 are integrated and the data processor 1131 is separated, which has flexibility in the modification method and continuously generates an address according to the hash method. The memory for storing functions can be realized.

Now, as a fourth embodiment of the present invention, a bridge device using the memory circuit described in the third embodiment as an address database will be described.

The configuration of the network system interconnected by the bridge device according to the fourth embodiment is as shown in FIG.

In FIG. 16, the bridge device according to the present invention is connected to a plurality of FDDIs.

The bridge device is composed of an address table for storing a position where a terminal exists.

In the case of relay data, the bridge device refers to an address table for relay or discard decision and the destination address of the introduction packet. In other words, the bridge device executes the address filtering device.

More specifically, if the destination terminal of the packet is in the direction of another LAN or the destination is unknown, the packet is relayed and the packet is discarded if the destination terminal is in the introduction direction.

In addition, the bridge device refers to an introduction packet and performs learning by registering a source address and a terminal position in an address table.

The address table is reviewed at predetermined intervals for the following purposes.

① Prevents the address table from filling up completely by learning

(2) It flexibly copes with the movement of the terminal position, and the registration of the terminal for which no packet is transmitted is deleted.

FIG. 16 shows a case where a bridge device is connected to two FDDIs for simplicity of explanation.

In the bridge device according to the present embodiment, the path is executed by expressing the position where the intermediate access control (MAC) address (48 bits) exists by the port number of the bridge device connected to the FDDI.

For example, the MAC address location is represented by ports A and B.

In this embodiment, two FDDIs are assumed to be connected. Therefore there are two ports.

The structure of this address table is the same as that in FIG. 17 and FIG.

The address table has a MAC address, and the FDDI port number shows the direction of the MAC address and aging timer.

28 shows the configuration of the bridge device according to the fourth embodiment of the present invention. This corresponds to the configuration of the bridge device of FIG.

In FIG. 28, reference numeral 91 denotes a bridge device connected to the FDDI, reference numeral 911 denotes a relay control unit, and reference numerals 912A to 912D denote FDDI controllers (ports A to D) corresponding to the FDDIs A to D, respectively.

9116 is an address database for performing the learning of the station position and determining the relaying / closing of the relayed frame, and uses the storage circuit 113 according to the address database third embodiment.

9115 is a processor, the operation of which is described below.

First, filtering is performed as follows.

When a frame is received from the FDDI A, for example, the processor 9115 extracts the destination address DA of the accommodation frame stored in the transmission / reception buffer 912A5, transfers the DA to the address database 9316, and executes the third implementation. Generate the search function described in the example. The processor 9115 can know the port number of the port where the target terminal exists from the data obtained from the address database 9316 (do in the previous embodiment).

In the address database 9316, the MAC address corresponds to the key field of FIG. 23, the port number corresponds to the write item field, and the aging timer corresponds to the timer field of FIG.

As a result of the above processing, relaying or discarding is determined as follows.

① If the target port number is the same as the introduction port number, the frame is discarded.

② If the target port number is different from the introduced port number, the frame is relayed to the corresponding port. The received frame is copied to the transmit and receive buffers of the corresponding port and then transmitted.

③ If the target port number is not found, the frame is relayed to all ports.

The learning is executed by sending the set of source address SA and introduced port number to the address database 9316 to generate the registration function described in the third embodiment.

The aging timer value corresponding to the memory of the row address is updated by transferring the row address to the address database 9316 to generate the aging timer function described in the third embodiment. By repeating the process of increasing the row address intermittently, the aging timer values corresponding to all the memory addresses can be updated.

For example, when the aging timer is not required in the bridge device or when the registration value is not required in the system, the processing and timer fields may be omitted.

As described above, according to this embodiment, the processing efficiency of the address filter process can be improved and the physical quantity of hardware can be reduced.

In each of the embodiments described above, the case where the memory circuit is used as the database has been described. However, needless to say, that the memory circuit related to the present invention can be generally applied to the other image processing described above.

In the above embodiments, address generation is executed by a hash method. However, depending on the processing using the memory circuit, address generation may be performed by a method suitable for the processing. In addition, the configuration of the data field and the functions to be realized may be appropriately determined depending on the processing using the memory circuit.

According to each of the above-described embodiments, the processing speed can be increased by performing data processing of the database in one cycle by accessing the memory element only once. In addition, the processing speed can be increased by realizing the memory circuit in a single chip.

As described above, according to the present invention, it is possible to provide a memory circuit capable of performing high-speed processing of data retrieval / registration and the like.

That is, according to the memory circuit according to the present invention, the data is read from the memory in the address generated by the address generator for data input from the outside. Based on these data, the comparison section determines the data generation mode for the data to be written to the memory instead of the data read from the memory. Based on the determination result, the data processing unit generates data to be written and writes this data into the memory.

Until one of the predetermined conditions for the relationship between the input data and the read data is satisfied, the data is sequentially read from the memory according to a predetermined rule with respect to the input data, and the data generation and writing are repeated.

As described above, according to the storage circuit according to the present invention, the retrieval processing and registration processing can be realized at high speed by hardware such as a database device. Further, by applying the data input to the image data stored in the memory under predetermined conditions in image processing or the like, high-speed processing can be performed to obtain new data.

In addition, by configuring the memory as a DRAM having a read-write write mode, it is also possible to increase the processing speed by configuring the data read to the address read from the memory and the write of data generated by the data processor to be executed in one cycle of read-write write cycle. Can be.

Furthermore, by configuring the above-mentioned DRAM to have a high speed page mode, the address generator also generates a row address and a column address of the DRAM for the first address into which the data will be read for comparison with data input from the outside and the data Is configured to generate only a column address for the second address and subsequent addresses that are generated sequentially, and also to allow the reading of data from the memory and the writing of the data to the read address generated by the data processor to be executed in the high speed page mode. By constructing, high speed processing can be realized faster.

In the case where the memory circuit is used as a database, the retrieval and registration process can be efficiently executed by using a hash method for data having an input portion of address generation.

In addition, according to the data retrieval and registration method according to the present invention, the data retrieval and registration can be executed by a hash method, and since the hash function is hn = h1 + n (n is the number of hashes), the DRAM memory is used as a fast page mode read-modified surge mode. Memory data can be retrieved and registered at.

In addition, according to the memory circuit IC according to the present invention, the memory circuit is integrated and has advantages such as high speed, high load density, and easy use.

Therefore, according to the bridge apparatus according to the present invention, since this memory circuit IC is used as the address database, it is possible to execute high speed address filter processing and to make the memory circuit IC have a compact structure.

Claims (24)

An address filter apparatus for performing address filter processing between a plurality of networks using address information extracted from an introduction information frame registered in a writing item table, comprising: timers provided in correspondence with each address information registration and each timer value sequentially And intermittent raising timer updating means, and means for canceling registration of address information corresponding to the timers from a entry table. An address filter device for performing address filter processing between a plurality of networks using address information extracted from an introduction information frame registered in a write item table, the address filter device comprising: timers provided in correspondence with each address information registration; Timer updating means for raising each timer value sequentially and intermittently, starting means for starting said updating means in a predetermined cycle [Delta] T, and registration of address information corresponding to the timers when the timer value is a predetermined value or more. An address filter device comprising means for erasing from the entry table. 3. The address filter device according to claim 2, wherein said timer updating means raises each timer value intermittently at a time interval [Delta] t (maximum number of registrations in [Delta] t < = DELTA T ÷ entry item table). An address filtering method for performing address filter processing between a plurality of networks by using address information extracted from an introduction information frame registered in a entry item table, wherein the source address or entry entry table taken out from the introduction information frame at the time of registration into the entry item table A first step of sequentially generating a function (fi (a), i = 1 to n) of the destination address a taken out from the introduction information frame upon retrieval from the entry information frame, and at the first step at registration A second step of determining whether or not information should be registered in the address of the generated entry table; and a step of determining whether address information registered in the address of the entry table generated in the first step at the time of retrieval is desired information at the time of retrieval; Three steps to filter the dress. 5. The method of claim 4, wherein the first and second or third stages are operated as pipelines. 5. If the address information registered in the address fi (a) of the entry item table in the third step at the time of retrieval is determined to be desired information, the search is terminated, and the address fi (a) of the entry item table is set. And if it is determined that the registered address information is not the desired information, the address fi + 1 (a) of the entry item table generated in the first step is continued. An address filter device that performs address filter processing between branch LANs and a relay network composed of N (N≥1) logical transmission paths or physical transmission paths by retrieving address information extracted from the introduction information frame registered in the entry item table. In order to prioritize the registration of the address information coming from the branch LANs into the entry item table, the registration of the address information from the N transmission path of the relay network into the entry item table, and the retrieval of the address information from the entry item table. An address filter device comprising a ranking means and execution means for executing a process in accordance with a result of the determination. 8. The method according to claim 7, wherein the priority is in order of retrieving address information from a write-in target, registration of address information entering the entry table from the branch LANs, and registration of address information entering the entry table from the relay network. An address filter apparatus characterized by the above-mentioned. 8. The apparatus according to claim 7, wherein the filter device includes storage means for temporarily storing address information coming from the relay network, and the execution means includes address information stored in the storage means for a period when no other processing is being executed. And the execution means registers the address information stored in the storage means in the entry item table during the period when no other processing is being executed. An address filter device that performs address filter processing between branch line LANs and a trunk line network composed of N (N≥1) logical transmission paths or physical transmission paths by retrieving address information extracted from the introduction information frame registered in the entry item table. Determining priority of registering address information from the branch LANs into the entry table, registering the address information from the N transmission path of the relay network into the entry table, and searching the address information from the entry table. A function of the priority determining means and the destination address (a) taken out from the introduction information frame at the time of registration in the entry item table or in the entry information frame at the time of retrieval from the entry item table (fi (a), i = Address generating means for sequentially generating 1 to n) to the address of the write item table; Registration address candidate determining means for determining a registration address from among addresses sequentially generated by the address generating device in the write item table, and searching for desired address information among addresses generated in the write item table by the address generating means at the time of retrieval; An address generating process for generating an i-th address by said address generating means, a search process for searching for an i-1 th address by said searching means, or an i-1 th by said registered address candidate determining means; An address filter device comprising means for processing the decision processing for determining an address in parallel. An address filter device according to claim 1, and data conversion means for converting a data format of an information frame to be relayed to another network as a result of address filter processing by the address filter device to a data format of a network to which the information frame is to be relayed. A relay device for connecting a plurality of networks. An address filter device according to claim 1 for connecting branch LANs with a relay network consisting of N (N≥1) logical transmission paths or physical paths, and a relay network as a result of address filter processing by said address filter device. Reassembly means for converting the data format of the information frame to be relayed from to the branch LANs to the data format of the branch LANs to which the information frame is to be relayed, and the information frame to be relayed from the branch LANs to the relay network as a result of address filter processing. A bridge device comprising a relay device including division means for converting a data format into a data format of a relay network to which an information frame is to be relayed, and a branch LAN control unit for controlling an interface with a branch LAN. 13. The apparatus of claim 12, wherein the address filter device comprises an information frame on branch LANs, an information frame transmitted to its own bridge device of the relay network, and an information frame relayed to the relay network by at least its own bridge device of the relay network. Extracts address information from an information frame transmitted to another bridge device, registers the address information in the entry table, and branches all the information frames received from the relay network without performing the address filter process. Bridge device, characterized in that relaying to. A comparator for determining a data generation mode based on a memory, externally input data and data read out from the memory, and writing to an address into which data is read from the memory in accordance with the data mode determined by the comparator. A memory circuit comprising a data processor for generating quality data and an address generator for sequentially generating addresses in accordance with a predetermined rule until a condition determined from the relationship between input data and read data from the memory becomes one of predetermined conditions. 15. The data processing apparatus according to claim 14, wherein each of said data read out from said memory consists of a plurality of fields, and said data processing section includes a plurality of processing circuits for independently generating generation of the data to be written for each field. Memory circuit to do. 15. The memory circuit according to claim 14, wherein one of said predetermined conditions is a number of times said comparator reads data to be compared with said input one data from a memory. 15. The method of claim 14, wherein the comparison unit determines a data generation mode based on data input from the outside and data read from the memory, as well as function signals to be input from the outside in order to allocate a function of the comparison circuit. Memory circuit. 15. The memory according to claim 14, wherein the memory is a DRAM having a diary correction write mode, and writing of data from the memory and writing of data generated at a read address by the data processing unit are executed in a read modification write cycle in one cycle. And a memory circuit. 19. The DRAM of claim 18, wherein the memory is a DRAM having a high-speed page mode, and the address generator is configured to read a row address and a column address of the DRAM for an address from which the data input from the outside and the data to be compared first are read. And a column address is generated only for the second and subsequent sequentially generated addresses, and reading of data from the memory and writing of data generated by the data processing unit to the read address are executed in the fast page mode. And a memory circuit. 15. The memory circuit according to claim 14, wherein the address generator generates an address by a hash method using the input data or a part of the data as a key. 20. The row address of a DRAM according to claim 19, wherein the address generator is configured to key input data or a part of the data as a key for an address at which data to be first compared with data input from the outside is read. And a column address for generating a column address, and sequentially generating the first and second column addresses for the sequentially generated addresses, and reading the data from the memory and writing the data. A gigabit memory circuit characterized in that a gigabit page mode read-modify write mode is executed. A method of retrieving and registering data characterized in that the high speed page mode read and write write mode is executed by taking the search and registration of memory data in the DRAM such that the hash function hn = h1 + N (where N is the number of times of disaster). A memory circuit IC incorporating the memory circuit according to claim 14. A bridge device comprising an address database by the memory circuit IC according to claim 23, and connecting a plurality of circuits to perform address filter processing using the address database.

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