DE4103888A1 - Address filter for interface between communication networks - has clock sources responding to entry of extracted address information in table to control subsequent erasure - Google Patents

Abstract

The address filter, allows address information to be extracted from an incoming information to be extracted from an incoming information frame, for entry in an input table. The address filter has clock sources responding to each address information input, with a clock source renewal device for sequential and intermittent indexing of each clock value and a device for erasing the address information from the input table corresponding to the clock sources, upon a preset clock source value being reached. ADVANTAGE - Prevents input table from being overloaded.

Description

The present invention relates to an address filtering method and unit which used in a bridge unit or the like for connecting networks will.

Switch processing of packets is usually done as follows executed:

A bridge unit has an input table for storing a position, in which a connection is arranged. When performing a mediation operation the bridge unit refers to this input table and a destination address an incoming packet to decide whether to send the packet or should be removed, d. that is, the bridge unit performs address filter processing by.

To be more precise, the packet is transmitted when the destination or The packet's destination port is in the direction of a different LAN or if the destination of the package is not known and if the package is in the arriving direction, it will be removed.

They are methods of dynamic learning of the contents of an input table been proposed. For example, a technique is known which is disclosed in JP-A-64-39 852 is described.

According to this technique, an incoming packet is referred to and its source address and its connection position are in the input table registered to perform learning.  

The entry table is checked periodically with the aim of:

• 1. Prevent the table from being completely filled by learning; and
• 2. Flexible handling with one movement of the connection position, and one Registration of a connection that does not send or receive packets is deleted from the input table.

However, according to the prior art described above, the periods are separated and a registration period of each connection is marked by an in Bring agreement from her with the contents of the registration, so that only those connections that are within the current period and within of the previous period have been registered, and those connections that were registered before the previous period, will be deleted. A registration of connections that do not send or Received packets will be deleted. Therefore Contents of a learning that occurred during the period before the previous period executed, deleted. As a result, at the beginning of each period The number of entries in the input table is insufficient, making it a problem indicates that the hit rate is reduced.

It is an object of the present invention, an address filtering method and an - create unit that can keep a table from learning to be filled without reducing a hit rate, and flexible with can handle several connection positions.

It is another object of the present invention to provide an address filtering method and to create a unit that has processing efficiency of address filter processing can improve.

To achieve the above objects, the present invention provides one Address filter unit for performing address filter processing among a plurality of networks by using address information that comes from an incoming Extracted information frame, which is registered in an input table is. The address filter unit consists of a timer which is provided to to correspond to each address information registration, a timer renewal unit to sequentially and intermittently advance each timer value, and a unit for deleting registration of address information corresponds to the timer from the input table if a timer value equals or becomes larger than a predetermined value.  

To achieve the above objects, the present invention further provides one Address filter unit for performing address filter processing among a plurality of networks by using address information derived from a incoming information frame is extracted, which is in an input table is registered. The address filter unit consists of a timer that is provided is a timer renewal unit to correspond to each address information registration to sequentially and intermittently advance each timer value, a starting unit for starting the timer renewal unit in one constant cycle ΔT and a unit for deleting a registration of the Address information corresponding to the timer from the input table, if one Timer value becomes equal to or larger than a predetermined value.

The present invention also provides an address filtering method for Perform address filter processing on a variety of networks Receive address information resulting from an incoming information frame is extracted, which is registered in an input table. The Address filtering consists of a first step for sequential generation as an address of the input table of a function (fi (a), i = 1 to n) one Destination address (a), which comes from an incoming information frame at the time of the Receiving a source address is extracted, or the input table that is extracted an incoming information frame at the time of registering the Input table is extracted, a second step to make a decision about whether address information generated in the first step is or must not be registered in the address of the input table, and a third step in making a decision as to whether the in the first step generated address information in the address of the input table is registered, is a desired address information or not, the first Step, the second step and the third step are processed sequentially or pipeline will.

Furthermore, the present invention provides an address filter unit for execution address filter processing under a branch line LAN and one Trunk network, the N (N1) logical Have transmission paths or physical transmission paths through Receive address information resulting from an incoming information frame is extracted, which is registered in an input table, namely at Purposes of improving processing efficiency of address filter processing. The address filter unit consists of a priority order decision unit for Decide on a priority order to perform registration of a Address information arriving from a branch line LAN into the  Input table, a registration of address information by N transmission paths of a wide area network arrives in the input table, and a Receiving address information from the input table and from one Execution unit for executing the processing based on the result of a Decision based.

To achieve the objects described above, the present invention provides an address filter unit for executing address filter processing under a branch line LAN and a trunk network, the N (N 1) have logical transmission paths or physical transmission paths, by receiving address information resulting from an incoming information frame is extracted, which is registered in an input table, for the purpose improving the processing efficiency of address filter processing. The Address filter unit consists of a priority order decision unit for Decide on a priority order to perform registration of a Address information coming from a branch line LAN into the entry table arrives, a registration of address information, which consists of N transmission paths a long-distance network arrives in the input table and a reception the address information from the input table, from an address generation unit for sequential generation as an address of the input table of a function (fi (a), i = 1 to n) a source address, which consists of an incoming information frame is extracted at the time of registration in the entry table, or a destination address (a), which comes from an incoming information frame to the Time of reception is extracted from the input table from a Registration address decision unit for deciding on a Registration address among addresses sequentially by the address generation unit are generated in the entry table at the time of registration, from a Receiving unit for receiving desired address information from the Address generated by the address generation unit in the input table, and from a unit for operating processing to generate in parallel an i-th address by the address generation unit, processing to Receiving an (i-1) th address by a receiving unit or one Processing for deciding on the (i-1) th addresses by the registration address deciding unit.

To achieve the objects described above, the present invention provides further a memory circuit consisting of a memory, a Comparison section for deciding a data generation mode based on data that is entered from outside and data that is from memory be read out, a data processing section for generating data,  which are to be written into the address, into the data from the memory in In accordance with the data generation mode read by a comparison section is selected, and an address generation section for sequentially generating an address in accordance with a predetermined one Rule until a condition resulting from a relationship between entered data and determined data is to be determined, one of predetermined conditions of not less than 1, and for reading data from memory.

Further advantages, features and possible uses of the present Invention emerge from the following description of exemplary embodiments in connection with the drawing.

Fig. 1 is a system construction diagram showing the construction of a network system to which the present invention is applied;

Fig. 2 is an explanatory diagram showing the outline of a frame connection;

Fig. 3 is a block diagram showing the construction of a bridge unit;

Fig. 4 is an explanatory diagram showing the representation of segmenting and reassembling processing;

Fig. 5 is an explanatory diagram showing the structure of a cell;

Fig. 6 is an explanatory diagram showing the structure of an input table;

Fig. 7 is a circuit diagram of a control circuit;

Fig. 8 is a block diagram showing the construction of a guidance control section related to a first embodiment of the present invention;

Fig. 9 is a state change diagram showing the operation of the guidance control section;

Fig. 10 is a timing chart showing the sequential operation of the control circuit;

Fig. 11 is a state change diagram showing the operation of the control circuit;

Fig. 12 is a state change diagram showing the operation of reception processing;

Fig. 13 is a state change diagram showing the operation of registration processing;

Fig. 14 is a timing chart showing the control of renewing an aging timer;

Fig. 15 is a state change diagram showing the operation of an old timer value renewal process;

Fig. 16 is a system construction diagram showing the construction of a network system related to a second embodiment of the present invention;

Fig. 17 is an explanatory diagram showing the structure of an input table;

Fig. 18 is a block diagram showing the construction of a bridge unit;

Fig. 19 is a timing chart showing the operation of a D-RAM used in a memory circuit;

Fig. 20 is a block diagram showing the structure of a database using the memory circuit;

Fig. 21 is a timing chart showing the operation of the memory circuit;

Fig. 22 is a state change diagram showing the operation of the memory circuit;

Fig. 23 is an explanatory diagram showing a field structure of memory data;

Fig. 24 is a block diagram showing the construction of a memory circuit related to a third embodiment of the present invention;

Fig. 25 is an explanatory diagram showing the principle of operation of the memory circuit;

Fig. 26 is an explanatory diagram showing an example of change processing of the memory data;

Fig. 27 is a diagram showing a chip division of the memory circuit; and

Fig. 28 is a block diagram showing the construction of a bridge unit.

Below is a bridge unit in one embodiment of the present Invention described.

The network system that uses the bridge unit that relates to the present Embodiment related will be described first.

Fig. 1 shows the structure of the network system.

In Fig. 1, nodes 1 to 3 are connected to a high speed local area network (LAN) 4 (600 Mbps to 2.4 Gbps, 150 Mbps x 4 to 16 multiplex), and fiber splitting data interfaces (FDDI) 5 to 8 fit e.g. . B. 802 family LAN. Node 1 matches up to four gates using bridge units 11 through 14 as gates.

Regarding the bridge units z. B. a bridge unit 11, the FDDI 5 and the high-speed connection LAN 4 .

The FDDI 5 connects 802 family LANs 51 and 52 . In other words, the network system related to the present embodiment has three hierarchies of LANs. In this case, the entirety of the 802 family LANs 51 and 52 and FDDI 5 is considered as a branch LAN for the bridge unit 11 . If the 802 family LANs are connected directly to the bridge unit 11 , these connected LANs are considered to be branch LANs.

The bridge units 11 to 14 decide whether frames that are received by the FDDIs should be removed or switched, by finding switching routes. For the frames to be switched, the bridge units 11 to 14 convert those frames into a data format of a high-speed connection LAN 4 (segmentation processing) and transmit the result. The bridge units 11 to 14 convert data received from the high-speed link LAN 4 into an original data format by the FDDI (reassembly processing) frames and transmit the result (hereinafter referred to as routing processing).

The illustration of the routing processing will be explained below based on the bridge unit 11 for connecting the high speed link LAN 4 and the FDDI 5 as an example.

The high speed trunk LAN uses a cellular system fixed length using a broadband ISDN transmission mode, that corresponds to multimedia transmission, and uses a statistical one Multiplex that uses cells of a required number, that of quantity corresponds to information, thereby creating a hyper-complex multiplex Realize information from slow access to fast Access is enough.

Fig. 2 shows a flow of a frame from the 5 to the FDDI FDDI 8 via the trunk LAN high speed 4.

The bridge units 11 and 21 store positions of the FDDI nodes existing in input tables 1114 and 2114 (learning) and execute the routing processing with reference to the stored positions.

The input tables 1114 and 2114 express directions in which the FDDI nodes exist by using bridging unit numbers of the trunk LAN 4 . In the present exemplary embodiment, bridge unit numbers A and B are assigned to the bridge units 11 and 21 , respectively.

Due to the above arrangement, the input of the input table has 11 sets of an FDDI address with a control with medium access time (MAC) and a bridge unit number.

The bridge unit 11 converts a frame received from the FDDI 5 into cells of a transmission data format of the trunk LAN of a high speed switch 4 (segmentation processing).

More specifically, the bridge unit 11 divides a received frame into a fixed length cell unit, adds a head having a source bridge unit number, a target bridge unit number, etc. to the cell unit, and transmits the result to the high speed LAN 4 . A target bridge unit 21 (B) is a bridge unit with a target FDDI node 81 (b) under its control, and is obtained by referring to the entry table 2114 which uses the target FDDI MAC address as a key.

On the other hand, the receiving bridge unit 21 receives cells transmitted to this bridge unit, reassembles the cells in a frame (reassembly processing), and conveys the result to the FDDI 8 under its control.

The above guidance information (the FDDI MAC address and the number of bridge units) is learned as follows:
The transmitting bridge unit 11 registers a set of the source address (a) and its own bridge unit number (A) of the frame received by the FDDI 5 in the input table 1114 .
The receiving bridge unit 21 registers in the input table 2114 the set of the source address (a) and the transmitting bridge unit number (A) based on the cells received by the high speed LAN 4 .
In the present embodiment, the inputs in the input tables 1114 and 2114 are cleared by the old timer value based on the IEEE 802.1 regulation (range: 10 to 10⁶ seconds).

Details of the bridge unit and details of the lead processing are as explained next.

Fig. 3 shows the structure of the bridge unit 11.

In Fig. 3 there is shown: a loop access region 10 of a high speed LAN, the part of the node, a bridge unit 11, a switching control section 111 and an FDDI control portion 112. A segmentation control area 1111 that disassembles the frame received by the FDDI control area 112 from the FDDI ring into cells and transfers the cells to the high speed LAN 4 , and a reassembly control area 1112 that assembles the cells from the loop access area 10 has been received in a frame, transmits the frame to the FDDI control area 112 . A routing control area 1113 learns the position of the station and filters the trunk frame. An input table is designated 1114 .

To perform switching in the bridge unit, data format conversion is performed between the FDDI and the high speed LAN 4 , as shown in FIG. 2.

First, segmentation processing to disassemble the FDDI Bordering in cells and reassembly processing for reassembly of the cells described in the original frame.

The segmentation control area 1111 takes apart the received FDDI frame, which is in cells in a receive buffer 1121 of the FDDI control area 112 ( FIG. 4 (1)), and delivers the cells to the loop access area 10 .

In segmentation processing, a cell header including a target virtual channel identifier (VCI) and a source VCI (proprietary VCI) is added to a cell unit to build cells as shown in FIG. 5. The VCI stands for the bridge unit number described above and this has the node address and the gate (bridge unit) address. The target VCI to match the target port is obtained from the input table 1114 .

In the meantime, the reassembly control section 1112 in reassembly processing reassembles the cell units disassembled by the transmitting or transmitting bridge unit into the original frame in the received bridge unit ( Fig. (2)). The reassembled frame is transferred to a transmission buffer 1125 of the FDDI control section 112 .

Now the connection / removal decision and routing processing described for transferring cells to the bridge unit that the Adjusts decision connection.

The segmentation control section 1111 receives the frame at the FDDI to be connected, holds the input table 1114 under the control of the routing control section 1113 using the destination MAC address (DA) as a key, and obtains the VCI (destination VCI) adapts the input table 1114 .

Based on the result of the above processing, there is an arbitration or remove decided as follows:

• 1. If the target VCI is the same as your own VCI, the DA is below the Control of your own bridge unit. Therefore, the framework does not become that LAN transferred at high speed, but it is removed.
• 2. If the target VCI is not the same as your own VCI, the DA is below the Check the other bridge unit. Hence the framework becomes the Bridge to the LAN switched at high speed.
• 3. If the VCI is not found, the framework is common to all of them Bridge units switched to the LAN at high speed, so that the mediated framework to all the FDDIs. Accordingly, this is Frame conveyed by all the other bridge units to the FDDIs, with to which these bridge units are connected. As a result, the Reach the destination node achieved.

The bridging unit that relates to the present embodiment does not perform filtering in the downward direction. The bridge unit, has received the cells, which are widely distributed by the transmitting bridge unit mediated or transmitted by determining the target VCI, reassembles and mediates all the cells that have been received the result of the FDDI connected to the bridge unit.

As the bridge unit that transmits the cells, the position of the destination node assessed and the cells transferred to the bridge unit which is determined to receive the cells in that direction, it is obvious that a Destination node under the control of the receiving bridge unit exists. Since only one FDDI is connected to the bridge unit, it will go beyond that also evident that the destination node exists in this FDDI.

The bridge unit of the embodiment learns from all of the cells including those intended for a different bridge unit. This means, that any bridge unit connected to the central office LAN should have the same input table.

The reason why no downward filtering is required has been already explained above for the case of receiving cells, their provisions  are known. Now, based on the above assumption, that any bridge unit has the same input table, the case Distribution cells considered, the provisions of which are not known. The The source bridge unit does not know the determination. In the case where one widespread mediation is effected for all the bridge units, it can therefore, without retrieving or checking the input tables, it is known that none Bridge unit knows the destination. So there is no filtering down required.

Next, the learning will be described, which is the processing for storing information of the terminal position. The bridge unit relating to the present embodiment performs two-way learning, that is, from the frame received by the FDDI and from the cells received from the high-speed trunk LAN 4 .

Learning from the upward direction is performed by the segmentation control section by registering the set of source MAC address (SA) positioned in the front section of the frame and its own VCI in the input table 1114 under the control of the guide control section 1113 if the segmentation control section performs the segmentation. With this arrangement, the bridge unit learns the position of the connector under its control. The route of this learning is shown by path a in FIG. 3.

The learning from the downward direction is carried out by the cells that are transmitted to the own bridge unit and by all the cells that are transmitted to the other bridge unit. This route is shown by the receiving path ( Fig. 3b) and the common learning path ( Fig. 3c).

Among a series of cells segmented from the frame by the transmitting bridge unit, only the first cell contains the SA. Therefore, the bridge unit learns from this first cell the learning from the cells received by this bridge unit. This learning is carried out by the reassembly control section 1112 by registering the set of the SA within the information section of the first cell and the source VCI of the cell header section into the input table 1114 under the control of the guide control section 1113 .

For the purpose of improving learning efficiency, learning from the common learning path (the path in Fig. 3c) enables learning from the cells that are transmitted to the other bridge unit and also the cells that are transmitted to the own bridge unit .

The transmission path of the high-speed link LAN 4 has N (N = 4 to 16) logical multiplex lines of 150 Mbps, and the loop access section 10 collects all of these multiplex lines and transmits the cell (the first cell) including learning information to all the bridge units, which are loaded to the own node (a maximum of 4 gates can be loaded). Each of the bridge units 11 to 14 receives the cell and registers the cell in the entry table in the same manner as the learning from the cells received by the own bridge unit to thereby carry out learning.

Details of the input table 1114 will be explained next.

Fig. 6 shows the structure of the input table 1114th

As shown in Figure 6, the input is registered by writing 48 bits of the MAC address and 12 bits of the VCI and displaying the "Apply" in the "Apply" / "Not Apply" display.

The position of writing the input is determined by using the control function with a strong random mapping and by using the MAC Address generated as a key.

The input is deleted by a time lock of the timer with the old value. The deletion becomes the display by renewing the "Apply" display "Do not apply" executed.

A static input is also provided which is registered or cleared by the bridge unit processor 1115 and which is cleared by the old value timer.

The bridge unit processor 1115 registers e.g. B. the own station FDDI MAC address as a static input in advance in the input table 1114 . In other words, the static input is used when it is not usually possible to learn from the source address of the frame transmitted from the own station to the FDDI ring, although the own bridge unit also has the FDDI MAC address .

The entry position is determined by the control function for the following reason certainly:

It requires a capacity of 2⁴⁸ in the input table to input from 48 bits of the MAC address fixed, and it is practically difficult to do so to realize large capacity.

Accordingly, it becomes necessary to compress the input position by the 48 bits of the MAC address is to be determined, e.g. B. to about 16 bits (64 kilos Entrance). To reduce the likelihood that different MAC If addresses with the same input collide, a function that is effective in the range of 16 bits with a random uniform distribution is strong.

If the control function is used when a new input is to be registered assuming an input utilization rate ρ, the MAC addresses are likely to collide ρ with the registered input. The probability that registration can be performed at the nth time after a collision is made (n-1) times is ρ ^n-1 × (1-ρ). If e.g. B. ρ = 50%, the probability that a registration can be made for the 10th time is 99.9%.

To enable high speed recovery / registration, a control function is implemented in hardware.

Fig. 7 shows the structure of the hardware.

As shown in Fig. 7, it is believed that the control function is that which can be easily done by simple circuits of FX-OR, addition and rotation.

Candidate positions of an entry registration through the control generation are distinguished by the following discrimination method by performing an n- Checking times (e.g. 10 times) with the corresponding MAC address as a keyword determines:

• 1. If an unused entrance is found, a registration is with possible at this entrance.  
• 2. If a registered input by the corresponding MAC address is found, registration at this entrance is possible, and
• 3. If a candidate of 1st or 2nd is not found after an n- has been carried out, an input with a Priority registered. Accordingly, data is input to the oldest Timer value written.

On the other hand, the MAC address is obtained using the same control function with the corresponding MAC address as a key.

Next, the routing control section for realizing registration processing of the input in the input table 1114 and recovery processing of the input from the input table 1114 will be described.

FIG. 8 shows the structure of the guidance control section 1113 shown in FIG. 3.

Fig. 8 shows: interface circuits 11131-11134 for performing an interface with the segmentation control section 1111, the bridge processor 1115, the re-assembly control section 1112 or the common learning path c. Also shown are an aging timer circuit with an old value 11135 , a state management circuit 11136 for performing state management and access control of the input table in accordance with the state, a control subcircuit 11137 for generating a control chain from the MAC address of 48 bits and for obtaining the input position in the input table 1114 , a recovery circuit 11138 for realizing the filtering function, and a registration circuit 11139 for realizing the learning function.

In the control control section 1113 , filtering processing including renewing processing of the aging timer value, segmenting recovery processing, segmenting registration processing, reception path registration processing, and common learning path registration processing and learning processing are integrated.

Accordingly, the above processings are carried out in accordance with the following order of priority.

• 1. To improve the performance of mediation processing, highest priority is assigned to filtering the upward direction.
• 2. Among the diffusion due to unknown regulations is the most useless Traffic communication under connections under the control of the own bridge unit. To avoid this, learning from the receiving FDDI frame under the control of its own bridge unit assigned a higher priority than another learning.
• 3. The learning from the learning path and the common learning path is assigned a lower priority and registration data are temporarily held in FIFOs 111331 and 111341 until there is some time left during processing. Filtering and learning a frequency is done once for each frame, or once for 8 cells on average in terms of a number of cells. Therefore, there is even time left if the processing of 1st and 2nd is assigned a priority. Accordingly, the present processing can be carried out in this remaining time. Refreshing the aging timer value corresponding to each input is carried out intermittently for each input so as not to interrupt the other processings for a long time. Accordingly, since the interval for renewing the aging timer value becomes long and the time required for this processing is short, this processing is given the highest priority.

Fig. 9 shows the change of state of the Leitsteuerungsabschnitts 1113th

As shown in Fig. 9, the guidance control section 1113 has the following three functions:

• 1. a renewal processing of the aging timer value,
• 2. recovery processing,
• 3. registration processing.

The state management circuit 11136 decides a priority order based on requests from the interface circuits 11131 through 11134 with each of the other control sections that may occur simultaneously or the aging timer circuit 11135 . The state management circuit 11136 then manages the state of the guidance control section, controls the state, and accesses the input table 1114 to realize the above function.

The access address at the time of retrieval and registration in the input table 1114 is generated by the control circuit 11137 using the MAC address as a key, and memory read and memory write are in an eight-byte unit and a four-byte, respectively -Unit executed. The operation of the control sub- circuit 11137 is explained below. As an example, the operation of the control circuit 11137 when there has been a request for recovery / registration from the segmentation control section 1111 will be described.

Fig. 10 shows the timing charts of the recovery / registration processing.

In Fig. 10, the operation (a) of the generation of the first control function h 1 , of (b) of the generation of the repeated control function h 2 to hn and (c) of the memory access is carried out by the continuous processing as shown in the drawing .

In other words, the memory access / coincidence differentiation of hi and the generation of the next control chain hi + 1 are carried out in parallel. When the generation of h 2 has started, the generation of the next query h 1 is started.

Fig. 11 shows the state change diagram of the control circuit.

A description will be given starting with the generation of h 1 .

If there is a request for recovery or registration from any of the interface circuits 11131 to 11134 in the request waiting state, the MAC address is read by the corresponding interface circuit based on the result of the priority order discrimination by the state management circuit 11136 and h 1 is used using this MAC Address generated as a key.

Generation of the next request h 1 indicated by the state management circuit 11136 is expected until the generation of h 2 is started while processing is in progress.

Generation from h 2 to hn will be explained next.

When the generation of h 1 has ended, h 2 is generated based on h 1 , and h 3 and above are successively generated. In the meantime, the hi-1 input is accessed in parallel while hi is being generated.

The hi generation processing is completed on the following condition.

In the case of recovery, the hi generation processing is completed when the recovered circuit 11138 has found a desired MAC address or when the maximum control hn (10 times) is reached.

In the case of registration, the hi generation processing is completed when candidates of registration input have been determined by the registration circuit 11139 in accordance with the candidate determination algorithm. A maximum control hn is sought to determine candidates.

Upon completion of retrieving by the retrieval circuit 11138 or registration by the registration circuit 11139, the control circuit 11137 starts In addition to generation of the next h 2, when a generation of the next h has been completed. 1

The recovery processing and the registration processing using the access address generated by the above control subcircuit 11137 will be described next.

The recovery processing is explained first.

The recovery processing is carried out by the recovery circuit 11138 . For the recovery processing, there is a request from the segmentation control section 1111 for the segmentation processing and a request from the bridge processor 1115 .

Fig. 12 shows the state transition diagram for the recovery processing in the recovery circuit the 11,138th

If there is a request for recovery from the state management circuit 11136 in the idle state, the source MAC address (SA) is read by the corresponding interface circuit 11131, 11132 and the generation of h 1 by the control circuit 11137 is expected. When h 1 has been generated, the input from h 2 and above (eight higher order bytes) is read sequentially, starting with h 1 from input table 1114 . Since the eight higher order bytes of input contain a MAC address, a decision is made as to whether that MAC address matches the MAC address that becomes a key. If these MAC addresses match, control generation and memory reading are stopped and the remaining eight low order bytes of the input are read. The input is made known to the appropriate unit and the aging timer value is reset within the four higher order bytes.

If after executing a control total of no more than n times Entrance has been found, a non-entrance is advised. In this case the segmentation processing becomes due to an unknown determination redistributed.

The registration circuit will now be described.

Registration processing is performed by the registration circuit 11139 . As previously described, there are requests from the following directions for registration processing:

• 1. A registration from the segmentation control section (learning the Upward direction);
• 2. A registration from the receiving path (learning from the cells that received through the negative gate of the downward direction);
• 3. A registration from the common learning path (learning from all Downlink multiplex lines).

Fig. 13 shows the state transition diagram of the registration processing shown in the registration circuit 11,139th

If there is a request for registration from the state management circuit 11136 in the idle state, the destination MAC address (DA) is read from the corresponding interface circuit and generation of h 1 by the control circuit 11137 is expected. When h 1 has been generated, the input from h 2 and above (eight higher order bytes) is successively read from h 1 . The eight higher order bytes contain information to be used to determine candidates, ie, the "Apply" / "Not Apply" display, a dynamic / static display, and an aging timer value. Candidates are determined in accordance with the candidate determination algorithm described above. When control summing has been carried out a maximum of n times, the memory reading is stopped and registration data of 16 bytes is written to the candidate entry position four times by dividing the data into four, each part containing four bytes. Then the processing is finished.

The timer value renewal processing for the aging timer that for the Clearing the registry entry is used next.

In the present embodiment, it is allowed to allow the bridge processor 1115 to operate the timer and set a time ΔT of the timer value unit (resolution) to provide flexibility in the resolution of the aging timer value. The renewal processing of the aging timer value over the entire input is carried out intermittently so as not to interrupt the other processings.

Fig. 14 shows the timing chart for renewing the aging timer value.

The timer circuit updates the timer values of all of the M inputs (e.g. 128 K inputs) in the ΔT (resolution) time. If e.g. B. the resolution of the timer value is a minimum of a second is to renew all the inputs the interval Δt for renewal between the inputs as follows:

Δt = one second ÷ 128 K = 7.8 µs

In other words, if the inputs are consecutive in every time interval of 7.6 µs or less, it is possible to change all the inputs in the Renew the resolution value of the timer value. If a renewal of all of that Entries within the time period is expected to be renewed until to the next ΔT timeout.

Fig. 15 shows the state change diagram for renewing the aging timer value.

As shown in Fig. 15, completion of other processing that is currently being executed is sequentially expected every ΔT, and renewal is performed as follows.

The eight higher order bytes of the input are read. In the case of "Apply" and "Dynamic" state becomes the timer value in the corresponding Input in the "Apply" / "Not Apply" display and the dynamic / static display incremented and renewed (writing four bytes higher order).

If the timer value is time-locked, the "Apply" - / "Not Apply" - Display in the corresponding input again for not using (Writing four bytes of higher order) is written, and the input is deleted.

In the present embodiment, the bridge processor 1115 can directly access the input table to perform the following processing.

1. Memory read / write test

The bridge processor 1115 outputs a real address and writes directly to and reads directly from the input table to perform a memory check on the input table.

2. Valid entrance examination

The bridge processor 1115 outputs a real address and reads directly from the input of the input table to judge whether it is valid or not. In other words, the bridge processor 1115 judges whether the input is used or not. The bridge processor 1115 repeats this by sequentially evolving the memory address and looking for a valid input. Then, if it is desired to copy the learned port position information to the external memory or to copy the information to the other bridge unit, the bridge processor reads and copies a found valid input.

3. Entry renewal

The bridge processor registers the input using the MAC address as a key. This is the same as the one described above Registration processing.

According to the first embodiment, there are the following effects.

• 1. It is possible to carry out filtering of the frame and guidance information to learn in the bridge unit that the FDDI is transmitting in a Frame unit and the high-speed connection LAN to Transferred into the cell unit of fixed lengths.
• 2. It is possible to filter and learn at high speed Use the control algorithm in the hardware for recovery and register in the input table.
• 3. Because deleting the input in the input table intermittently and executed consecutively by the aging timer that Equipped accordingly for each input, it becomes possible to use the table to prevent being filled by learning without the hit rate to humiliate.

Because the aging timer value intermittently by advancing the entry position is renewed, the processing of the aging timer does not affect the performance of recovery / registration processing.

The bridge unit relating to the second embodiment of the present Invention relates will be described.

Fig. 16 shows the structure of the network system that uses a bridging unit, which relates to the present embodiment.

As shown in FIG. 16, a bridge unit 91 relating to the present embodiment connects a plurality of FDDIs. To simplify the explanation, two FDDIs are connected in Fig. 16.

For the line in the bridge unit 91 relating to the present second embodiment, the position where the MAC address is located is shown as a port number for connecting FDDIs.

For example, the MAC address positions are shown as port A and port B. There two FDDIs are connected in the present embodiment, there are two Gates.

It is possible to perform an address filter by retrieving a port number from the input table 9114 using the destination address as a key and deciding whether to decide on the transmitted port number or whether to remove it. The learning is carried out by registering the set of the source address and the incoming gate number to the input table 9114 .

Fig. 17 shows the structure of the input table 9114th

The direction of the source MAC address is shown as an FDDI port number, and the others are the same as those in the first described above Embodiment.

Fig. 18 shows the construction of the bridge unit 91.

In Fig. 18 there is shown: a bridging unit 91 for connecting the FDDIs and a switching control section 911th FDDI control sections (gates A to D) 912 A to 912 D correspond to FDDIs A to D. A master control section 9113 performs station position learning and filtering of a switched frame, and an input table is designated 9114 .

The filtering and learning processing is carried out as follows.

If e.g. For example, if a frame has been received by the FDDI A, the bridge processor 9115 DA and SA recovers from the received frame stored in the transmission / reception buffer 912 A 5 and transmits them to the routing control section 9113 .

For filtering, the routing control section 9113 retrieves the input table 9114 from the DA under the control of the routing control section 113 to obtain a port number of the port where the destination port exists.

Then a mediation or removal decision is as follows performed based on the result of the above operation.

• 1. The frame is removed when the number of goals is equal to arriving number of goals.
• 2. The frame is conveyed to the corresponding gate when the Determination goal number is not equal to the incoming goal number. In other Words become the receiving frame in the send and receive buffer of the corresponding gate is copied and then transmitted.
• 3. The framework is conveyed to all the goals if no number of goals is found.
  The learning is carried out by registering the set of the SA and the incoming gate number in the input table 1114 under the control of the guidance control section 9113 .
  The operation of the guidance control section 9113 is the same as that of the first embodiment described above, and therefore a description of this operation is omitted here.

According to the second embodiment above, there are the following advantages:

• 1. It is possible to filter and learn at high speed to execute using the control algorithm in the hardware for recovery and registration in the entry table.
• 2. Since deleting the input in the input table intermittently and is executed in sequence by the aging timer, the is equipped according to each input, it is possible to see the table of it to keep being filled by learning without increasing the hit rate humiliate.

Because the aging timer value intermittently by advancing the entry position is renewed, the aging timer processing has no effect on the performance of recovery / registration processing.

As described above, according to the present invention, it is possible to use one To create a bridge unit that can keep the table from learning to be filled without lowering the hit rate, and the flexibility of the Movement can correspond to the connection position. It is also possible to get one  Address filter unit to create the processing efficiency of the address filtering processing can improve.

As described above, according to the address filter unit referring to the The present invention involves, according to each address information registration Timers created, and a timer renewal unit switches sequentially and intermittently continue each timer value. If the timer value is equal to or becomes larger than a predetermined value, registration of the address information, which corresponds to the timer, deleted from the input table so that it is possible to keep the table from being filled by learning without lowering the hit rate.

Furthermore, according to the address filter unit referring to the present The invention relates to a timer corresponding to each address information registration created and if a timer renewal unit by a starter unit is started at every constant period ΔT, the timer renewal unit switches the value of each timer according to the registered address information sequentially and intermittently until the end. If the timer value is one reached predetermined value or above, the registration of the address information deleted according to this timer of the input table so that it it is possible to keep the table from being filled by learning without lowering the hit rate.

Furthermore, according to the address filter unit referring to the present Invention relates, in the first step, a function (fi (a), i = 1 to n) Source address resulting from the incoming information frame at the time of a Registry is extracted in the entry table, or the destination address, those from the incoming information frame at the time of retrieval is extracted from the input table, successively as an address of the Input table generated. The second step at the time is the Registration decided whether to register the address information in the address is or not, which is generated in the first step of the input table. At the third step, at the time of recovery, it is decided whether the Address information registered in the address used in the first step of the input table is generated, the desired information is or not. By the above processings, it is possible to use the efficiency of the Improve input table. Furthermore, the efficiency of address filter processing by sequentially operating the first step with the second step or the third step can be improved.  

Furthermore decides according to the address filter unit, which is based on the present Invention relates, the priority order decision unit on the priority order, if at least two processing operations compete with each other registering the incoming address information from the branch LAN in the input table, the registration of the incoming address information from N transmission paths of the switching network in the Input table and the recovery of the address information from the Entry table. In the meantime, the execution unit carries out the processing based on the result of the above processing. Through this As a result, the address filter processing can be quietly performed in improved processing. If a storage unit is provided for temporarily storing the incoming address information from the switching network, the execution unit registers the address information in the input table, which is stored in the storage unit during the period, while the other processing is not carried out. Through this Processing is possible, the throughput performance of the current address filter processing ensure.

According to the address filter unit relating to the present invention the priority order decision unit continues to decide on the priority order performing registration of the incoming address information from the branch LAN in the input table, the registration of the incoming Address information from N transmission paths of the switching network the input table and the retrieval of the address information from the Input table, so that processing quietly with improved efficiency is performed. The address generation unit generates sequentially as an address the input table a function (fi (a); i = 1 to n) of the source address that from the incoming information frame at the time of registration in the Input table is extracted, or the destination address, which from the incoming information frames at the time of retrieval from the Input table is extracted. The registration address candidate decision unit decides on a registration address at the time of registration from the addresses sequentially by the address generation unit from the Input table are generated, and the recovery unit wins to the Time of retrieval of the desired address information from the address again, which is generated by the address generation unit in the input table, so that the efficiency of using the input table is improved. Furthermore, the address generation processing for generating the i-th address by the address generation unit, the recovery processing for Retrieving the (i-1) th address by the retrieval unit or  the decision processing for examining the (i-1) th address by the Registration address decision unit executed in parallel to the Improve processing efficiency.

According to the switching unit relating to the present invention the address filter unit continues to perform address filter processing based on the result of address filter processing, and a data format conversion unit converts the information frame that goes to the other network into that The data format of the network to which the frame communicates is to be conveyed must become.

According to the bridge unit related to the present invention the address filter unit continues to perform address filter processing. Then walk in the switch based on the result of the address filter processing by the address filter unit, the recovery unit the information frame, to be switched from the switching network to the branch LAN, into the data format of the branch LAN. Based on the result of the The processing unit converts the address of the processing to the information frame, from the branch LAN to the switching network mediate is in the data format of the mediation network. In the meantime the LAN control section interfaces with the branch LAN and enables the information frame to and from the branch LAN transferred to.

In the present bridge unit, it is when the address filter unit is provided which is address information in the input table by extracting the Address information from the information frame on the branch LAN registered, the information frame that connects to the own bridge unit on the Switching network is transferred, and the information framework that to the is sent to another bridge unit that is different from the information frame that by at least the own bridge unit on the switching network to the Switching network is switched, it is desirable that that of the switching network received information frames all to the branch LAN are conveyed without having the address filter processing.

An example of the case where the constructions of the guidance control section 1113, 9113 and the input table 1114, 9114 in the first and second embodiments are compact and of high speed type will now be described.

A third embodiment of the present invention is explained below.

First, a dynamic random access memory (D-RAM) is explained, which as a Memory element is used in the memory circuit (corresponding to the guidance control section and the entry table), which refer to the present Embodiment relates.

Fig. 19 shows a high speed page mode read change write cycle of the D-RAM.

As shown in Fig. 19, the read-change-write is a mode in which WE is negative, CAS is confirmed, and data is read from Dout, and then WE is confirmed in the same cycle so that data is in the same Address to be written by Din. In the present embodiment, the D-RAM is used in the high speed page mode read change write mode which is a combination of the read change write mode and a page mode which is a high speed mode. Of course, in this case, renewal of the column address is performed in synchronism with the negative of CAS.

The page mode at high speed is the mode in which the data read the same row continuously by changing the column address alone and the page mode at high speed becomes widespread along with the read-change-write mode in the commercially available D-RAM IC or the like is used.

Next is the illustration of the operation of the memory circuit that is based on the present embodiment relates, explained.

The memory circuit relating to the present embodiment is used the control procedure in the recovery / registration processing.

The control procedure is the procedure for calculating a position where a Data value by performing a predetermined conversion of the data value save is.

In other words, according to the control procedure over elements to Store data in accordance with the data value or a value k (the key is called) that is contained in the data.  Therefore, recovery of data can only be done by checking it Items are finished and processing is very efficient.

According to the control method, there is a case that h (k) = h (k ′), where k is different from k ′. However, in this case there will be another check hi (k) (i = 2 to n) to avoid a collision.

In the recovery / registration processing, a value derived from the Control function, that is h (k), is generated as an address for the memory element used. In other words, a registration in the storage location performed, indicated by h (k), or data with the data compared, which are stored in the storage position indicated by h (k) becomes.

Fig. 20 shows the structure of the database using the memory circuit relating to the present embodiment.

In Fig. 20, there is shown: a memory circuit 113 corresponding to the routing control section 1113 , etc., a processing section 1131 and an address generation section 1132 . Also shown is a memory element 114 , which corresponds to the input table 1114 , etc., and a processing unit 115 , which corresponds to the bridge processor 1115 , etc. In the present exemplary embodiment, the memory circuit 113 is integrated in an integrated circuit on a chip.

A signal f denotes a function for designating processing of the memory circuit 113 by the processing unit 115 , r denotes a result of the processing by the memory circuit 113 , di denotes input data from the processing unit 115 , z denotes data to be written into a memory element 114 , do denotes data to be read from the memory element 114 and k denotes a value that becomes a key of the control function h (k). Details of the function will be described later.

The operation of the memory circuit 113 is explained based on the timing chart shown in FIG. 21.

First, the key k is extracted from the input data di in the data processing section 1131 , and the row address and the column address are generated from the control function h (k) in the address generation unit 1132 , and they are kept in the storage element 114 .

Based on the read data do and the input data di read from the address, the data processing section 1131 processes the data to generate the write data z and writes this data z into the storage element 114 . The data processing is decided from the relationship between the input data di and the read data do.

The column address is incremented and the above operation is repeated to the completion condition, based on the relationship between the input data di and the reading data do is to be decided is fulfilled.

In other words, in the present embodiment, hi + 1 () = hi () +1 is set to make it possible to make the page mode read change write cycle high speed of D-RAM, and a series of operations through the above-described re-inspection is in realized in one cycle.

The above operation is explained below in accordance with the state change shown in FIG. 22.

The address generation section 1137 generates the row address and the column address from the first control function h 1 (k) of the key k, and the processing section 1131 reads data from the corresponding address.

For purposes of explanation, assume that the key k is a value which is contained in the input data di.

The data processing section 1131 generates the write data z from the input data di and the read data do in accordance with the condition of the function f and the read data do, and writes the data z to the same address. Until the completion condition corresponding to the respective functions is met, the column address generated from the recheck function hi (k) (i = 2 to n) is held, and the above processing is repeated. As described above, hi + 1 () = hi () +1 is assumed in the present embodiment.

When the processing has been completed, the result r of the processing is reversed to the CPU 115 .

Assuming that the D-RAM has 4M bits and the data length is 64 bits, the maximum number of row addresses and column addresses is calculated, to be 4M bits / 64 bits = 64K inputs. So if a repeat Control is executed eight (n) times, the column address can be 0 to 7, and the row address can be from 0 to 8k-1.

Details of the functions described above are explained below.

The memory circuit relating to the present embodiment has the functions of 1. recovery processing, 2. registration processing and 3. aging timer renewal processing.

The signal f ( Fig. 20) denotes one of the above functions, and the memory circuit 113 executes processing based on the displayed function.

Details of each of the processings will be explained with reference to Fig 23, Fig 24 and 25 and Fig. 26..:

Fig. 23 shows the structure of the fields of each input of the memory element 114. As shown in Fig. 23, the fields have a key k, an input e and a timer t.

Fig. 24 shows the details of the memory circuit 113.

In Fig. 24 is shown: a processing section 1131 for controlling the data processing, a comparator circuit 11311 for comparing each of the fields k, e and t of the input data di with each of the fields k, e and t of the read data do, and performs a predetermined operation , based on the result of the comparison. Data processing circuits 11312, 11313 and 11314 perform predetermined data processing of k, e and t from di and k, e and t from do in accordance with displays 11f1, 11f2 and 11f3 of the comparator circuit to supply write data z (k, e, t) produce.

An address generation unit 1132 generates an address for the memory element 114 in accordance with a display from the data processing section 1131 .

A state monitor circuit 11321 receives a start indication from the data processing section 1131 , controls the state of the memory element access by monitoring the state in accordance with the state change to be described later, and continues the operation until an end indication is received from the data processing section 1131 . A control generation circuit 11322 generates a control from the key k, and counter circuits 11323 and 11324 refresh the row and column addresses in accordance with a command from the condition monitoring circuit, respectively.

The processing of the memory circuit 113 is commanded by the CPU 115 , which outputs the data di to the memory circuit 113 , and outputs the function f.

Thereafter, the CPU 115 waits until the following processing in the memory circuit 113 has ended.

First, the data processing section 1131 in the memory circuit 113 is explained in detail:

FIGS. 25 and 26 show the contents of processing by the data processing section 1131st

The comparator circuit 11311 decodes the function f received from the CPU 115 , transfers the key k to the address generation circuit 1132, and performs the following operation.

• 1. For the recovery processing, the comparator circuit 11311 repeats the read-change-write processing until the key k of the input data di matches the key k of the read data do.
  If the keys do not match in the above method, the processing circuits 11312 to 11314 are notified that no change has been made to the read data do, and the processing is repeated.
  On the other hand, if the keys match in the above processing, the comparator circuit 11311 indicates to the processing circuit 11314 that the timer value t of the read data do is cleared, and indicates to the processing circuits 11312 and 11313 that the data is not processed (the do are passed through) ).
  Then, an end of the processing of the condition monitoring circuit 11321 is indicated ( Fig. 26a).
  The processing is also completed if the keys do not match after the control sum is repeated up to the maximum number of control summations n.
  After the processing is completed, the comparator circuit 11311 returns the processing result r (discovery / no discovery) to the CPU 115 . The CPU 115 receives the result r and reads the read data do (desired data) in the case of detection and ends the recovery processing in the memory circuit 113 .
• 2. For the recovery processing, the comparator circuit 11311 repeats the processing of finding a registrable position until di (k) matches do (k) or until a space is found where di (k) can be registered. If the space cannot be found, the processing circuits 1131 to 11314 are informed that the read data do not be processed, and the processing is repeated.
  On the other hand, when the space has been found, the processing circuits 11312 and 11313 are notified that the input data di is output, and the processing circuit 11314 is reported that the timer value t is cleared.
  Then, completion of the processing of the condition monitoring circuit 11321 is indicated ( Fig. 26b). A condition for a registrable area is the case where the key data match (di (k) = do (k)) or the case where the key data is empty (do (k) = "").
  The processing is also completed if no registerable area is found after a control sum is repeated up to the maximum number of control summations (n times).
  After the processing is completed, the comparator circuit 11311 returns the processing result r (registration / no registration) to the CPU 115 . Upon receiving the result r, the CPU 115 ends the registration to the memory circuit 113 .
• 3. An aging timer renewal procedure is performed as follows:
  The aging timer renewal procedure relates to processing an input clear that has not been used within a predetermined time.
  In the present processing, no control function is used to generate an address and the value of a key is made. The row address and the column address are simply incremented to repeat the processing.
  For data processing, processing circuit 11314 is informed that the timer value of the read data is incremented (z (t) = do (t) +1), and processing circuits 11312 and 11313 are informed that data is not being processed ( Fig. 26c ).
  When the timer has timed out, the key data of the corresponding position is invalidated (e.g. 0 is written) and the data is cleared ( Fig. 26d).
  When the control total has reached the maximum number (n times), the processing is completed.
  If the aging timer function is not used, the processing unit 115 cannot output this function.

In the above processing 1 to 3, the write data z (k), z (e) and z (t) generated in the processing circuits 11312 to 11314 ( Fig. 26) are transferred to the main storage element 114 under the control of the Address generation section 1132 is written.

Next, the address generation section 1132 will be explained in detail:

The status monitor circuit 11321 starts operation based on the start display from the comparator circuit 11311 and outputs the timing signal 11321 to the memory element 114 and thus continues the operation until there is an end display ( FIG. 24).

The control generation circuit 11322 generates the row address from the key k obtained from the comparator circuit 11311 and loads the original row address into the counter circuit 11323 .

The counter circuits 11323 and 11324 hold the row address 11323 a and the column address 11324 a, respectively , and increment in accordance with the timings 11321 a and 11321 b, which are indicated by the condition monitoring circuit 11321 .

As described above, it is according to the present embodiment possible to realize a database, which is a repeated control procedure used, and in particular there are the following effects.

• 1. It is possible to start a recovery or registration process in the Execute memory in one cycle.
• 2. It is possible to delete registration data for a predetermined period are not required.
• 3. It is possible to change the reading timing and speed increase Reduce processing when the data is handled in a chip.

In the above embodiment, the data processing section, the address generation section and the memory are realized in one chip. However, the chip may be divided as shown in FIGS. 27 (a) to (d) according to other conditions such as a memory capacity or the memory circuit.

More specifically, FIG. 27 (a) shows a case where the data processing section 1131 and the address generation section are integrated 1132, and only the D-RAM 114 is disconnected. With this arrangement, it is possible to realize a database function by using a general D-RAM.

Fig. 27 (b) shows a case where the data processing section 1131 , the address generation section 1132 and the D-RAM 114 are separated. With this arrangement, it is possible to have flexibility in the change process and the control process according to the application process.

Fig. 27 (c) shows a case where the data processing section 1131 and the D-RAM 114 are integrated, and the address generation section 1132 is separated. This arrangement makes it possible to have flexibility in the control method and to implement a continuous data processing in a memory for storing the function.

Fig. 27 (d) shows a case where the address generation section 1132 and the D-RAM 114 are integrated, and the data processing section 1131 is separated. With this arrangement, it is possible to have flexibility in the change method and to realize a memory for storing the function of continuously generating the address after the control method.

The bridge unit using the memory circuit will now be described is explained as the address database in the third embodiment, and as a fourth embodiment of the present invention.

The structure of the network system mutually connected by the bridge unit relating to the fourth embodiment is the same as that shown in FIG. 16.

As shown in Fig. 16, the bridge unit relating to the present embodiment uses a variety of fiber-distributed data interfaces (FDDIs).

The bridge unit has an address table for storing a position, where a connection exists. In the case of communicating data, this refers to the bridge unit to the address table and the destination address of the incoming packet to make a decision on an operator or a Remove to hit. In other words, the bridge unit performs address filter processing out.

More specifically, if the destination port of the packet is in the direction of the the other LAN or if the destination is not known, the packet will switched and the packet is removed when the destination port in the arriving direction.

Furthermore, the bridge unit refers to the incoming package and registers the source address and the connection position in the address line doing learning.

The address table is viewed every predetermined period for the purpose of:  

• 1. Prevent the table from being filled by learning
• 2. Flexible coping with the movement of the connection position, and one Registration of the connections to which no packet is transmitted deleted.

Fig. 16 shows the case where the bridge unit connects two FDDIs to simplify the explanation.

In the bridge unit, which relates to the present 10161 00070 552 001000280000000200012000285911005000040 0002004103888 00004 10042nd embodiment, the route is carried out by expressing the position where the address with medium access control (MAC) (48 bits) by the number of ports Bridge unit for connecting the FDDIs exists.

For example, the MAC address positions are expressed as a port A and a port B. It is assumed that two FDDIs in the present embodiment are to be connected. Therefore there are two gates.

The structure of this address table is the same as that shown in FIG. 17 and FIG. 23.

The address table has MAC addresses, FDDI gate numbers, the directions of the Show MAC addresses, and the aging timer.

Fig. 28 shows the structure of the bridge unit relating to the fourth embodiment of the present invention. This corresponds to the structure of the bridge unit in FIG. 18.

In Fig. 28 is shown: a bridging unit 91 for connecting the FDDIs and a connection control section 911th FDDI control sections 912 A to 912 D (gates A to D) correspond to FDDIs A to D.

An address database 9116 carries out the learning of the station position and a discrimination of switching / removing the switched frame (filtering), and this address database uses the memory circuit 113 relating to the third embodiment.

A processor is designated 9115 .

The operation of the 9115 processor is explained below.

First, the filtering is carried out as follows.

When a frame has been received by the FDDI A, e.g. B. the processor 9115 a destination address (DA) of the received frame stored in the transmission / reception buffer 912 A 5 , transmits the DA to the address database 9116 and outputs a retrieval function which is explained in the third embodiment. The processor 9115 can recognize the number of gates of the gate where the destination terminal exists from the data obtained from the address database 9116 (do in the previous embodiment).

In the address database 9116 , the MAC address corresponds to the key field in FIG. 23, the number of gates corresponds to the input field, and the aging timer corresponds to the timer field in FIG. 23.

As a result of the above processing is carried out through a switch or a Removal decided as follows.

• 1. The frame is removed when the number of goals determined is equal to arriving number of goals.
• 2. The frame is conveyed to the corresponding gate when the Determination goal number is not equal to the incoming goal number. In other Words become the received frame in the transmit and receive buffer of the corresponding gate is copied and then transmitted.
• 3. The frame is conveyed to all the goals if the goal number is determined is not found.

The learning is carried out by transferring the set of the source address (SA) and the incoming gate number to the address database 9116 and outputting the registration function explained in the third embodiment.

The value of the aging timer corresponding to the row address memory is renewed by transferring the row address to the address database 9116 and outputting the aging timer function explained in the third embodiment. By intermittently incrementing the row address and repeating this processing, it becomes possible to renew the aging timer value that corresponds to all of the memory addresses.

If e.g. B. no aging timer is required in the bridge unit or if it is not necessary to mix a registration value in the system the above processing and the timer field are omitted.

As described above, it is according to the present embodiment possible to improve the processing efficiency of the address filter processing and reduce the physical quantity of the hardware.

In each of the above-described embodiments, the case has been described where the memory circuit is used for the database. However, it is not necessary to mention that the memory circuit that relates to the present Invention relates also to the other image processing described above can be applied generally.

In the above embodiments, the address generation by Control procedure carried out. However, the address can be generated by a Procedures are carried out for processing in accordance with the Processing using the memory circuit is suitable. Furthermore, about the structure of the data fields and the functions to be implemented are suitable to be decided in accordance with the processing performed by the memory circuit used.

According to each of the above-described embodiments, it is possible to use a Data processing of the database in one cycle by only one access to the Execute storage element to thereby speed up the processing. Furthermore, the processing speed can be realized by realizing the memory circuit be increased in a chip.

As described above, according to the present invention, it is possible to use one To create a memory circuit that processes data recovery / Can perform registration etc. at high speed.

In other words, according to the memory circuit referring to the the present invention relates to reading data from the memory into the address, which is generated by the address generation section for the data which is external are entered. A comparison section decides on the basis of this data a data generation mode for the data that is in place in the memory data read from the memory are to be written. Based on the As a result of this decision, the data processing section generates the to write data and write the data to memory.  

Until one of the predetermined conditions for the relationship between the entered data and the read data is satisfied, data is sequential from memory in accordance with a predetermined rule for a Read data element that has been entered and the above data generation and the writing will be repeated.

As described above, according to the memory circuit referring to the The present invention relates to the recovery processing and the Registration processing at a high speed by, for example, the Hardware can be implemented in the database unit or the like. Farther it is under predetermined conditions in image processing or the like possible to perform processing at high speed to get new data by editing input data to obtain image data stored in the Memory are stored.

It is also possible to speed up processing arranging such that the above memory has a memory with dynamic random access, which has a read-change-write mode, and that reading the data from memory into the address that was read and writing the data through the data processing section generated in one cycle in the read-change-write cycle will.

In addition, it is possible to continue processing at high speed by arranging such that the above-mentioned dynamic Random Access Memory has a high speed page mode that the address generating section has a row address and a column address of the dynamic random access memory for the first address generated in the data are read out to compare them with the data entered from outside and only one column address for the second address and the subsequent ones Generated addresses to which the above data are successively generated, and that reading data from memory and writing data that are generated in the read address by the data processing section in which Pages mode run at high speed.

Furthermore, it is in the case where the above memory circuit as a database used, possible, recovery and registration processing efficiently by applying the control procedure to the data that a Have received the address generation.  

According to the data recovery and registration procedures that apply to the relate to the present invention, data recovery and Data registration carried out through the control process, and since the control function hn = h1 + n (where n is a number of control times), it is it is still possible to recover and register the storage data in the dynamic random access memory in the page mode read change write mode run at high speed.

Furthermore, according to the memory circuit IC, which relates to the present Invention relates to integrating the memory circuit so that it has high advantages Speed, high charge density, easy operation, etc. there.

According to the bridge unit relating to the present invention, there therefore, this memory circuit IC is used as the address database possible to perform address filter processing at high speed and to have a compact structure of the memory circuit IC.

Claims (24)

An address filter unit for performing address filter processing between a plurality of networks using address information extracted from an incoming information frame registered in an input table ( 11, 21, 1114, 2114 ), the address filter unit comprising:
Timers each provided to correspond to a respective address information registration;
timer renewal means ( 11135 ) for sequentially and intermittently incrementing each timer value ; and means for deleting the registration of address information corresponding to the timers from the input table. 2. Address filter unit for performing address filter processing between a plurality of networks using address information extracted from an incoming information frame registered in an input table, the address filter unit comprising:
Timers provided to correspond to each address information registration;
timer renewal means for sequentially and intermittently incrementing each timer value; start means for starting the timer renewal means in a predetermined cycle ΔT and means for deleting the registration of the address information corresponding to the timers from the input table when a timer value becomes a predetermined value or more. 3. The address filter unit of claim 2, wherein the timer renewal device intermittently increments each timer value in a time interval Δt, where ΔtΔT ÷ is a maximum registration number in the entry table.   4. Address filtering method for performing an address of processing between a plurality of networks using address information extracted from an incoming information frame registered in an input table, the address filtering method comprising:
a first step of sequentially generating, as an address of the input table, a function (fi (a), i = 1 to n) a source address extracted from an incoming information frame at the time of registration in the input table or a destination address (a) extracted from an incoming information frame at the time of retrieval from the entry table;
a second step for deciding whether or not information can be registered in an address generated in the first step of the entry table at the time of registration; and
a third step for deciding whether or not address information registered in the address generated in the first step in the input table is desired information at the time of retrieval. 5. Address filtering method according to claim 4, wherein the first step and the second Step or the third step can be carried out in succession. 6. The address filtering method according to claim 4, wherein at the time of recovery, if it has been decided in the third step that a Address information registered in the address fi (a) of the input table, is a desired information, the recovery is ended, and if it has been decided that address information contained in the address fi (a) the entry table is registered, is not desirable information that Retrieval of the address fi + 1 (a) of the input table contained in the first step is generated, is continued. 7. Address filter unit for executing an address filtering process between Branch LANs and switching networks, the N (N1) logical transmission paths or have physical transmission paths through Retrieve address information from an incoming Extracted information frame, which is registered in an input table, the address filter unit having:  a priority order decision device for deciding on a Priority order of registration of address information provided by the Branch LANs in the entry table comes up, the registration of the Address information from the N transmission paths of the switching network comes into the entry table and a recovery of the Address information from the input table; and an execution device to execute processing in accordance with the result of a Decision. 8. Address filter unit according to claim 7, wherein the order of priority in the Magnitude of a retrieval of the address information from the Input table is a registration of the address information that is provided by the Branch LANs come into the entry table, and a registration of the Address information from the switching network to the entry table is coming. 9. Address filter unit according to claim 7, wherein the address filter unit Contains memory device for temporarily storing address information, which comes from the switching network and the execution device an address information registered in the storage device in the Input table is stored during a period while other processing cannot be executed. 10. Address filter unit for performing address filter processing between branch LANs and switching networks having N (N1) logical transmission paths or physical transmission paths by retrieving address information extracted from an incoming information frame registered in an input table ( 1114 ), wherein the address filter unit has:
priority order deciding means for deciding a priority order of performing registration of address information coming from the branch LANs into the entry table, registration of address information coming from the N transmission paths of the switching network into the entry table and retrieval of address information from the entry table;
an address generator ( 1132 ) for sequentially generating, as an address of the input table, a function (fi (a), i = 1 to n), a source address extracted from an incoming information frame at the time of registration in the input table, or a destination address ( a) extracted from an incoming information frame at the time of retrieval from the entry table;
registration address candidate deciding means ( 11139 ) for deciding a registration address among addresses sequentially generated by the address generating means in the entry table at the time of registration;
retrieval means ( 11138 ) for retrieving desired address information from addresses generated by the address generation means in the input table at the time of retrieval; and
means for parallel processing the address generation processing for generating an i-th address by the address generation means, the recovery processing for retrieving an (i-1) th address by the recovery means, or the decision processing for deciding on an (i-1) th address the registrant candidate decision facility. 11. Switching unit for connecting a variety of networks that having: an address filter unit according to claim 1, 2, 3, 4, 5, 6, 7, 8 or 9; and a Data format conversion device for converting the data format of a Information framework that is linked to another network as a result of one Address filter processing is to be conveyed by the address filter unit in one Data format of the network to which the information frame is conveyed. 12. Bridge unit ( 91 ), which has:
a switching unit containing an address filter unit according to claim 1, 2, 3, 4 or 5 for connecting branch LANs and a switching network having N (N1) logical transmission paths or physical transmission paths, or an address filter unit according to claim 6, 7, 8 or 9, and a reassembly means for converting the data format of an information frame to be switched to branch LANs from the switching network as a result of address filter processing by the address filter unit into a data format of the branch LANs to which the information frame is transmitted , and segmentation means for converting the data format of an information frame to be switched to the switching network from the branch LANs as a result of address filter processing into a data format of the switching network to which the information frame is switched; and
a branch LAN control section for controlling the interface with the branch LANs. 13. bridge unit according to claim 12, wherein the address filter unit contains address information from an information frame on branch LANs extracted from an information frame that is transmitted to its own bridge in the switching network, and from an information frame that is transmitted to another bridge unit that is other than an information frame that goes to the switching network at least through its own bridge unit in the switching network is switched, and the address information in the input table registered; and the bridge unit conveys the whole information frame, that of the Switching network to the branch LANs is received without one Execute address filter processing. 14. Memory circuit comprising:
a memory ( 114 );
a comparison section ( 11311 ) for deciding a data generation mode based on data input from the outside and data read from the memory;
a data processing section ( 11312, 11313, 11314 ) for generating data to be written in an address from which data has been read from the memory in accordance with a data generation mode decided by the comparison section; and
an address generation section ( 1132 ) for sequentially generating an address based on predetermined rules up to one of predetermined conditions for a relationship between input data and data read out from the memory. 15. The memory circuit of claim 14, wherein each element of the data is through a plurality of fields is structured and the data processing section a variety of processing circuits for generating the data has to be written independently in each field. 16. The memory circuit of claim 14, wherein one of the predetermined conditions is a number of times by which the comparison section makes data has read the memory to the data with the entered data to compare. 17. The memory circuit according to claim 14, wherein the comparison section has a Data generation mode decides based on a function signal that is to be entered from the outside in order to function the comparison circuit assign, and also data that is entered from the outside and data that are read from the memory. 18. The memory circuit of claim 14, wherein the memory is dynamic Random access memory with a read-change-write mode, and writing data from memory and writing data that are generated by the data processing section into a read address executed in one cycle in the read-change-write cycle. 19. The memory circuit of claim 18, wherein the memory ( 114 ) is a high-speed dynamic random access memory;
the address generating section ( 1132 ) generates a row address and a column address of the dynamic random access memory for an address in which data is read out to compare this data at a first time with the data input from the outside and only generates a column address for the second address and subsequent addresses to be generated sequentially; and
reading the data from the memory and writing the data generated by the data processing section to a read address in a page mode is performed at high speed. The memory circuit according to claim 14, wherein the address generation section ( 1132 ) generates an address by the control method using the input data or part of the data as a key. The memory circuit according to claim 19, wherein the address generation section ( 1132 ) generates a row address and a column address of the dynamic random access memory for an address in which data is read to compare this data with the data input from the outside at the first time according to the Control method using the inputted data or a part of this data as a key, and generates a column address by sequentially increasing the column address generated at the first time for the second address and subsequent addresses to be generated sequentially, and reading the data out the storage and writing of the data in a page mode read change write mode at high speed. 22. A method for recovering and registering data, one being Recovery and registration of storage data in one dynamic random access memory in a page mode read change write mode run at high speed, under Assumption of a control function of hn = h1 + n (where n is the number of one Repeating a control sum is). 23. A memory circuit IC containing a memory circuit according to claim 14. 24. Bridge unit for connecting a variety of networks to one Perform address filter processing using an address database, wherein the address database by a memory circuit IC according to claim 23 is constructed.