KR950003386Y1 - Sleep mode cancelling unit in data processor - Google Patents

Abstract

No content.

Description

Sleep mode release device of information processing equipment

Figure is a detailed circuit diagram of a sleep mode release device of an information processing device according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

141,142,143: Inverter G41: Exclusive OR Gate

G43, G45: NAND gate G44, G46: AND gate

G42: OR gate DF1, DF2, DF3: D type flip flop

The present invention relates to a device for releasing a sleep mode of an information processing device, and more specifically, an interrupt signal for waking up a sleep mode without using a microcontroller. The present invention relates to an apparatus for releasing a sleep mode of an information processing apparatus that can easily design a product by reducing the cost and reduce the cost of the product.

In a small portable information processing device such as a notebook size personal computer or a word processor, a central processing unit (CPU) is used when there is no input / output of data until a certain time from a peripheral device. In order to reduce power consumption, the CPU enters the sleep mode by stopping the clock input of the CPU or supplying a low frequency clock until an interrupt signal is inputted to the CPU. In addition, when an interrupt signal for requesting the release of the sleep mode is input, a method of returning the clock of the central processing unit to its original state is generally used.

Conventionally, as described above, an interrupt signal used for requesting the central processing unit to release the sleep mode is generated through a device such as a microcontroller that is specifically programmed.

However, the conventional interrupt generation circuit for releasing the sleep mode has a disadvantage in that a specific program is required for the microcontroller to operate. These drawbacks lead to the inconvenience that the hardware engineer must have some knowledge of the software when designing the hardware, and also raises the cost of the product by using expensive microcontrollers. .

Accordingly, an object of the present invention is to solve the above-mentioned disadvantages, and by generating an interrupt signal for releasing the sleep mode without using a microcontroller, it is easy to design the product and reduce the cost of the product. The present invention provides a device for releasing a sleep mode of an information processing device.

The structure of this invention for achieving the above object, AC / DC adapter detection unit for detecting whether or not the AC / DC adapter (adaptor) is connected to the system; A system state detection unit for detecting whether power supply to the system is cut off or power supply to the liquid crystal display panel is closed or the liquid crystal display panel is closed; A system access detection unit for detecting input / output of data from a peripheral device of the information processing device; A sleep mode releasing unit for combining the signals input from the AC / DC adapter detector, the system status detector, and the system access detector to generate an interrupt signal for the CPU to be released from the sleep mode; When the interlap signal is input from the sleep mode canceling unit, the central processing unit is released to the sleep mode.

With reference to the accompanying drawings, a preferred embodiment for easily carrying out this invention by the above-described configuration will be described in detail.

Figure is a detailed circuit diagram of a sleep mode release device of an information processing device according to an embodiment of the present invention. As shown in the figure, the configuration of the sleep mode releasing device of the information processing device according to the embodiment of the present invention is the AC / DC adapter detection unit 10, the system state detection unit 20, the system access detection unit 30 ), A sleep mode canceling unit 40 having an input connected to an output terminal of the AC / DC adapter detecting unit 10, the system state detecting unit 20, and the system access detecting unit 30, and a sleep mode canceling unit 40. It consists of a central processing unit 50 is connected to the input of the output terminal.

In the sleep mode canceling unit 40, the input terminal D is connected to the adapter connection signal line ADPIN of the sensing unit 10 of the AC / DC adapter, and the clock terminal is connected to the refresh request signal line REREFQ. And a first D-type flip-flop DF1 having a clear terminal CLR connected to the power state good signal line PWRGOOD, an AC / DC adapter detector 10 and an adapter output signal line ADPIN; Exclusive OR gate G41 connected to an inverted output terminal 1Q of the first D-type flip-flop DF1, and a system power off signal line SPWROFF of the system state detector 20, respectively. A first inverter I41 connected to an input terminal thereof, an OR gate G42 connected to an output terminal of the exclusive OR gate and the first inverter I41, and a system state sensing unit 20 Output terminal of the second inverter (I42) and the second inverter (I42) connected to the input terminal of the liquid crystal display opening / closing signal line (/ LICDCLOSE) A second D-type flip-flop DF2 connected to the input terminal D, a clock terminal connected to the refresh request signal line REFREQ, and a clear terminal CLR connected to the power state positive signal line PWRGOOD, and a second inverter NAND gate G43 having an input terminal connected to an output terminal of I42 and an inverting output terminal / Q of second D flip-flop DF2, and a power-off signal line of system state sensing unit 20 AND gate G44 having an input terminal connected to a third inverter I43 connected to an input terminal of the PWROFF, an output terminal of the third inverter I43, and a system access signal line SYSACC of the system access detection unit 30, respectively. ), And a third D having an input terminal D connected to the output terminal of the AND gate G44, a clock terminal connected to the refresh request signal line REREFQ, and a clear terminal CLR connected to the power state positive signal line PWRGOOD. The flip-flop DF3, the output terminal of the AND gate G44, and the inverted output terminal of the third D-type flip-flop DF3. Input terminals are respectively connected to the output terminals of the NAND gate G45 and the OR gate G42 and the NAND gates G43 and G45 respectively connected to (/ Q), and the output terminal is the central processing unit 50. It consists of an AND gate (G46) connected to the interrupt terminal (/ INT).

The operation of the sleep mode releasing device of the information processing device according to the embodiment of the present invention by the above configuration is as follows.

When the use of the information processing device is interrupted for a predetermined time or more by the user, the central processing unit 50 of the information processing device causes the peripheral device to operate at a low speed in order to reduce power consumption before inputting a command by the user. The system enters the sleep mode in which it is waiting for.

The central processing unit 50 that has switched to the sleep mode continuously maintains the state of the information processing device in the sleep mode until the low interrupt signal INT is input from the sleep mode canceling unit 40.

In this case, the sleep mode releasing unit 40 detects the AC / DC adapter when the high system power off signal / SPWROFF is input from the system state detecting unit 10 and the refresh request signal REFREQ is at the rising edge. When the adapter connection signal ADPIN input from the unit 10 is changed before the next rising edge of the refresh request signal REREFQ, the low interrupt signal / INT is output to the CPU 50. .

The system power off signal / SPWROFF, the refresh request signal REFREQ, and the adapter connection signal ADPIN are as follows.

System power off (/ SPEROFF): Signal that goes low when the power supply to the information processing system is interrupted. Active low

Refresh request signal (REFREQ): A signal generated to refresh DRAM (Direct Random Access Memory), which is system memory, and active high

Adapter connection signal (adaptor in, ADPIN): A signal that goes low when the AC / DC adapter is connected to the information processing device.

Therefore, when there is a change in the connection of the AD / DC adapter while the system power is being supplied, an interrupt signal (/ INT) for canceling the sleep mode from the sleep mode canceling unit 40 to the CPU 50 is provided. Is output.

In addition, the sleep mode canceling unit 40 has the liquid crystal display opening / closing signal / LIDCLOSE input from the system state detecting unit 20 when the refresh request signal REFREQ is at the rising edge, and the refresh request signal REFREQ is high. When the low state liquid crystal display opening / closing signal (/ LIDCLOSE) is input from the system state detection unit 20 before the next rising edge of), the low state interrupt signal (/ INT) is output to the central processing unit 50. .

The liquid crystal display opening / closing signal / LIDCLOSE is defined as follows.

Liquid crystal display open / close signal (LCD close, / LIDCLOSE): Signal that goes low when the liquid crystal display panel is closed and opened, active low

Therefore, when the liquid crystal display panel is closed and opened, an interrupt signal / INT for outputting the sleep mode is output from the sleep mode canceling unit 40 to the central processing unit 50.

In addition, the sleep mode canceling unit 40 may include a power-off signal (/ PWROFF) and a system access signal input from the system state detecting unit 20 and the system access detecting unit 30 when the refresh request signal REFREQ is at the rising edge. When (SYSACC) is high or low, respectively, a low power-off signal (/ PWROFF) is input from the system state detection unit 20 before the next rising edge of the refresh request signal REFREQ and system access. When the system access signal SYSACC in the high state is input from the detector 30, the interrupt signal / INT in the low state is output to the CPU 50.

The power off signal / PWROFF and the system access signal SYSACC are defined as follows.

Power off signal (LCD panel power off, / PWROFF): A signal that goes low when the supply of power to the LCD panel is cut off.

System access signal (SYSACC): A signal that is turned high when the peripherals of an information processor are used.

Therefore, when the peripheral device of the information processing device is used in a state in which the power supplied to the liquid crystal display panel is cut off, an interrupt signal for releasing the sleep mode from the sleep mode canceling unit 40 to the central processing unit 50 (/ INT) is output.

Unlike the above cases, when the power state good signal PWRGOOD is in the low state, all of the first to third D flip-flops of the sleep mode canceling unit 40 are cleared.

As described above, the present invention, in the embodiment, generates an interrupt signal for releasing the sleep mode without using the microcontroller, thereby making it easy to design the product and having the effect of reducing the cost of the product. It is possible to provide a device for releasing the sleep mode of the device. This effect of the invention can be used in the field of information processing equipment.

Claims (2)

An AC / DC adapter detector 10 for detecting whether an AC / DC adapter is connected to the system; A system state detecting unit 20 for detecting whether power supply to the system is cut off or power supply to the liquid crystal display panel is closed or the liquid crystal display panel is closed; A system access detection unit 30 for detecting whether data is input or output from a peripheral device of the information processing device; By combining the signals input from the AC / DC adapter detector 10, the system status detector 20, and the system access detector 30, the CPU 50 generates an interrupt signal that can be released from the sleep mode. Sleep mode canceling unit 40 and; And a central processing unit (50) which is released in the sleep mode when an interrupt signal is input from the sleep mode canceling unit (40). The sleep mode releasing unit 40 has an input terminal D connected to the adapter connection signal line ADPIN of the AC / DC adapter detector 10 and a clock terminal to the refresh request signal line REFREQ. A first D-type flip-flop DF1 connected to the power supply state positive signal line PWRGOOD and a clear terminal CLR connected thereto; Exclusive OR gate (G41) having an input terminal connected to the adapter connection output signal line (ADPIN) of the AC / DC adapter detector 10 and the inverted output terminal (/ Q) of the first D-type flip-flop (DF1), respectively. ; A first inverter I41 connected to an input terminal of the system power off signal line SPWROFF of the system state detection unit 20; An OR gate G42 connected to an input terminal of an exclusive OR gate and an output terminal of the first inverter I41, respectively; A second inverter (I42) connected to an input terminal of a liquid crystal display open / close signal line (/ LIDC LOSE) of the system state detection unit 20; The second D-type flip connected with the input terminal D connected to the output terminal of the second inverter I42, the clock terminal connected to the refresh request signal line REFREQ, and the clear terminal CLR connected to the power state positive signal line PWRGOOD. Flop DF2 and; A NAND gate G43 having an input terminal connected to an output terminal of the second inverter I42 and an inverted output terminal / Q of the second D-type flip-flop DF2, respectively; A third inverter I43 connected to an input terminal of the power-off signal line / PWROFF of the system state detection unit 20; An AND gate G44 connected to an output terminal of the third inverter I43 and a system access signal line SYSACC of the system access detector 30, respectively; A third D-type flip-flop having an input terminal D connected to the output terminal of the AND gate G44, a clock terminal connected to the refresh request signal line REREFQ, and a clear terminal CLR connected to the power state positive signal line PWRGOOD. (DF3) and; A NAND gate G45 having an input terminal connected to an output terminal of the AND gate G44 and an inverting output terminal / Q of the third D flip-flop DF3, respectively; An input terminal is connected to the output terminals of the OR gate G42 and the NAND gates G43 and G45, respectively, and the output terminal is composed of an AND gate G46 connected to an interrupt terminal (/ INT) of the CPU 50. A sleep mode releasing device for an information processing device.