JPH11327706A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform efficient power control and communication control among divided circuit blocks by dividing an electronic circuit into the plural circuit blocks and supplying an electric power source to the circuit blocks needed for operation in the system modes when various system modes are set. SOLUTION: Electronic circuits needed to realize functions, etc., in various system modes are divided into plural circuit blocks in circuit units which are necessary and unnecessary at the same time when the various system modes are switched. Different electric power sources capable of controlling the ON and OFF individually for the every divided circuit blocks are supplied and when the various system modes are set, the electric power is supplied to the circuit blocks needed for the operation in the system modes. In this processor, a power supply control part 29 converts the source voltage obtained by the power source 32 consisting of an AC adapter, a dry battery or the like connected to the power supply control part 29 to voltage levels needed for the every blocks and supplies it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus in which an electronic circuit for realizing various functions is divided into a plurality of blocks.

[0002]

2. Description of the Related Art In a portable notebook personal computer or the like which can be operated by a battery, the power consumption of an electronic circuit is increased in order to extend the operation time by a battery, or the clock or operation mode of a CPU is switched according to the use state of a user. To avoid wasting power.

[0003]

However, power is efficiently supplied to necessary electronic circuits according to various use states, and efficient data communication is performed between divided circuit blocks in a low power consumption state. I couldn't say.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus having various system modes in which necessary functions or performances are restricted in accordance with a use state. It is to perform good power supply control and communication control.

[0005]

Means of the present invention are as follows. An information processing apparatus having various system modes in which necessary functions or performances are limited according to a use state, and an electronic circuit necessary to realize the functions or performances in the various system modes is provided in the various system modes. Power supply dividing / supplying means for dividing a plurality of circuit blocks into a plurality of circuit blocks which are required / unnecessary at the same time in switching, and supplying different powers which can be individually turned on / off controlled for each of the divided circuit blocks; When the system mode is set, power supply selecting and supplying means for supplying power to circuit blocks required for operation in the system mode is provided.

[0006] The means of the invention of claim 2 is as follows.
An information processing apparatus having various operation modes for realizing necessary functions or performances in accordance with a use state, wherein an electronic circuit necessary for realizing the functions or performances in the various operation modes includes an electronic circuit for the various operation modes. A plurality of circuit blocks divided into circuit units that are required / unnecessary at the time of switching, and serial signals capable of transmitting data between the divided circuit blocks even in a low power consumption state in which the operation of the main CPU is limited. A communication unit connected by a line for transmitting and receiving data between the blocks without the intervention of a main CPU; and an operation mode setting unit for setting an operation mode of each circuit block by a transmission command from the communication unit. An operation state checking means for checking an operation state between circuit blocks based on status information from the communication means. When, characterized by comprising a.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an external view showing a system configuration of a data processing device. The data processing device includes a personal computer 1 as a central device thereof.

The personal computer 1 is used, for example, as a portable book-type personal computer. The personal computer 1 has a keyboard 2 and a liquid crystal display unit 3 in a main body case, and a memory card mounting unit 4 on the right side of the keyboard 2. .

On the outer peripheral side of the main body case of the personal computer 1, connection terminals for a plurality of peripheral devices are provided. For example, an extended disk driver 5, a printer 6, an electronic notebook (another computer equipped with RS232C) 7 and the stationary extension unit 8 are connected. The expansion unit 8 further includes an expansion disk mounting section 9.

FIG. 2 is a block diagram showing the overall configuration of a main electronic circuit in the data processing apparatus. The main electronic circuit is composed of three chips A, B, and C. Execution of a program corresponding to the central function, arithmetic control processing, and the like are performed.

The chip B performs interface processing with various input / output devices and peripheral devices, and manages system states such as a power supply state, an input / output mode, and an operating frequency. In the chip C, a display control process for displaying the program execution information, the system management information, and the like on the liquid crystal display unit 3 is performed.

The chip A includes a CPU (Central Processing Unit) 11, a DMAC (Direct Memory Access Controller) 12, a ROM 13, a RAM 14, a command storage control unit 15, and a serial data interface 1.
6, interrupt control unit 17, RAM disk control unit 18, sleep control unit 19, refresh control unit 20,
A clock generation control unit 21 and a bus control unit 22;
They are connected by a system bus 23.

The CPU 11 executes a program stored in advance in the ROM 13 or a program input from the outside in accordance with a system program read from the ROM 13. Necessary data during execution is input and output.

The command storage control unit 15 stores and retains the system command data before the transition to the suspend state due to the power-off when setting the resume mode for returning to the system state immediately before the power-off when the power is turned on. The command data stored and held by the command storage control unit 15 is read out and returned to the system state immediately before the power is turned off in response to the suspending state release processing accompanying the power on.

Here, the command data stored and held at the time of the transition to the suspend state is created and held at the same time as the command data, and it is determined whether the command data coincides with the checksum data based on the read command data at the time of releasing the suspended state. Done.

The serial data interface 16
The serial data interface 16 performs input / output processing of serial data between the chip B and the chip C. The serial data interface 16 receives, for example, clock frequency setting data and resume mode data supplied from the chip B via the chip C. Serial data indicating a system state such as setting data is input, and response data or the like is output to the chip B.

The interrupt control section 17 causes the CPU 11 to perform an interrupt process in accordance with a predetermined priority according to various input / output interrupt signals.

The RAM disk control unit 18 performs data access to the RAM disk 18a connected to the RAM disk control unit 18.
The M disk 18a is composed of a serial memory and is handled in the same manner as the access processing for a floppy disk.

The sleep control unit 19 causes the CPU 11 to shift to the HALT state when a predetermined time has elapsed in the unprocessed state during operation when the sleep mode is set. Is determined according to the use state of the system bus 23.

The refresh control unit 20 performs refresh control of memory data for a DRAM provided as a part of the RAM 14. In this refresh method, two types of clock signals are input from the same input pin in a time-division manner. CAS (column address strobe) before
The RAS (row address strobe) method is used.

Here, the refresh clock signal for the DRAM is supplied to the chip A during normal operation.
It is created on the basis of the system clock φSYS generated in the memory, and based on the refresh clock φREFR supplied from the chip B in the suspend state when the resume mode is set.

The clock generation control section 21 generates an operation clock in the CPU 11 based on the clock frequency setting data input through the serial data interface 16.
Is selectively set to either 5 MHz or 10 MHz.

The bus control unit 22 selectively controls connection and disconnection of the system bus 23 between the above-described chips and between blocks within the chip based on the operation control of the CPU 11. The information is given to the sleep control unit 19 as a determination factor of an unprocessed state during system operation.

On the other hand, the chip B includes a key interface 24, an RS232C interface 25, a printer interface 26, and an FDD interface 2.
7. In addition to the serial data interface 28, a power control unit 29, a system state management unit 30, a clock generation unit 3
1 and are connected by a system bus 23. The keyboard 2 is connected to the key interface 24, the electronic organizer 7 is connected to the RS232C interface 25, for example, the printer 6 is connected to the printer interface 26, and the FDD
The extended disk driver 5 and the like are connected to the interface 27, and each of them is connected to the CP via the system bus 23.
Input / output control is performed with U11.

The serial data interface 28
The serial data input / output process is performed between the chip C and the chip A. In the serial data interface 28, for example, display state setting data is given to the chip C, and clock frequency setting data and resume mode are set. Setting data etc. from chip C to chip A
Given to. Then, response data of various system states is returned to the serial data interface 28 of the chip B via the chip A.

The power supply control unit 29 includes a power supply 3 such as an AC adapter or a dry battery connected to the power supply control unit 29.
The power supply voltage obtained by the above-described chip B is converted into a voltage level required for each block and supplied.
For some blocks above, the system management operating voltage V
The SM is supplied, the system operating voltage VSYS is supplied to each block on the chip A, the memory backup voltage VMEM is supplied to a memory block requiring a backup, and each block on the chip C is further supplied. And the display voltage VDISP is supplied to the liquid crystal display unit 3.

The system state management unit 30 is constituted by a microcomputer, and includes a power supply state, a clock frequency setting state, a resume mode and a sleep mode setting state, a display mode setting state, a key input mode setting state, and a disk memory setting state. Each system state of the personal computer 1, such as an access state and a current time, is managed. The setting data of each system state is sent to the chip C or the chip A through the serial data interface 28.

The clock generator 31 includes an operation clock φSM for system state management on the chip B and a refresh clock φREFR for supplying to the refresh controller 20 of the chip A in the suspend state when the resume mode is set. Together with
The clock operation of the current time and the timer operation are performed. The clock data of the current time in the clock generation unit 20 is always given to the system state management unit 30.

On the other hand, in the chip C, in addition to the serial data interface 33 and the liquid crystal display interface 34, a system management display control unit 35, a system status display control unit 36, and a display control unit 37 are respectively provided via the system bus 23. Connected, LCD display interface 3
4 is connected to the liquid crystal display unit 3, and a system bus 23 of the chip C is connected to a V (Video) -R
AM 38 is connected.

The system management display control unit 35 is used to select and set various system states such as a clock frequency, a resume mode, a sleep mode, a display mode, and a current time managed by the system state management unit 30 on the chip B. A screen display control and a screen display control for a power remaining amount warning are performed. The system state selection setting screen and the power remaining amount warning warning screen include various states input through the serial data interface 33. A window screen is created to be developed at the center of the display area in accordance with the management data, and is displayed on the liquid crystal display unit 3 through the liquid crystal display interface 34 in a window.

In this case, the system state selection setting screen is appropriately displayed based on control data given as serial data by a key input operation on the keyboard 2.

The system status display controller 36 controls the clock frequency, the resume mode, the sleep mode, the display mode, the current time, etc. managed by the system status manager 30 on the chip B, as well as the key input mode and the disk memory. A screen display control indicating the setting state of various systems such as an operation state is performed.
In accordance with various state setting data input through the interface, it is created so as to be strip-shaped along the upper and lower ends of the display area, and is always displayed on the liquid crystal display unit 3 through the liquid crystal display interface 34 in a window.

Here, the system state management unit 3 of the chip B
Display control data, selection setting data, and the like relating to various system status data managed by 0 are all input / output as serial data through the serial data interface 28 → 33 → 16 on each chip.

FIG. 3 shows the data structure of serial data input / output between the chips of the data processing apparatus. The serial data is composed of a command such as a display control command or a switching command of a system state and a command such as this command. The corresponding data, for example, the data indicating the setting contents of the system state and the like are alternately transferred.

FIG. 4 shows each chip A,
6 is a flowchart showing input / output processing in the serial data interfaces 16, 28, and 33 provided on B and C, that is, when inputting serial data of one segment, first, it is determined whether or not the serial data is a command for a block on its own chip; (Steps S1, S
2).

If it is determined in step S2 that the input serial data is command data for the block on the own chip, the command data is fetched, and The control signal is output (steps S3, S
4).

On the other hand, "N" in step S2,
That is, when it is determined that the input serial data is not command data for the block on the own chip, the serial data is transferred and output as it is to the serial data interface provided on the next chip on the serial bus ( Step S4).

FIG. 5 is a block diagram showing the configuration of an electronic circuit excluding the resume function unit in the data processing apparatus.
The key interface 24 includes a microcomputer 39 and a memory switch storage unit 40, and the key interface 24 includes a microcomputer 39 and a key input port 41.

The liquid crystal display interface 34 on the chip C is composed of a liquid crystal display control unit 42, a step / inversion control unit 43, and a display buffer 44.

Here, various system status information stored and managed by the system status management unit 30 is stored in the CPU 1.
1, the setting information of the operating clock frequency φSYS “5 /
10 (MHz) ", resume mode, sleep mode,
Setting information “ON / OFF” for each reverse display mode,
Current time setting information "hour / minute", display gradation setting information "8/2 (gradation)", access baud rate setting information with computer equipped with RS232C "1200/300 (baud)", number of printer connection pins Setting information "16/24
(Pin) ”, setting information“ 7/8 (bit) ”of the access data bit length with the RS232C-equipped device,
Parity check setting information "ON
/ OFF ", the operation status information of the memory disk" FDD /
RAM ", key input mode setting information" CAPS / NU "
M ”and the like, among which the setting contents of the access baud rate, access data bit length, parity check, and the number of printer pins related to the RS232C are set in the memory switch storage unit 40. on the other hand,
Power supply state information obtained through the power supply control unit 29 is determined by the microcomputer 39.

FIG. 6 shows a display state of various system state information managed by the system state management section 30 of the data processing apparatus on the liquid crystal display section 3. FIG. 6A shows a display screen of various system states. FIG. 6B is a diagram showing a selection setting screen for various system status information, and FIG. 7C is a diagram showing a power remaining amount warning screen.

That is, as shown in FIG. 6A, the setting information "CAPS / NUM" of the key input mode, the operation state information "FDD / RAM" of the memory disk, and the setting information "RESU" of each of the resume mode and the sleep mode.
"ME", "SLEEP", setting information "5/10 (MHz)" of the operation clock φSYS, and setting information "hour / minute" of the current time are all set as current system state information.
Through the serial data interfaces 28 and 33 and the system status display controller 36 from the microcomputer 39,
The setting information “CAPS / NUM” of the key input mode is always displayed on the liquid crystal display unit 3.
Is turned on in response to depression of the "CAPS" key 2d or the "NUM" key 2e.

Further, the operating state information "F
DD / RAM ”is the FDD interface 27 or R
“FDD” or “RAM” is turned on in response to a disk access through the AM disk control unit 18. In the setting information of the resume mode and the sleep mode, “RESUME” and “SLEEP” are turned on in response to the selection setting “ON / OFF” of the resume mode or the sleep mode by a key input operation.
Also, the setting information of the operation clock φSYS “5/10 (MH
“z)” is turned on with “5 MHz” or “10 MHz” corresponding to the clock frequency selection setting by key input operation. Further, the current time setting information is updated and displayed in the clock circuit of the clock generation unit 31 in correspondence with the current time "hour / minute" measured every second or every tenth of a second.

Here, the "SYS" key 2 on the keyboard 2 is used to select and set the various system states.
When a is operated, the control signal is transferred from the microcomputer 39 to the system management display control unit 35 through the serial data interfaces 28 and 33. Then, in the system management display control unit 35, a selection setting screen for various system states is created based on the various system state setting information, and displayed on the liquid crystal display unit 3 as shown in FIG.

In this case, the selection setting operation of various system states or the scroll operation of the selection setting screen is performed by the “cursor” key 2 b and the “return” key on the keyboard 2.
This control is performed using the key 2c.
From the microcomputer 39 to the serial data interface 28
Is output via.

That is, when, for example, the clock frequency φSYS is set to “10 MHz” in the selection setting screen of various system states in FIG. 6B, the clock on the screen created by the system management display control unit 35 is displayed. The setting information of the frequency φSYS is displayed as a cursor as “10 MHz”, the clock control signal is transferred to the clock generation control unit 21 on the chip A, the operation clock φSYS for the CPU 11 is switched to 10 MHz, and the chip C Display data corresponding to the clock setting is transferred to the upper system status display controller 36, and “10 MHz” is lit and displayed at the lower end of the liquid crystal display unit 3.

When, for example, the resume mode is selected to "ON" on the selection screen for various system states in FIG. 6B, a flag is set in a system state register inside the microcomputer 39, and
The display data associated with the setting of the resume mode is transferred to the system status display control unit 36 on the chip C, and “RESUME” is lit on the lower end of the liquid crystal display unit 3.

Further, when, for example, the sleep mode is selected to be “ON” on the selection setting screen of various system states in FIG. 6B, a flag is set in a system state register inside the microcomputer 39 and
The display data accompanying the setting of the sleep mode is chip C
The data is transferred to the upper system status display controller 36, and "SLEEP" is lit on the lower end of the liquid crystal display 3.

Further, in the selection setting screen for various system states in FIG.
When the “tone” is selected and the inverted display mode is selected as “OFF”, the tone setting information and the inverted setting information on the screen created by the system management display unit 35 are “two-step” and “O”, respectively.
A cursor is displayed as "FF", and the tone and inversion control signal are transferred to the tone and inversion control unit 43, and the display tone is set to two-tone and the inverted display mode is switched to OFF.

When time adjustment or timer time adjustment is performed in a state where time information is displayed by scrolling the selection setting screen for various system states in FIG. 6B, a clock is generated through the microcomputer 39. Part 31
The clock circuit and the timer circuit are controlled to set the time and the timer time, and the time setting data is transferred to the system status display control unit 36 on the chip C, and the set time is displayed at the lower end of the liquid crystal display unit 3. Is displayed.

On the other hand, when the microcomputer 39 determines through the power supply control unit 29 that the remaining power supply has decreased to a predetermined amount or less, a power supply warning control signal is transferred to the system management display control unit 35 in the chip C, and the power supply A message screen for a low remaining amount warning is created, and FIG.
As shown by, a window is displayed on the liquid crystal display unit 3.

That is, in the data processing device including the plurality of chips A, B, and C, a large number of blocks mounted on each of the chips A, B, and C are connected via the system bus 23 including a plurality of signal lines. At the same time, commands and data related to various system states that are not related to the processing of the CPU 11, that is, the processing speed does not need to be increased, are serially transferred via the serial data interfaces 16, 28, and 33. A, B,
The number of input / output terminals in C can be minimized.

FIG. 7 is a block diagram showing the configuration of an electronic circuit related to the sleep and resume function unit in the data processing apparatus. The sleep function unit is mainly composed of the CPU 11 and the sleep control unit 19, and the resume function unit is The microcomputer 39, the command determination unit 45, and the SRA
The command storage control unit 15 including M46 is mainly configured.

When the sleep mode is set for the CPU 11, the sleep control section 19 monitors a bus control signal from the CPU 11 to the bus controller 22, and if the number of times the bus has been used is less than the expected value within a predetermined time, the sleep control section 19 sets the signal to C.
A “sleep-in” control that puts the PU 11 into a sleep state, and a “sleep-out” control that releases the sleep state of the CPU 11 when an input interrupt from the keyboard 2 or another connected device occurs. And CP
In U11, a JOBEND signal is output to the microcomputer 39 on the chip B in accordance with the "sleep-in".

The command judging section 45 detects the CPU 11 during the normal operation with the resume mode set.
Address and data output from the DMAC
12 or a command to the GDC (graphic display controller) 48.
If it is a command, it is uniquely determined by a gate array or the like.
A RAM address is created, that is, the CPU 11
Command data for the DMAC 12 or the GDC 48 output from the RAM 46 are sequentially written and stored in the SRAM 46.

FIG. 8 is a timing chart showing a command writing operation when the resume mode is set in the command judging section 45 of the data processing apparatus. The address data from the CPU 11 corresponds to the 4th of the CPU operation clock φSYS.
The data changes every cycle, and the data is output one cycle of the operation clock φSYS after the change of the address data. When writing I / O for two cycles of the operation clock φSYS from the data output, the command determination unit If it is determined at 45 that the command data is for the DMAC 12 or the GDC 48, the command data from the CPU 11 is written to the SRAM 46.

The command data written in the SRAM 46 is changed to a power-off due to a power switch or IC card insertion / removal, or to a suspend state due to power-off performed when the “sleep-in” state continues for a predetermined time or more. At the time of transition, the system operation state is stored and held just before the power is turned off, whereby the display power supply VDISP in the power supply control unit 29 is switched off → the refresh clock of the DRAM 47 is switched in the refresh control unit 20 → the clock generation control unit The stop of the system operation clock φSYS in 21 → the shutoff of the system power supply VSYS in the power supply control unit 29 is performed under the control of the microcomputer 39 of the chip B.

In this case, when shifting to the suspend state, the CPU 11 causes the DRAM 47 and the VRAM 3
8 is created and written into the SRAM 46 together with the command data.

Then, at the time of the transition from the suspension state release to the ON state of the power switch, the power supply control section 29 turns on the system power supply VSYS → the clock generation control section 21 oscillates the system operation clock φSYS → the refresh control section 20 refreshes the DRAM 47. Clock switching → display power supply VDI in power supply control unit 29
The input of the SP is performed under the control of the microcomputer 39 of the chip B, whereby the command data stored and held in the SRAM 46 is read out in a predetermined order and set in the DMAC 12 and the GDC 48, respectively.
The system is returned to the system operation state immediately before the power is turned off.

In this case, DRA is executed again by the CPU 11.
The checksum data of the M47 and the VRAM 38 is created and compared with the checksum data stored in the SRAM 46 in advance. When the checksum data does not match, the suspension state release processing is stopped.

That is, the CPU 11 and the CPU 1
DMAC1 that operates based on command data from
In the data processing apparatus provided with the GDC 48 and the GDC 48, when the resume mode is set, the command data output from the CPU 11 to the DMAC 12 and the GDC 48 is detected by the command determination unit 45, and a predetermined SRAM corresponding to the command data is detected. In addition to creating an address, the command data detected by the command determination unit 45 based on the SRAM address is stored in the SRAM 46.
Therefore, even when the supply of the clock signal to the DMAC 12 and the GDC 48 constituted by the dynamic circuit is stopped in accordance with the transition to the suspend state due to the power-off, the system operation state immediately before the power-off is changed. The SRAM 46 can be securely held in the SRAM 46, and the DMAC 12 and the like do not need to be constituted by an expensive CMOS circuit or the like which requires power supply. FIG. 9 is a block diagram showing the internal configuration of the CPU 11 and the sleep control unit 19 which are responsible for the sleep function unit of the data processing device. The sleep control unit 19 includes a bus use clock generation circuit 49, a bus use counter 50,
And a count latch circuit 51.
The CPU 11 includes, in addition to the main control unit 52, a coincidence determination unit 53 that determines whether the number of times of bus use has dropped below an expected value set in advance at the time of I / O reading at predetermined time intervals.

FIG. 10 shows the CP in the data processing apparatus.
It shows the relationship between the bus control signal output from the main control unit 52 of U11 to the bus control unit 22 and the operation content. The bus control signal has a 3-bit configuration of BS0, BS1, and BS2, and is "000". Interrupt approval, "100" for I
/ O read, I / O write at "010", halt at "110", instruction read at "001", memory read at "101", memory write at "011", and non-read at "111". It is controlled to the operating state.

The bus-use clock generation circuit 49 has a C
Bus control signal BS from PU 11 to bus control unit 22
0, BS1 and BS2 are input and a bus use clock is generated each time a bus operation is performed. The clock signal from the bus use clock generation circuit 49 is output to a bus use number counter 50.

The bus usage counter 50 is a CPU
The bus usage count within the predetermined time counted by the bus usage counter 50 is performed in accordance with an I / O read signal from the CPU 11. Then, the data is latched by the count latch circuit 51 and transferred to the coincidence determination unit 53 through the main control unit 52 of the CPU 11.

Here, in the coincidence determination section 53, if the preset expected value and the number of times of use of the bus within the predetermined time are equal to or less than the expected value, that is, if the number of times of bus use is equal to the expected value If it has fallen to a lower level, the coincidence determination signal is output to the main controller 52, a JOBEND signal indicating "sleep-in" is output to the microcomputer 39 on the chip B, and the CPU 11 enters the HALT state. Is set.

In this case, the coincidence determination unit 5 of the CPU 11
The expected value set in advance in 3 is taken into consideration because the bus is used and a bus use clock is generated when determining sleep conditions, for example, when taking in count data in the bus use counter 50. Thus, the expected value is set to at least “1” or more.

FIG. 11 is a flow chart showing a sleep process when the data processing apparatus is set to the sleep mode. The bus use counter is controlled in accordance with an I / O read signal output from the main control unit 52 of the CPU 11 at predetermined time intervals. When the I / O read signal is output again after a predetermined time has elapsed after the reset of the CPU 50, the bus use count data counted by the bus use counter 50 is latched by the count latch circuit 51, and the main CPU 11 The data is read by the control unit 52 and transferred to the coincidence determination unit 53 (steps A1 to A4).

Here, when it is determined that the number of times of use of the bus within the predetermined time is equal to or less than a predetermined expected value, that is, C
If it is determined that the new system operations based on the PU 11 are almost equal, a match determination signal from the match determination unit 53 is output to the main control unit 52 (step A5).

Then, a JOBEND signal “1” indicating “sleep-in” is output from the main control unit 52 to the microcomputer 39 on the chip B, and the CPU 11 is set to a halt state to suspend the control operation. (Step A6).

In the sleep state due to the halt of the CPU 11, if an interrupt occurs in response to a key input operation on the keyboard 2 or an input operation from another connected device such as an RS232C-equipped device or a mouse, an interrupt occurs. Through the control unit 17, the CP
A sleep-out signal is output to the main control unit 52 of U11 (step A7).

Then, the JOBEND signal output from the main control unit 52 to the microcomputer 39 on the chip B is reset to “0”, the halt state of the CPU 11 is released, and the control operation is started. You. (Step A8).

That is, in a data processing device in which a plurality of blocks are connected to the CPU 11 via the system bus 23, the number of bus uses is counted by the bus use counter 50, and the count data is counted at predetermined time intervals. CPU1 through the latch circuit 51
When the coincidence determination unit 53 determines that the number of times the bus has been used within a predetermined time period is equal to or less than a preset expected value, the operation of the CPU 11 is suspended and the HALT (HALT) is stopped. ) Since the state is set to the state, the state where there is no new control processing in the CPU 11 can be reliably determined.

Thus, for example, during execution of an application program that requires a long time, the CPU 11 in the actual operating state can be suddenly turned off without inadvertently setting the sleep state due to no key input for a certain period of time.
Transition to the FF state or the HALT state can be prevented.

FIG. 12 is a block diagram showing the internal structure of the microcomputer 39 which controls the resume control in the data processing apparatus. The control unit 54 of the microcomputer 39 includes not only the keyboard 2 but also an input to the CPU 11 of the chip A. An output port 55, a system status register 5 indicating the presence or absence of a sleep mode or a resume mode and its function status
6, a sleep counter 57 for counting the duration of the sleep state of the CPU 11, a remaining amount determining unit 58 for determining that the remaining power is higher than a predetermined amount, a power switch 59 for turning on / off the power, and a serial data interface. 28 are connected.

When the CPU 11 shifts to the sleep state or the suspend state, the input / output port 55
JOBEND flag area 55 to which signal "1" is applied
a, a SET flag area 55b to which a SET signal “1” is given in accordance with the normal recovery of the CPU 11 when the suspend mode is released when the resume mode is set, and for an abnormal return of the CPU 11 when the suspend mode is released when the resume mode is set Accordingly, an error signal “1” is provided and an error flag area 55c is provided.

The system status register 56 has a sleep mode register 56a in which a flag "1" is set when a sleep mode is set, a resume mode register 56b in which a flag "1" is set when a resume mode is set, and a sleep mode. Sleep register 56 in which flag "1" is set at the time of transition to the state
c, there is provided a suspend register 56d in which a flag "1" is set at the time of transition to the suspend state.

The sleep counter 57 is reset when the flag "1" is set in the sleep register 56c of the system state register 56, and simultaneously counts up in accordance with the system state management operation clock φSM. From this sleep counter 57,
The carry signal is output to control unit 54 corresponding to the preset sleep time.

FIG. 13 is a flow chart showing the resume processing when the resume mode of the data processing apparatus is set.
When U11 shifts to the sleep state, the input / output port 5
5, when the JOBEND signal "1" is given to the JOBEND flag area 55a, the flag "1" is set in the sleep register 56c of the system status register 56, the sleep counter 57 is reset, and at the same time, the sleep corresponding to the clock φSM is performed. A time counting operation is started (steps B1 to B3).

Here, as Case 1, when the sleep state of the CPU 11 elapses a preset sleep time and the counter carry from the sleep counter 57 is output to the control unit 54, the CPU 11 shifts to the suspend state. First, the remaining amount determining unit 58 determines whether the remaining amount of power is higher than a predetermined amount (steps B4 and B5).

In case 2, step B 1
When the power switch 59 is turned off in the state of normal processing such as key scan to which the JOBEND signal “1” is not supplied, first, the remaining amount determination is performed in order to shift to the suspend state as described above. The unit 58 determines whether the remaining power is higher than a predetermined amount (steps B1 → B6, B7 → B5).

Further, as Case 3, the above Step B
4, that is, even if the sleep state of the CPU 11 does not elapse the preset sleep time, if the power switch 59 is turned off as it is, the remaining state is first set to shift to the suspend state as described above. The amount determination unit 58 determines whether the remaining power level is higher than a predetermined amount (steps B4 → B8, B9 → B).
5).

On the other hand, in step B4, "N
o ”, that is, if the sleep state of the CPU 11 does not exceed the preset sleep time and a key operation signal from the keyboard 2 is input to the control unit 54 before the power switch 59 is turned off. , A key input interrupt signal is output to the interrupt control unit 17 on the chip A, a sleep-out signal is supplied to the CPU 11, and the sleep state is released (steps B4 → B8-B12).

During the counting operation of the sleep counter 57 in the sleep state of the CPU 11, the processing of steps B3, B4 → B8 to B13 is repeatedly executed. Then, when the remaining power is checked to shift to the suspend state through the processing of Case 1, Case 2, or Case 3, "N" is set in Step B5.
o ", that is, when the remaining amount determining unit 58 determines that the power remaining amount has decreased to a predetermined amount or less, the control unit 54 transmits serial data indicating that transition to the suspend state is impossible via the serial data interface 28 to the chip C. The message is transferred to the system management display control unit 35, and a process of displaying a resume function cancel message due to insufficient power is performed (steps B5 to B14).

FIG. 14 is a diagram showing a display state of the resume function cancel message on the liquid crystal display unit 3 when the resume mode of the data processing device is set. FIG. 14A shows the resume function cancellation due to the power supply shortage. FIG. 11B is a diagram showing a display state of a message, and FIG. 11B is a diagram showing a display state of a resume function cancel message accompanying a CPU error when the suspend state is released.

Then, as shown in FIG.
When the return key 2c on the keyboard 2 is operated in a state in which the resume function cancellation message accompanying the power supply shortage is displayed, the control unit 54 causes the power control unit 2 to operate.
A control signal for turning off the power is output to the power supply 9, and the power supply control unit 29 shuts off all the power supply of the system operating voltage VSYS, the memory backup voltage VMEM, and the display voltage VDISP (steps B15 and B16).

On the other hand, in step B5, "Ye
s ”, that is, when the remaining power determination unit 58 determines that the remaining power is maintained at a state higher than the predetermined amount, the control unit 54 issues a resume-in, that is, a serial signal indicating a suspend-in request. The data is transferred to the interrupt controller 17 on the chip A via each serial data interface 28 → 33 → 16, and a suspend-in control signal “SUS IN” is supplied to the CPU 11 (steps B5 → B17).

FIG. 15 shows the CPU 11 of the data processing apparatus.
7 is a flowchart showing the suspend-in control process in FIG. 6. When the suspend-in control signal “SUS IN” is supplied to the CPU 11 through the interrupt control unit 17, the CPU 11
It is determined whether or not the display data is being drawn in the VRAM 38 through (steps C1 and C2).

In step C2, "Yes", that is, when the GDC drawing is being performed, the drawing processing state is maintained. When the GDC drawing processing is completed, the drawing address data is changed to the display address information immediately before the transition to the suspend state. Is stored in the SRAM 46 (steps C2 and C3).

Here, the CPU 11 creates checksum data of the data stored in the DRAM 47 and the VRAM 38, and the checksum data is stored in the SRAM 11.
46 is stored and held (steps C4 and C5).

Then, the JOBEND flag area 55a in the input / output port 55 on the chip B from the CPU 11
In response to the JOBEND signal "1"
Is output (step C6).

Thus, the JOBEN of the input / output port 55
When a JOBEND signal “1” is given to the D flag area 55 a in response to the suspend-in of the CPU 11, first, the display power supply VDISP is cut off from the control unit 54 through the power supply control unit 29 (steps B 18 and B 19).

Next, data indicating a refresh switching request is transferred from the control unit 54 to the refresh control unit 20 on the chip A via each serial data interface 28 → 33 → 16. System clock φ from clock generation control unit 21
SYS is shut off and the refresh clock (CAS, RA
S), a refresh clock φREFR from the clock generator 31 on the chip B is used as a basic clock.
Is supplied (step B20).

Then, the data indicating the clock stop request is transferred from the control unit 54 to the clock generation control unit 21 on the chip A via each serial data interface 28 → 33 → 16. Is stopped, and the clock generation stop state is notified to the control unit 54 from the serial data interface 16 of the chip A through the serial data interface 28 of the chip B. The system power supply VSYS is cut off through the control unit 29 (steps B21 to B2).
3).

As a result, the data processing device enters a suspend state accompanying the setting of the resume mode.

In this case, in the SRAM 46 on the chip A, the command data for each of the DMAC 12 and the GDC 48 immediately before the transition to the suspend state in the CPU 11 is held in advance through the command judging section 45, and the drawing address data and the The checksum data of the DRAM 47 and the VRAM 38 is also held.

FIG. 16 is a flowchart showing the suspend-out control processing when the data processing apparatus is set in the resume mode. When the power switch 59 is turned on to start using the data processing apparatus, first, the control unit 54 The system power supply VSYS is turned on through the power supply control unit 29 (steps D1 and D2).

Next, data indicating a clock oscillation request is transferred from the control unit 54 to the clock generation control unit 21 on the chip A via each serial data interface 28 → 33 → 16. At the same time as the clock generation operation is started, the clock generation operation state is notified to the control unit 54 from the serial data interface 16 of the chip A via the serial data interface 28 of the chip B (steps D3 and D4).

Then, data indicating a refresh switching request is transferred from the control unit 54 to the refresh control unit 20 on the chip A via each serial data interface 28 → 33 → 16. , Refresh clock (CAS, RA
S), a refresh clock φREFR from the clock generator 31 on the chip B is used as a basic clock.
At the same time, the system clock φSYS is supplied from the clock generation controller 21 (step D5).

Then, the display power supply VDISP is turned on from the control unit 54 through the power supply control unit 29, and the control unit 5
4, the serial data indicating the request for suspend-out is transferred to the interrupt control unit 17 on the chip A via each serial data interface 28 → 33 → 16, and the suspend-out control signal “SU
S OUT ”is supplied (steps D6, D7).

FIG. 17 shows the CPU 11 of the data processing apparatus.
10 is a flowchart showing a suspend-out control process in the CPU 11;
Through the suspend-out control signal “SUS OU
When "T" is supplied, the CPU 11 creates checksum data of the data stored in the DRAM 47 and the VRAM 38 after the suspend state (step E).
1, E2).

The CPU 11 stores the DRAM 4 at the time of transition to the suspend state, which is stored and held in the SRAM 46 in advance.
7 and the checksum data of the data stored in the VRAM 38 are read, and it is determined whether or not the checksum data matches the new checksum data created in step E2 (steps E3 and E4).

In this step E4, "No", that is, when the DRAM 47, VR
The checksum data of the AM 38 does not match the checksum data of the DRAM 47 and the VRAM 38 when the suspend state is released, and the DRAM 47 and the VRAM 38 do not match.
When it is determined that an abnormality has occurred in the stored data in the
11 to the error flag area 55c of the input / output port 55
, An error signal "1" accompanying the suspend-out abnormality is output (steps E4 and E5).

Then, in the microcomputer 39, the serial data indicating that the suspension state cannot be restored (canceled) is transferred from the control unit 54 to the system management display control unit 35 on the chip C through the serial data interface 28, and the microcomputer 39 shown in FIG. As shown in (), display processing of a resume function cancel message due to a CPU error is executed (steps D8 → D9).

Then, as shown in FIG. 14B,
When the return key 2c on the keyboard 2 is operated in a state where the resume function cancel message accompanying the CPU error at the time of canceling the suspended state is displayed, a reset signal is output from the control unit 54 to the CPU 11,
This data processing device is initially set (initial setting) regardless of the setting of the resume function (step D1).
0, D11).

Even if the error signal "1" from the CPU 11 is not output to the microcomputer 39, the control unit 54 of the microcomputer 39 outputs the CP before the predetermined time elapses after the request data of the suspend-out is output.
If the SET signal "1" accompanying the normal recovery from U11 is not applied to the SET flag area 55b of the input / output port 55, the control unit 54 returns the suspended state (when the error signal "1" is applied). Release) The serial data indicating “impossible” is not
Then, as shown in FIG. 14B, the display process of the resume function cancel message is executed (steps D8 → D12, D13 → D9).

In this case as well, by operating the return key 2c of the keyboard 2, a reset signal is output from the control unit 54 to the CPU 11 as in the above, and the data processing apparatus operates in the initial set (regardless of the setting of the resume function). (Initial setting) (Steps D10 and D1)
1).

On the other hand, in step E4, "Ye
s ”, that is, the DRAM at the time of transition to the suspend state.
The checksum data of the DRAM 47 and the VRAM 38 at the time of releasing the suspend state match the checksum data of the DRAM 47 and the VRAM 38 when the suspend state is released.
When it is determined that the storage data in the AM 38 is normally held, the DMAC 12 and the GDC
Command data for each of the 48 devices is read,
The DMAC 12 and the GDC 48 are set in a predetermined order (steps E4 to E6).

With the return processing of the command data, the drawing address data for the GDC 48 before the transition to the suspend state, which is stored in the SRAM 46 in advance, is read and set for the GDC 48 (step E7).

Then, the CPU 11 outputs a SET signal "1" accompanying the normal recovery to the SET flag area 55b of the input / output port 55, and the data processing apparatus is returned from the suspend state accompanying the setting of the resume mode. (Step E8).

In other words, the DRAM 47 and the VRAM 38 also shift to the suspend state when the power is turned off.
In the data processing apparatus having the resume function of retaining the memory contents in the DRAM 47 and the VRAM
Checksum data based on memory data
U11, which is stored and held in the SRAM 46. When the suspend state is released upon power-on, the CPU 11 again generates checksum data based on the memory data of the DRAM 47 and the VRAM 38, and
A comparison is made with the checksum data at the time of transition to the suspend state stored in the RAM 46 in advance, and only when a match is determined, the command data for the DMAC 12 and the GDC 48 stored and held in the SRAM 46 is set. Since the system state is restored before the power is turned off, abnormal operation and display may be performed or data may be destroyed when the power supply is restarted when the memory contents are changed due to a voltage drop in the suspend state. Can be prevented from occurring beforehand.

FIG. 18 is a circuit diagram showing the internal configuration of the refresh control unit 20 in the data processing apparatus. The system clock φSYS from the clock generation control unit 21 on the chip A is supplied to the shift registers 60a and 60b by the shift clocks, respectively. Supplied as CK and chip B
The refresh clock φREFR from the clock generation unit 31 above is supplied to the frequency dividing circuit 61 and the AND gate AND
3 is provided to the second input.

A refresh switching request signal from the microcomputer 39 in response to each of the suspend-in and the suspend-out when the resume mode is set is supplied to the switching signal generator 62.

The switching signal generator 62 generates a refresh switching signal X which becomes "1" when the switching request signal accompanying the suspend-out is supplied and "0" when the switching request signal accompanying the suspend-in is supplied. The refresh switching signal X from the switching signal generator 62 is supplied to a first input of an AND gate AND1, and is also supplied to the first input of an AND gate AND2 and a first input of the AND gate AND3 via an inverter INV1. Supplied to

The frequency dividing circuit 61 generates a refresh clock φREFR from the clock generator 31 on the chip B.
A refresh timing signal ST that changes to "1" and "0" every four periods is generated. The refresh timing signal ST from the frequency dividing circuit 61 is generated by the second gate of each of the AND gates AND1 and AND2. Supplied to input.

The output signal from AND gate AND1 is
The signal is supplied to the inversion set terminal S of the flip-flop FF1, and is also supplied to the inversion reset terminal R of each of the shift registers 60a and 60b. The output signal Q from the flip-flop FF1 is supplied to the input terminal I of the shift register 60a and to the first input of the AND gate AND4 via the inverter INV2. The output signal O from the shift register 60a is supplied to the input terminal I of the shift register 60b, and is also supplied to the first input of the AND gate AND5 via the inverter INV3. Then, the output signal O of the shift register 60b is output.
Is supplied to the reset terminal R of the flip-flop FF1.

On the other hand, the output signal from the AND gate AND2 is supplied to the analog delay circuit 63,
The output signal from the inverting set terminal S of the flip-flop FF2 and the output signal from the AND gate AND3 are supplied to each reset terminal R of the flip-flop FF2 and the flip-flop FF3.

The analog delay circuit 63 delays the refresh switching signal X when the refresh switching signal X is "0", that is, when the switching request signal accompanying the suspend-in is supplied and the refresh timing signal ST becomes "1". Signal, ie, refresh timing delay signal STD
The refresh timing delay signal STD from the analog delay circuit 63 is supplied to the inverting set terminal S of the flip-flop FF3.

The inverted output signal Q from the flip-flop FF2 is supplied to the second input of the AND gate AND4, and the inverted output signal Q from the flip-flop FF3 is supplied to the second input of the AND gate AND5. Supplied.

Here, CA from AND gate AND4 is
S (column address strobe) is AND gate AND5
RAS (row address strobe) is DRAM
This signal is output as a refresh clock for 47.

FIG. 19 shows a refresh clock (CAS, CAS) in the refresh controller 20 of the data processing apparatus.
(RAS) is a timing chart showing the operation of generating
First, in a state where the switching request signal in the normal operation is supplied, when the refresh switching signal X from the switching signal generating unit 62 is “1”, both the output signals of the AND gates AND2 and AND3 are output. It becomes “0” and the flip-flop FF2 and the flip-flop FF
3 is set to "1", and each of the second gates of the AND gates AND4 and AND5 is set to "1".
Supplied to input.

When the refresh timing signal ST output from the frequency dividing circuit 61 is "1",
Since the output signal of the AND gate AND1 becomes "1" and the output signals of the flip-flop FF1 and the shift register 60a are fixed to "0", the output signal of the AND gate AND1 is fixed.
4 and the first input of the AND gate AND5 are supplied with "1", and neither refresh clock CAS nor RAS is generated.

Here, when the refresh timing signal ST output from the frequency dividing circuit 61 changes to "0", the output signal of the AND gate AND1 becomes "0" and the output signal Q of the flip-flop FF1 becomes "1". First, the refresh clock CAS is supplied from the AND gate AND4.
"0" is generated, and subsequently the output signal O of the shift register 60a becomes "1", and the refresh clock RAS "0" is generated from the AND gate AND5.

The refresh clock (CAS before RAS) in the normal operation is returned to “1” when the output signal O of the shift register 60b subsequently becomes “1” and the flip-flop FF1 is reset. .

That is, during the normal operation, the refresh clock (CAS b) is sequentially generated with the count delay of the system clock φSYS by the shift register 60 a in accordance with the change of the refresh timing signal ST from “1” to “0”.
efore RAS) is generated.

On the other hand, when the switching request signal accompanying the suspend-in is supplied and the refresh switching signal X from the switching signal generator 62 is "0", the output signal of the AND gate AND2 is divided. "1" according to the change of the refresh timing signal ST from the circuit 61
The output signal of the AND gate AND3 changes "1" and "0" according to the change of the refresh clock φREFR from the clock generator 31. At this time, since the output signal Q of the flip-flop FF1 and the output signal O of the shift register 60a are both "0", the first inputs of the AND gates AND4 and AND5 are fixed at "1". .

Then, the refresh timing signal ST
Changes from “0” to “1”, the AND gate A
Since the output signal of ND2 also changes from "0" to "1", the inverted output signal Q of the flip-flop FF2 becomes "1" and the refresh clock C from the AND gate AND4.
No AS is generated.

In this case, the refresh timing delay signal STD "1" is generated from the analog delay circuit 63, but the inverted output signal Q of the flip-flop FF3 becomes "1" and the refresh clock RAS from the AND gate AND5 is generated. Not done.

Thereafter, when the refresh timing signal ST changes from "1" to "0", the AND gate AN
When the output signal from D2 becomes "0", the inverted output signal Q from flip-flop FF2 becomes "0", and the refresh clock CAS is generated from AND gate AND4.

Then, the refresh timing delay signal STD from the analog delay circuit 63 also becomes "0", the inverted output signal Q from the flip-flop FF3 becomes "0", and the refresh clock RAS is generated from the AND gate AND5. You.

The refresh clock (CAS before RAS) associated with the suspend-in is generated by changing the refresh clock φREFR from the clock generation unit 31 from “0” to “1” and changing each flip-flop FF2
Each of the FFs 3 is reset to “1”
Is returned to.

That is, in the suspend-in state, the system clock φSYS from the clock generation control unit 21 is output.
However, the supply of the refresh clock (C) is sequentially stopped with the delay of the refresh timing delay signal STD by the analog delay circuit 63 as the refresh timing signal ST changes from "1" to "0".
AS before RAS) is generated.

That is, in the data processing device provided with the refresh control unit 20 of the DRAM 47 by the CAS before RAS system, the refresh operation is performed through the frequency dividing circuit 61 based on the clock generation unit 31 that generates a necessary low-period clock signal even in the suspended state. An analog delay circuit 63 for generating a timing signal ST and delaying the refresh timing signal ST to obtain a refresh timing delay signal STD is provided, and an AND gate A is provided in accordance with the refresh timing signal ST.
ND2, flip-flop FF2, AND gate AND
4, the refresh clock CAS is generated through the flip-flop FF3 and the AND gate AND5 in accordance with the refresh timing delay signal STD from the analog delay circuit 63. Therefore, when the resume mode is set, At the time of transition to the suspend state, even if the operation of the clock generation control unit 21 for generating the high-speed system operation clock φSYS is stopped, the DRAM
47 can be surely refreshed, and further lower power consumption can be achieved during suspend.

Therefore, according to the data processing apparatus having the above-described configuration, the data processing apparatus is provided with the resume function for retaining the memory contents in the DRAM 47 and the VRAM 38 even when shifting to the suspend state due to the power-off. At the time of transition to the state, DR
The checksum data based on the memory data of the AM 47 and the VRAM 38 is created by the CPU 11,
And the DRAM 47 and the VRAM 38 are again stored when the suspend state is released when the power is turned on.
Checksum data based on the memory data of
1 and is compared with the checksum data at the time of transition to the suspend state, which is stored in the SRAM 46 in advance, and the SR is determined only when a match is obtained.
DMAC12 and GDC previously stored and held in AM46
Since the system is configured to set the command data for 48 and restore the system state before the power is turned off, for example, when the power is restarted when the memory contents are changed due to a voltage drop or the like in the suspend state, abnormal operation and display may occur. It is possible to prevent the occurrence of troubles such as the occurrence of data corruption and the occurrence of data destruction.

[0134]

According to the first aspect of the present invention, a plurality of electronic circuits necessary for realizing functions or performances in various system modes are provided in a plurality of circuit units which are simultaneously required / unnecessary in switching the various system modes. It is divided into circuit blocks, and different power supplies that can be individually turned on / off are supplied to each of the divided circuit blocks. When various system modes are set, operation is required for operation in the system mode. Since the power is supplied to the circuit block, it is possible to perform the optimal power supply without waste according to the use state, and it is possible to extend the battery life.

According to the second aspect of the present invention, the electronic circuits necessary for realizing the functions or performances in the various operation modes are divided into a plurality of circuit units that are simultaneously / necessarily required for switching the various operation modes. Are connected by a serial signal line capable of transmitting data even in a low power consumption state in which the operation of the main CPU is limited, and transmit and receive data between the respective blocks without the intervention of the main CPU, Set the operation mode of the circuit block by the transmission / reception command between each block,
Since the operation status between each circuit block can be confirmed based on the transmission / reception status information, efficient control between electronic circuit blocks can be performed by serial data communication which can reduce power consumption at low speed even in the power saving mode, The service life can be extended.

[Brief description of the drawings]

FIG. 1 is an external view showing a system configuration of a data processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of a main electronic circuit in the data processing device.

FIG. 3 is a diagram showing a data configuration of serial data input and output between chips of the data processing device.

FIG. 4 is a flowchart showing input / output processing in a serial data interface provided on each of chips A, B, and C of the data processing device.

FIG. 5 is a block diagram showing a configuration of an electronic circuit excluding a resume function unit in the data processing device.

FIG. 6 is a diagram showing a display state of various system state information managed by a system state management unit of the data processing device.

FIG. 7 is a block diagram showing a configuration of an electronic circuit related to a sleep and resume function unit in the data processing device.

FIG. 8 is a timing chart showing a command writing operation when a resume mode is set in a command determination unit of the data processing device.

FIG. 9 is a block diagram showing an internal configuration of a CPU and a sleep control unit which are responsible for a sleep function unit of the data processing device.

FIG. 10 is a diagram showing a relationship between a bus control signal output from a main control unit of a CPU to a bus control unit in the data processing device and the operation content thereof.

FIG. 11 is a flowchart showing sleep processing when the data processing apparatus sets a sleep mode.

FIG. 12 is a block diagram showing an internal configuration of a microcomputer that controls the resume control in the data processing device.

FIG. 13 is a flowchart showing a resume process when the data processing apparatus sets a resume mode.

FIG. 14 is a diagram showing a display state of a resume function cancel message when the resume mode of the data processing apparatus is set.

FIG. 15 is a flowchart showing a suspend-in control process in the CPU of the data processing device.

FIG. 16 is a flowchart showing a suspend-out control process when the data processing apparatus is in the resume mode.

FIG. 17 is a flowchart showing a suspend-out control process in the CPU of the data processing device.

FIG. 18 is a circuit diagram showing an internal configuration of a refresh control unit in the data processing device.

FIG. 19 is a timing chart showing an operation of generating a refresh clock (CAS, RAS) in the refresh control unit of the data processing device.

[Explanation of symbols]

1. Personal computer, 2. Keyboard, 2a ...
SYS key, 2b cursor key, 2c return key, 2d CAPS key, 2e NUM key, 3 liquid crystal display section, 4 memory card mounting section, 5 expansion disk driver, 6 printer, 7 electronic notebook (RS232C-equipped device), 8: expansion unit, 9: expansion disk mounting part, A, B, C: chip, 11: CPU (central processing unit), 12: DMAC (direct memory access controller), 13: ROM, 14 ... RAM, 15 ... Command storage control unit, 16, 28, 33 ... Serial data interface, 17 ... Interrupt control unit, 18 ...
RAM disk control unit, 18a ... RAM disk, 19
... Sleep control unit, 20 ... Refresh control unit, 21 ...
Clock generation control unit, 22 bus control unit, 23 system bus, 24 key interface, 25 RS23
2C interface, 26 printer interface, 27 FDD interface, 29 power supply control unit, 30 system status management unit, 31 clock generation unit, 32 power supply, 34 liquid crystal display interface,
35: System management display control unit, 36: System status display control unit, 37: Display control unit, 38: VRAM, 39 ...
Microcomputer, 40: memory switch storage unit, 41: key input port, 42: liquid crystal display control unit, 43: step tone / inversion control unit, 44: display buffer, 45: command determination unit, 4
6 SRAM, 47 DRAM, 48 GDC (Graphic Display Controller), 49 Bus use clock generation circuit, 50 Bus use counter, 51
Count latch circuit, 52: Main control unit, 53: Match determination unit, 54: Control unit, 55: Input / output port, 55a ...
JOBEND flag area, 55b ... SET flag area, 55c ... error flag area, 56 ... system status register, 56a ... sleep mode register, 56b ...
Resume mode register, 56c sleep register, 56d suspend register, 57 sleep counter, 58 remaining amount determination unit, 59 power switch, 60
a, 60b: shift register, 61: frequency dividing circuit, 62:
Switching signal generator, 63 ... analog delay circuit, FF
... Flip-flop, AND ... And gate, INV ...
Inverter, φSYS ... system operation clock, φREFR ...
Refresh clock, X: refresh switching signal, ST: refresh timing signal, STD: refresh timing delay signal, CAS (column addres)
s strobe), RAS (row address strobe) ... refresh clock.

Claims (2)

[Claims] An information processing apparatus having various system modes in which required functions or performances are limited in accordance with a use state, wherein an electronic circuit required to realize the functions or performances in the various system modes is provided. A power supply that divides into a plurality of circuit blocks in a circuit unit that is simultaneously required / unnecessary in switching the various system modes, and supplies different powers that can be individually turned on / off controlled for each of the divided circuit blocks A data processing apparatus comprising: a supply unit; and a power selection / supply unit configured to supply power to a circuit block required for operation in the system mode when various system modes are set. 2. An information processing apparatus having various operation modes for realizing a required function or performance according to a use state, wherein an electronic circuit required for realizing the function or performance in the various operation modes is: A plurality of circuit blocks divided into circuit units that are required / unnecessary at the time of switching between the various operation modes, and data is transferred between the divided circuit blocks even in a low power consumption state in which the operation of the main CPU is restricted. A communication unit connected by a transmittable serial signal line to transmit and receive data between the blocks without the intervention of a main CPU; and an operation mode of each circuit block is set by a transmission command from the communication unit. The operation state is confirmed between the circuit blocks based on the operation mode setting means and the status information from the communication means. The data processing apparatus characterized by equipped with operating state confirmation means.