KR950003118Y1 - Dtmf receiving sense circuit of private switching system exchange - Google Patents

Abstract

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Description

DFM reception detection circuit of private exchange

1 is a DMP reception detection circuit diagram of a conventional private exchange.

2 is a block diagram of a DFM reception detection circuit of a private exchange according to the present invention.

FIG. 3 is a reference diagram showing FIG. 2 in more detail.

4 is a flowchart of a system operation related to the present invention.

* Explanation of symbols for main parts of the drawings

ㄱ: CPU (B):: PAL logic

C: receiver FM: band division filter

b: bandpass filter c: output decoder

d: output register e: timing circuit

The present invention relates to a DTMF (Dial Tone Multi frequency) ring tone detection means, which can flexibly cope with the increase and decrease of the number of DTP receivers in a private exchange, while simplifying its configuration. The present invention relates to a DMP reception detection circuit.

The DFM reception detection circuit used in the conventional private exchange has shown an example as shown in FIG.

Here, di TM F (multi-frequency) lines (L1, L2) to the high-impedance line for the interface resistance (R1, R2) and the signal capacitor bypass resistor (C1, C2) and a reference voltage setting (R ₃₎ and A line interface circuit 1 composed of a zener diode ED ₁ , ZD ₂ for setting a reference voltage, a feedback resistor R ₄ , and an operational amplifier OP ₁ ; A low pass filter (2) consisting of resistors (R ₅ to R ₈ ) condensers (C ₃ , C ₄ ) and operational amplifiers (OP ₂ ) and receiving the output of the line interface circuit (1); A high pass filter 3 composed of resistors R ₉ to R ₁₂ , capacitors C ₅ and C ₆ and operational amplifiers OP ₃ to receive the output of the line interface circuit 1; Comparator composed of reference voltage supply resistor (R ₁₃ ), feedback resistor (R ₁₄ ), pull-up resistor (R ₁₅ ), and operational amplifier (OP ₄ ) receiving the output of the low pass filter (2) in the '-' stage. (4) and; Comparator composed of a reference voltage supply resistor (R ₁₆ ), a feedback resistor (R ₁₇ ), a pull-up resistor (R ₁₈ ), and an OP amplifier (OP ₅ ) receiving the output of the high pass filter (3) in the '-' stage. (5); The square wave outputs of the comparators 4 and 5 are applied to the low group input terminal R ₀ and the column group input terminal C ₀ , respectively, and converted into digital signals using the programmed memory contents. It consists of a one-chip microprocessor 6 which is output to the row group output terminals RO ₁ to RO ₄ and the column group output terminals CO ₁ to CO ₄ and applied to the controller 7.

In the prior art as described above, when a DFM signal is transmitted to the lines L ₁ and L ₂ , the signal is passed through a line interface circuit 1 which acts as a high impedance 1: 1 amplifier. (2) and high pass filter (3).

The low frequency passing through the low pass filter 2 is output as a low frequency sine wave, and the high frequency passing through the high pass filter is output as a high frequency sine wave. Since the low frequency sine wave is applied to the negative input terminal of the operational amplifier OP ₄ of the comparator 4 and compared with the reference voltage applied to its positive input terminal, a portion of the low frequency sine wave signal lower than the reference voltage is a low potential signal. The high voltage signal is output to the portion higher than the reference voltage and is applied to the row group input terminal R ₀ of the microprocessor 6.

Similarly, the high frequency sine wave signal output from the high pass filter 3 is also applied to the negative input terminal of the operational amplifier OP ₅ of the comparator 5 and compared with the reference voltage applied to its plus input terminal so that its output is micro. It is applied to the column group input terminal C ₀ of the processor 6.

Therefore, the microprocessor 6 counts the pulse number of the square wave signal for a predetermined time only when the square wave signal is simultaneously applied to the row group input terminal R ₀ and the column group input terminal C _{0 as} described above. The number of pulses counted is compared with the contents of the memory, respectively, to distinguish the row group address and the column group address of the received complex frequency.

In addition, the low-group address and column-group address signals are converted into the coded signals corresponding to the keys of the complex frequency and stored in the latches, and then the low-group output terminals (RO ₁ to RO ₄ ) and the column group output terminals. The low potential signal is output while the complex frequency signal is received only at the output terminal corresponding to the code signal among (CO ₁ to CO ₄ ).

In this way, the complex frequency signal received at the lines (L ₁ , L ₂ ) is converted into a code signal in the microprocessor 6 and applied to the control device 7, so that the switching function corresponding to the code signal , During a call, ...).

However, in the conventional DMP reception sensing circuit as described above, a large number of component elements (that is, a resistor, a capacitor, an operational amplifier), a system microprocessor, and the like which constitute a single DFM reception sensing circuit are required. In order to increase the number of DFM receivers in the system, each of the DFM receiver detection circuits having the above-described configuration must be individually provided, thereby increasing the area occupied by the system circuit and increasing the number of parts. It was also disadvantageous in terms of maintenance.

The object of the present invention is to devise a method for improving the above-described problems of the prior art, which is to provide a separate microprocessor for receiving a DTP receiver in a DTP receiver, in particular, when the DTP receiver is expanded in a system. The present invention provides a DMP reception detection circuit capable of performing a DFM reception detection function even if it is not provided.

Hereinafter, this will be described in more detail with reference to the accompanying drawings.

2 shows a system circuit block of the DFM reception detection circuit according to the present invention.

In this case, the DTP receiver receives the output data of the DTP receiver and controls the DTP receiver by the address output and is connected to the exchange device of the exchange system, and the DTP is output by the output address of the receiver. It is composed of PAL logic receiver for controlling receiver and DTP receiver which receives analog signal (AS) input of DFM and transmits it to data.

In addition, the DMP receiver ㈂ shows this in more detail as shown in FIG. 3.

Here, a band split filter (a) receiving an analog signal (AS) input of DTF, a band filter (b) connected to an output of the band split filter (a) to filter signals of a predetermined band, and An output register (d) for receiving the output of the bandpass filter (b) through the output decoder (c) and outputting data (D ₀ to D ₃ ) applied to the receiver, and decoding the output register (d). A decoder (c) for providing a digital signal, and a timing circuit (e) which are coupled to the output side of the bandpass filter (b) and provide a timing signal at the rear of the system, are configured.

The present invention of such a configuration is as follows.

That is, the DFM signal input as an analog signal from the system is input to the DFM receiver, and the DFM receiver is a signal received by the enable signal of the DFM signal controlled by PAL logic. It is transmitted through the D7 signal to the UE.

If you read the 16 standard frequencies by D0 ~ D3 as data from the DFM receiver, you can see that the signal is a DFM signal.

In this case, when the DTP receiver detects the DTP code at the DFM receiver, the UE sends a detected signal to the exchange apparatus of the exchange system to perform an operation necessary for connecting a trunk line or performing a call exchange. will be.

In addition, in PLogic㈁, the information on how much DTM is to be scanned is determined by the period of the UE, and in the exchange, the UE accesses the address periodically every 16 ms, and detects the DFM signal.

Meanwhile, as shown in FIG. 3, the DMP receiver T is divided into a high frequency signal and a low frequency signal by a band-sized filter (a), and the signal is divided into international standard DMT signals. After passing the band through the bandpass filter (b) according to the tone signal, it is input to the output decoder (c) and the timing circuit (e) and outputs that this signal is a DFT signal, and the output register (d) The output signal of the output decoder (c) is applied together with the enable signal provided by the logic logic to convert each signal into data.

When the system receiver detects and processes the DFM signal in the system, as shown in Fig. 4, if the terminal hook is 'off', the DTP receiver is selected and the first digit of the dial pulse / DMP is selected. (digit) is checked to determine the dial pulse / DMP. If the determined signal is DMP, it is determined to be the first digit. If it is not the first digit, the digit is checked again. Release (Receiver Release).

Therefore, the present invention is economically advantageous because it implements the desired circuit with few components, and the number of DFM receivers can be increased or decreased depending on the capacity of the exchanger. As the number of TFM ports increases, the area occupied by the circuit is reduced and cost is reduced.

Claims (2)

In the DFM reception detection circuit of the private exchange, DFM receiver digital code data, etc. are generated from the DFM analog signal and provided to the system receiver, and connected to the address output of the receiver. A PAL logic receiver that receives an address signal from the PDP receiver and provides an enable signal to the DFM receiver, and a DFM receiver that connects the enable signal terminal of the PAL logic receiver to output DFM digital data. DFM reception detection circuit of a private exchange, characterized in that consisting of. The band receiver of claim 1, wherein the DMP receiver ㈂ receives a band split filter (a) for separating the analog input DTF signals into high and low frequencies, and a band through which the output of the band split filter is applied. An output register (d) which receives the pass filter (b) and the output of the band pass filter (b) through an output decoder (c), converts the digital signal together with the enable signal of the follow logic, and transmits the digital data to the receiver. And a timing circuit (e) for receiving the output of the bandpass filter (b) and outputting that the input signal is a DFT signal.