KR950001132Y1 - Clear circuit of souce - Google Patents

Abstract

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Description

Power clear circuit

1 is a conventional power supply clear circuit diagram.

2 is a power supply clear circuit diagram of the present invention.

3 is an operation timing diagram according to FIG.

* Explanation of symbols for main parts of the drawings

1: bias part 2: current source

3: sync signal generator 4: Schmitt trigger

MN: NMOS transistor MP: PMOS transistor

R: Resistance INV: Inverter

C: Capacitor

The present invention relates to a power supply clearing circuit, and more particularly, to a power supply clearing circuit mounted in a chip to have a desired clear when a power supply is applied.

FIG. 1 is a conventional power supply clear circuit diagram. As shown therein, a power supply terminal V _DD is connected to a drain of an NMOS transistor MN1 having a gate and a drain connected through a resistor R1 and a power supply terminal V. As shown in FIG. _DD ) is connected to the gate of the PMOS transistor MP1 connected to the source, and the source of the NMOS transistor MN1 is connected to the drain of the NMOS transistor MN2 connected to the gate of the power supply terminal V _DD . and it is connected to the source and the drain thereof yen of the PMOS transistor (MP1) also connected to the capacitor (C1) a grounded drain, and well as the power supply terminal (V _DD) PMOS transistor (MP2) of the MOS transistor (MN ₃ ) Is connected to the gates of the PMOS transistor MP2 and the NMOS transistors MN3 and MN4 respectively connected to the drain of the NMOS transistor MN4, and the PMOS transistor MP2 and the NMOS transistor are respectively connected to each other. JIS The common drain connection point of the (MN3) power supply terminal (V _DD) of the NMOS transistor (MN5) connected to the gate box and well connected to the input side of the inverter (INV), and the NMOS transistor (MN3) of the connected to the drain The source and drain connection points of the NMOS transistor MN4 were connected to the source of the NMOS transistor MN5, and the output side of the inverter INV was connected to the output terminal OUT.

In the conventional power supply clearing circuit configured as described above, when the power supply is turned on, the NMOS transistor MN2 is turned on, and the NMOS transistor MN1 is turned on by the voltage A dropped in the resistor R1. At this time, the voltage A is taken as a bias voltage by the turn-on resistance values of the resistor R1 and the NMOS transistors MN1 and MN2.

Therefore, when the bias voltage is lower than the threshold voltage V _{T of} the PMOS transistor MP1, the PMOS transistor MP1 is turned on, so that the capacitor C1 is charged. At this time, since the initial value of the capacitor C1 is low potential, the PMOS transistor MP2 is turned on and turned on to the NMOS transistor MN5 by the high potential applied to the drain of the PMOS transistor MP1. In addition, the high potential is inverted to a low potential by the inverter INV and output to the output terminal OUT.

Thereafter, when the value charged in the capacitor C1 increases and becomes higher than the threshold voltage V _T of the NMOS transistors MN3 and MN4, the PMOS transistor MP1 is turned off and the NMOS transistor MN3 is turned off. , MN4) is turned on. Therefore, the input of the inverter INV becomes low potential, the output of the inverter INV becomes high potential, and this high potential is output to the output terminal OUT.

Here, the variation of the clear time is controlled by the sizes of the resistor R1, the PMOS transistor MP1, and the NMOS transistor MN5.

As described above, the conventional power supply clearing circuit has a limit to increase the resistance value of the resistor, and is used as a well resistor on a layout to occupy a large area and have difficulty in lengthening the clearing time. There was a following issue.

In order to solve this problem, the present invention devised a power supply clear circuit that supplies a bias voltage by using a MOS device instead of a resistor that occupies a large area, and adjusts a desired clear in the chip itself. This will be described in detail with reference to the accompanying drawings.

FIG. 2 is a power supply clear circuit diagram of the present invention, and as shown therein, a bias unit 1 for supplying a bias voltage and a synchronization signal for clearing are turned on and off by a current supplied from the bias unit 1. And a Schmitt trigger (4) which outputs a clear signal in synchronization with the synchronizing signal output from the synchronizing signal generator (3).

Referring to the operation and effects of the present invention configured as described above in detail.

When the power supply is turned on as shown in FIG. 3, the NMOS transistors MN6 and MN8 and the PMOS transistors MP3 and MP5 of the bias unit 1 are turned on. At this time, since the PMOS transistor MP4 is initially turned on, the NMOS transistor MN7 is also turned on accordingly. Accordingly, the bias voltage is supplied to the PMOS transistor MP7 and the NMOS transistor MN9 of the current source 2 from the output sides S1 and S2 of the bias unit 1 to supply the PMOS transistor MP7 and the NMOS transistor ( MN9 is turned on and PMOS transistor MP6 is also turned on. Therefore, the output side S3 of the current source 2 gradually charges a certain amount of current to the capacitor C2 of the synchronous signal generator 3. At this time, since the capacitor C2 is initially charged at a low potential as shown in ⓑ of FIG. 3, the PMOS transistor MP8 is turned on and the NMOS transistors MN11 and MN12 are turned off. Accordingly, the output side S4 of the synchronization signal generator 3 applies a high potential signal such as © in FIG. 3 to the Schmitt trigger 4, whereby the PMOS transistors MP9 and MP11 are turned off and the NMOS transistor is turned off. Since the MN13 is turned on, the Schmitt trigger 4 outputs a low potential to the output terminal OUT as shown in FIG. At this time, the PMOS transistor MP10 is turned on.

In addition, the high potential output from the synchronization signal generator 3 to the output side S4 is fed back to the NMOS transistor MN10 of the current source 2, and the NMOS transistor MN10 is subsequently connected to the PMOS. The current S3 output from the drain of the transistor MP7 is divided into the currents ic ₂ and i ₉ flowing through the capacitor C2 and the NMOS transistor MN9, so that the current is charged by the capacitor C2. Is more slowly charged.

Thereafter, when the potential charged in the capacitor C2 is higher than the threshold voltage V _{T of the} NMOS transistors MN11 and MN12, the NMOS transistors MN11 and MN12 are turned on so that the synchronization signal generator 3 may be turned on. As shown in Fig. 3 of the output side S4 of FIG. 3, the low potential is fed back to the current source 2 to turn off the NMOS transistor MN10 to fill the potential of the capacitor C2 in FIG. As it increases further as ⓑ, the output side S4 of the synchronization signal generator 3 is further dropped to a lower potential as shown by ⓒ in FIG. Accordingly, even if the PMOS transmitters MN9 and MP11 of the Schmitt trigger 4 are turned on, the same signal as ⓓ in FIG. 3 is output to the output terminal OUT. At this time, the PMOS transistor MP10 is oppressed.

As described above, the present invention has the effect of controlling the desired clear on its own, and by configuring the bias supply with the Morse element, the chip area can be minimized, and thus the effect can be applied to a small area.

Claims (6)

A bias unit 1 for supplying a bias voltage as power is supplied, and a current source 2 for supplying a certain amount of current according to the bias voltage supplied from the bias unit 1 and stopping the supply of the current by a synchronization signal 2 ), A synchronization signal generator (3) for charging a predetermined amount of current supplied from the current source (2), and controlling the charging potential to generate the synchronization signal for clearing, and the synchronization signal generator (3). And a Schmitt trigger (4) for outputting a clear signal in synchronization with a synchronous signal output from the power supply. 2. The bias unit (1) according to claim 1, wherein the bias unit (1) connects the power supply terminal (V _DD ) to the drain and gate of the NMOS transistor MN6, and supplies the source of the NMOS transistor MN6 to the PMOS transistor MP3 (MP4). ) And NMOS transistors MN7 and MN8 are sequentially connected to the source of the PMOS transistor MP5 whose drain is grounded, and the gate of the NMOS transistor MN8 and the PMOS transistors MP3 and MP5 are connected. A power supply terminal V _DD and a ground terminal V _DD are respectively connected to a gate of the PMOS transistor MP4 and the NMOS transistor MN7. The common gate connection point of the PMOS transistor MP4 and the NMOS transistor M4 is connected to the PMOS transistor MP4 and the NMOS. The drain-source connection point of the PMOS transistor MP3 (MP4) and the source-drain connection point of the NMOS transistor MN7 (MN8) are connected to the common drain of the transistor MN7 and the output terminal S1 (S2). Are each connected to) Clear the power circuit. 2. The current source 2 according to claim 1, wherein the power source terminal V _DD is connected to the source of the PMOS transistor MP6, and the drain of the PMOS transistor MP6 is connected to the PMOS transistor MP7 and the NMOS transistor ( The source of the PMOS transistor MP6 is connected to the drain of the NMOS transistor MN10 having the source grounded through MN9, the gate of the PMOS transistor MP6 is connected to the ground terminal GND, and the output terminal S1 of the bias unit 1 is connected. (S2) is connected to the gate of the PMOS transistor MP7 and the gate of the NMOS transistor MN9, respectively, and the gate of the NMOS transistor MN10 is connected to the output terminal of the synchronous signal generator 3. And a power supply clearing circuit. 2. The synchronizing signal generator 3 connects the power supply terminal V _DD to the source of the PMOS transistor MP8, and drains the drain of the PMOS transistor MP8 through the NMOS transistor MN11. The source is connected to the drain of the grounded NMOS transistor MN12, the output terminal S3 of the current source 2 is connected to the capacitor C2, and the connection point is connected to the PMOS transistor MP8 and the NMOS transistor ( A power supply clearing circuit comprising a common connection to the gates of MN11 and MN12. 2. The Schmitt trigger (4) according to claim 1, wherein the Schmitt trigger (4) connects the power supply terminal (V _DD ) to the source of the PMOS transistor MP9, so that the source of the PMOS transistor MP9 is drained through the PMOS transistor MP11. The drain of the grounded NMOS transistor MN13 is connected, and the output terminal S4 of the synchronization signal generator 3 is commonly connected to the gates of the PMOS transistors MP9 and MP11 and the NMOS transistor MN13. The drain of the PMOS transistor MP11 and the NMOS transistor MN13 is commonly connected to the output terminal OUT, and the source is connected to the drain-source connection point of the PMOS transistor MP9 and MP11. A power supply clearing circuit, which is configured by being connected to a gate of a PMOS transistor MP10. 5. The power supply clearing circuit according to claim 4, wherein the output (S4) of the synchronization signal generator (3) is configured to control the output (S3) of the current source (2) by turning on / off the NMOS transistor (MN10). .