KR950000448Y1 - Power source circuit of lcd indication devices - Google Patents
Power source circuit of lcd indication devices Download PDFInfo
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- KR950000448Y1 KR950000448Y1 KR92008395U KR920008395U KR950000448Y1 KR 950000448 Y1 KR950000448 Y1 KR 950000448Y1 KR 92008395 U KR92008395 U KR 92008395U KR 920008395 U KR920008395 U KR 920008395U KR 950000448 Y1 KR950000448 Y1 KR 950000448Y1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2230/00—Details of flat display driving waveforms
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
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Abstract
내용 없음.No content.
Description
제1도는 종래 액정표시 구동전원회로 구성도.1 is a configuration diagram of a conventional liquid crystal display driving power supply circuit.
제2도는 제1도에 따른 전원회로와 액정표시 구동회로의 전원공급 표시도.2 is a power supply display of the power supply circuit and the liquid crystal display driving circuit according to FIG.
제3도는 본 고안 액정표시 구동전원회로 구성도.3 is a configuration diagram of a liquid crystal display driving power supply circuit of the present invention.
제4도의 (a) 내지 (d)는 제3도에 따른 파형관계도.(A) to (d) of FIG. 4 are waveform relationship diagrams according to FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 제어회로 2 : 전원회로1: control circuit 2: power supply circuit
3 : 액정표시 구동회로 4 : 액정표시판넬3: liquid crystal display driving circuit 4: liquid crystal display panel
5 : 분주기 6 : 레벨시프트부5: frequency divider 6: level shift unit
7 : 전압승압부 MP1, MP7 : 피모스 트랜지스터7: voltage boosting unit MP1, MP7: PMOS transistor
MN1-MN7 : 엔모스 트랜지스터 INV1, INV2 : 인버터MN1-MN7: NMOS transistor INV1, INV2: Inverter
C11, C12 : 캐피시터 R1-R6 : 저항C11, C12: Capacitor R1-R6: Resistance
CL1 : 래치클럭 CL2 : 시프트클럭CL1: Latch Clock CL2: Shift Clock
FLM : 프레임 스타트신호 M : 교류화신호FLM: Frame start signal M: AC signal
D : 표시전극 데이타D: display electrode data
본 고안은 액정표시 구동전원회로에 관한 것으로, 특히 액정구동전압을 생성하는 전원회로를 액정표시 구동소자내에 내장하여 액정구동전압을 발생함으로써 외부에서 공급되는 전원단자를 줄일 수 있도록한 액정표시 구동전원회로에 관한 것이다.The present invention relates to a liquid crystal display driving power circuit, and in particular, a liquid crystal display driving power source having a power supply circuit for generating a liquid crystal driving voltage in a liquid crystal display driving element to generate a liquid crystal driving voltage to reduce a power supply terminal supplied from the outside. It is about a circuit.
제1도는 종래 액정표시 구동전원회로 구동도로서, 이에 도시된 바와같이 전체시스템을 제어하기 위한 제어신호(CL1, CL2, FLM, M, D)를 출력하는 제어회로(1)와, 액정을 구동하기 위한 액정구동전압(V1-V4)을 출력하는 전원회로(2)와, 그 전원회로(2)에서 출력되는 액정구동전압(V1-V4)에 의해 상기 제어신호(CL1, FLM, M)를 처리하여 로우(Row)를 구동하기 위한 구동신호(O1-Om)를 출력함과 아울러 상기 제어신호(CL1, CL2, D, M)를 처리하여 컬럼(Column)을 구동하기 위한 구동신호(O1-On)을 출력하는 액정표시 구동회로(3)와, 그 액정 표시 구동회로(3)로부터 출력되는 구동신호(O1-Om)(O1-On)에 의해 문자나 기호를 디스플레이하는 액정표시판넬(4)로 구성하였다.FIG. 1 is a conventional liquid crystal display driving power supply circuit driving diagram, as shown in FIG. The control signals CL1, FLM, M are outputted by the power supply circuit 2 for outputting the liquid crystal drive voltages V1-V4 and the liquid crystal drive voltages V1-V4 output from the power supply circuit 2. Outputs driving signals O1-Om for driving the row and processes the control signals CL1, CL2, D and M to drive the columns O1-Om. A liquid crystal display panel 4 for displaying a character or a symbol by a liquid crystal display driver circuit 3 for outputting On) and a drive signal O1-Om (O1-On) outputted from the liquid crystal display driver circuit 3; ).
이와같이 구성된 종래 액정표시 구동회로는 먼저 제어회로(1)에서 시스템을 제어하는 제어신호(CL1, CL2, FLM, M, D)를 액정표시 구동회로(3)로 인가하고, 제2도에 도시된 바와같이 전원회로(2)의 VDD와 VEE간에 인가된 전압은 저항(R1-R5)에 의해 액정구동전압(V1-V4)으로 분압되어 상기 액정표시 구동회로(3)의 구동전원으로 공급된다.The conventional liquid crystal display driver circuit configured as described above first applies the control signals CL1, CL2, FLM, M, D to the liquid crystal display driver circuit 3 to control the system from the control circuit 1, and is shown in FIG. As described above, the voltage applied between V DD and V EE of the power supply circuit 2 is divided into the liquid crystal driving voltages V1-V4 by the resistors R1-R5 and supplied to the driving power of the liquid crystal display driving circuit 3. do.
이와같이 상기 액정표시 구동회로(3)로 공급되는 액정구동전압(V1-V4)간의 관계는 구동 바이어스수에 따라 결정되며, 최적의 바이어스수에 의해 1/10바이어스의 경우 상기 액정구동전압(V1-V4)은 하기의 식(1) 내지 (4)와 같이 나타낼 수 있다.As such, the relationship between the liquid crystal driving voltages V1-V4 supplied to the liquid crystal display driving circuit 3 is determined according to the number of driving biases, and in the case of 1/10 bias, the liquid crystal driving voltages V1-1 by an optimal bias number. V4) can be represented by the following formulas (1) to (4).
또한 상기 액정표시 구동회로(3)에서 내부로직은 VDD와 VSS간에 +5V가 공급되어 동작되며, 상기 액정구동전압(V1-V4)는 액정표시 구동회로(3)의 내부구동전극으로 전달되어 액정이 구동된다.In addition, the internal logic of the liquid crystal display driving circuit 3 is operated by supplying +5 V between V DD and V SS , and the liquid crystal driving voltages V1-V4 are transferred to the internal driving electrode of the liquid crystal display driving circuit 3. The liquid crystal is driven.
이에따라 상기 액정표시 구동회로(3)는 액정이 구동됨에 의해 로우(Row)을 구동하는 액정구동신호(O1-Om)와 컬럼(Column)을 구동하는 액정구동신호(O1-On)을 액정구동판넬(4)로 인가하므로 그 액정구동판넬(4)은 액정구동신호(O1-Om)(O1-On)에 의해 문자나 기호를 디스플레이하게 된다.As a result, the liquid crystal display driving circuit 3 includes a liquid crystal driving signal O1-Om for driving a low and a liquid crystal driving signal O1-On for driving a column by driving a liquid crystal. Since it is applied to (4), the liquid crystal drive panel 4 displays characters or symbols by the liquid crystal drive signals O1-Om (O1-On).
상기에서 설명한 바와같이 종래 액정표시 구동전원회로는 액정표시 구동회로(3)의 로직전원(VDD와 VEE)과 액정구동전원(VDD와 VSS, V1-V4)을 별도로 공급해야 하므로 소자의 핀수가 증가하고, 회로 구성이 복잡하며, 또한 구성부품수가 많아 생산원가가 높고, 생산율이 낮으며, 액정표시장치의 신뢰성을 저하시키는 문제점이 있었다.As described above, the conventional liquid crystal display driving power circuit has to separately supply the logic power supply (V DD and V EE ) and the liquid crystal driving power supply (V DD and V SS , V1-V4) of the liquid crystal display driving circuit 3. The number of pins increases, the circuit configuration is complicated, and the number of component parts is high, resulting in high production cost, low production rate, and low reliability of the liquid crystal display device.
본 고안은 이러한 문제점을 해결하기 위하여 전원회로를 구동소자내에 내장하여 액정구동전압(V1-V4)을 만들 수 있도록 함과 아울러 액정표시 구동호로에 공급되는 전원단자를VDD와 VSS두개로 줄일수 있도록한 액정표시 구동전원회로를 안출한 것으로, 이를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In order to solve this problem, the present invention allows a liquid crystal driving voltage (V1-V4) to be built in the power supply circuit, and reduces the power supply terminals supplied to the liquid crystal display driving arc to V DD and V SS . A liquid crystal display driving power circuit is provided, which will be described in detail with reference to the accompanying drawings.
제3도는 본 고안 액정표시 구동전원회로 구동도로서, 이에 도시한 바와같이 내부시프트클럭(CL2)을 분주하는 분주기(5)와, 그 분주기(5)에서 분주된 클럭레벨을 시프트시키는 레벨시프트부(6)와, 그 레벨시프트부(6)에서 시프트된 클럭레벨에 따라 로직전압(VDD, VSS)을 승압하는 전압승압부(7)와, 그 전압승압부(7)에서 승압된 전압을 분압하여 액정구동전압(V1-V4)을 발생하는 전원회로(2)와, 그 전원회로(2)에서 출력되는 액정구동전압(V1-V4)에 의해 제어회로에서 출럭되는 제어신호(CL1, CL2, FM, M, D)신호를 처리하여 구동신호(O1-Om)(O1-On)을 발생하는 액정표시 구동회로(3)로 구성한다.FIG. 3 is a driving diagram of the liquid crystal display driving power circuit of the present invention, and as shown therein, a divider 5 for dividing the internal shift clock CL2 and a level for shifting the clock level divided by the divider 5. A voltage boosting unit 7 for boosting the logic voltages V DD and V SS according to the shift unit 6 and the clock level shifted by the level shift unit 6; The control signal outputted from the control circuit by the power supply circuit 2 which generates the liquid crystal driving voltages V1-V4 by dividing the supplied voltage and the liquid crystal driving voltages V1-V4 output from the power supply circuit 2 ( A liquid crystal display driving circuit 3 is configured to process the signals CL1, CL2, FM, M, D and generate driving signals O1-Om (O1-On).
이와같이 구성된 본 고안의 작용 및 효과를 상세히 설명하면 다음과 같다.Referring to the operation and effects of the present invention configured as described above in detail.
액절표시 구동회로(3)의 내부에 존재하는 시프트클럭(CL2)를 분주기(5)가 분주하여 5KHz-50KHz의 클럭인(CLKin)신호를 만들어 레벨시프트부(6)로 출력한다.The divider 5 divides the shift clock CL2 existing in the liquid crystal display driver circuit 3 to generate a clock-in (CLKin) signal of 5KHz-50KHz and output it to the level shift unit 6.
이때 상기 클럭인(CLKin)신호가 저전위레벨이면, 그 저전위는 인버터(INV1)에서 고전위로 반전되어 피모스트랜지스터(MP1)를 턴-오프시키므로 점 NO는 저전위가 된다. 또한, 상기 인버터(INV1)에서 출력되는 고전위는 인버터(INV2)를 통해 저전위로 반전되어 피모스 트랜지스터(MP2)를 턴-온시키므로, 점 N1은 고전위가 되며, 그 고전위는 피모스 트랜지스터(MP3)와 엔모스 트랜지스터(MN3)로 구성된 인버터에서 저전위로 반전되므로, 점 N2는 저전위가 되고, 그 저전위는 피모스 트랜지스터(MP4)와 엔모스 트랜지스터(MN4)로 구성된 인버터에서 고전위로 반전되므로, 점 N3는 고전위가 되며, 그 고전위는 피모스 트랜지스터(MP5)와 엔모스 트랜지스터(MN5)로 구성된 인버터에서 반전되므로, 점 N4는 저전위가 되어 전압승압부(7)로 인가된다.If the clock-in signal CLKin is at the low potential level, the low potential is inverted to high potential in the inverter INV1 to turn off the PMOS transistor MP1, so that the point NO becomes low potential. In addition, since the high potential output from the inverter INV1 is inverted to a low potential through the inverter INV2 to turn on the PMOS transistor MP2, the point N1 becomes a high potential, and the high potential is a PMOS transistor. Inverting to low potential in the inverter composed of MP3 and NMOS transistor MN3, the point N2 becomes low potential, and the low potential becomes high potential in the inverter composed of PMOS transistor MP4 and NMOS transistor MN4. Since it is inverted, the point N3 becomes a high potential, and since the high potential is inverted in an inverter composed of the PMOS transistor MP5 and the NMOS transistor MN5, the point N4 becomes the low potential and is applied to the voltage boosting section 7. do.
따라서, 점 N4의 저전위 출력은 피모스 트랜지스터(MP6)와 엔모스 트랜지스터(MN6)으로 구성된 인버터에서 고전위로 반전되므로 상기 전압승압부(7)의 C1핀에는 VDD전압이 인가되며,상기 점 N2의 저전위가 피모스 트랜지스터(MP7)와 엔모스 트랜지스터(MN7)로 구성된 인버터에서 고전위로 반전되므로, 점 C2핀에는 VSS전압이 인가된다. 따라서 캐패시터(C11)에는 VDD와 VSS간의 전압이 인가되어 충전된다.Accordingly, since the low potential output of point N4 is inverted to high potential in an inverter composed of PMOS transistor MP6 and NMOS transistor MN6, the voltage V DD is applied to the C1 pin of the voltage boosting unit 7. Since the low potential of N2 is inverted to high potential in an inverter composed of PMOS transistor MP7 and NMOS transistor MN7, the voltage V SS is applied to pin C2. Therefore, the capacitor C11 is charged with a voltage between V DD and V SS .
반면, 상기 클럭인(CLKin)신호가 고전위 레벨이면, 그 고전위는 상기 인버터(INV1)에서 저전위로 반전되어 상기 피모스 트랜지스터(MP1)를 턴-온시키므로 범(NO)는 고전위가 된다.On the other hand, if the clock-in signal CLKin is at the high potential level, the high potential is inverted to a low potential in the inverter INV1 to turn on the PMOS transistor MP1, so that the NO becomes high. .
또한, 상기 인버터(INV1)의 저전위 출력은 상기 인버터(INV2)에서 고전위로 반전되어 상기 피모스 트랜지스터(MP2)를 턴-오프시키므로 점 N1은 저전위가 된다.In addition, since the low potential output of the inverter INV1 is inverted to a high potential in the inverter INV2 to turn off the PMOS transistor MP2, the point N1 becomes a low potential.
이에따라 점 N2, N4는 고전위가 되고, N3는 저전위가 되므로, 상기 전압승압부(7)의 C1핀에는 VSS전압이 인가되고, C2핀에는 상기 캐패시터(C11)에 충전되었던 VDD와 VSS간의 전압만큼 낮은 전압상태로 VEE전압 상태를 유지하게 된다.Accordingly, since the points N2 and N4 become high potential and N3 becomes low potential, V SS voltage is applied to the C1 pin of the voltage boosting unit 7, and V DD charged to the capacitor C11 to the C2 pin. It maintains the V EE voltage state as low as the voltage between V SS .
이때 상기 클럭인(CLKin)신호와 점 N4의 파형도는 제4도의(a)와 같이 도시되고, 상기 전압승압부(7)의 C1핀과 C2핀에 인가되는 전압 파형도는 제4도의 (b)와 같이 도시되며, 상기 클럭인(CLKin)신호와 VEE전압파형도는 제4도의 (c)와 같이 도시할 수 있다.In this case, the clock signal CLKin and the waveform diagram of the point N4 are shown in FIG. 4A, and the voltage waveforms applied to the C1 and C2 pins of the voltage boosting unit 7 are shown in FIG. shown as b) and the clock (CLKin) and a signal V EE voltage waveform may be shown as a fourth degree (c).
따라서, 클럭인(CLKin)신호가 계속적으로 스위칭됨에 따라 위의 동작이 반복되면 상기 전압승압부(7)에서 VDD와 VSS간의 전압이 승압되어 VDD와 VEE간에 걸리게 된다.Accordingly, when the clock-in signal CLKin is continuously switched, if the above operation is repeated, the voltage booster 7 boosts the voltage between V DD and V SS to be caught between V DD and V EE .
한편, 상기 전압승압부(7)의 VDD와 VSS단자간에 병렬 연결된 저항(R6)과 캐패시터(C12)는 VEE단자의 스위칭 노이즈를 제거한다.On the other hand, a resistance (R6) and the capacitor (C12) connected in parallel between V DD and V SS terminal of the voltage boosting section (7) removes the switching noise of the V EE terminal.
따라서 전원회로(2)는 VDD와 VEE사이에 승압된 전압을 저항(R1-R5)으로 분압하여 제4도의 (d)와 같은 액정구동전압(V1-V4)을 생성하며, 이 액정구동전압(V1-V4)을 액정표시 구동회로(3)로 출력한다.Therefore, the power supply circuit 2 divides the voltage boosted between V DD and V EE by the resistors R1-R5 to generate the liquid crystal driving voltages V1-V4 as shown in FIG. The voltages V1-V4 are output to the liquid crystal display drive circuit 3.
따라서, 상기 액정표시 구동회로(3)는 그 액정구동전압(V1-V4)에 의해 제어신호(CL1, CL2, FLM, M, D)를 처리하여 구동신호를 출력함으로, 액정표시판넬에 의해 문자나 기호가 디스플레이되어 진다.Accordingly, the liquid crystal display driving circuit 3 processes the control signals CL1, CL2, FLM, M, D according to the liquid crystal driving voltages V1-V4, and outputs a driving signal. Symbol is displayed.
상기에서 설명한 바와같이 본 고안은 액정구동전원을 구동소자내부에 내장하여 사용하므로, 액정표시 간소화할 수 있고, 부품수가 감소하여 제조원가를 줄일수 있으며, 액정표시장치의 생산수율 및 신뢰성을 높일수 있는 효과가 있을 뿐만아니라 전원단자를 VDD와 VSS두개로 줄일 수 있는 유용한 효과가 있다.As described above, the present invention incorporates a liquid crystal driving power supply into the driving element, thereby simplifying the display of the liquid crystal, reducing the number of parts, reducing the manufacturing cost, and increasing the production yield and reliability of the liquid crystal display device. In addition, there is a useful effect of reducing the power supply terminal to two V DD and V SS .
Claims (7)
Priority Applications (1)
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KR92008395U KR950000448Y1 (en) | 1992-05-16 | 1992-05-16 | Power source circuit of lcd indication devices |
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KR92008395U KR950000448Y1 (en) | 1992-05-16 | 1992-05-16 | Power source circuit of lcd indication devices |
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KR930026330U KR930026330U (en) | 1993-12-28 |
KR950000448Y1 true KR950000448Y1 (en) | 1995-01-27 |
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KR92008395U KR950000448Y1 (en) | 1992-05-16 | 1992-05-16 | Power source circuit of lcd indication devices |
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