KR950000343B1 - Memory tester - Google Patents

Abstract

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Description

Memory tester

1 is a diagram for explaining a bit line of a DRAM having a polarity inversion function;

2 is a block diagram of a conventional memory test apparatus,

3 is a diagram showing an example of a polarity inversion region;

4A is a display diagram of an example of data set in the X address area inversion memory;

4B is a display diagram of an example of data set in the Y address region inversion memory;

5 is a display diagram of an example of data set in the inversion register;

6 is a view showing another example of the polarity inversion region,

7 is a block diagram showing an embodiment of a memory test apparatus of the present invention;

8 is a display diagram of a specific example of the polarity controller 40 in FIG.

9 is a diagram showing an example of data stored in the area inversion memory 48;

* Explanation of symbols for main parts of the drawings

10: pattern generator 11: address generator

12: data generator 20: memory under test

30: logical comparator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus for testing a memory made by a semiconductor, and more particularly, to a memory test apparatus with a function suitable for testing a memory having a large storage capacity.

In dynamic random access memory (DRAM), a differential sense amplifier is used as a bit sense circuit for reading from a memory cell. For example, as shown in FIG. 1, vertical lines X1, X2, ... called word lines are provided corresponding to X addresses (column addresses), and bits are provided for each Y address (low address), respectively. A pair of horizontal lines Y1a, Y1b, Y2a, Y2b, called lines; Is installed.

Each pair of bit lines (Y1a, Y1b), (Y2a, Y2b),... Are alternately connected to the memory cells MC of a series of X addresses on the same Y address, and are connected at one end to corresponding non-inverting inputs and inverting inputs of the sense amplifiers SA1, SA2, ... have. Therefore, even if the logical value "1" is written into an arbitrary memory cell MC, the output logic read out depends on which of the two inputs of the sense amplifier is connected to the bit line connected to the memory cell MC.

Therefore, when such data is written into the memory cells MC, the DRAM stores the data in the memory cells as it is or the logic of the data depending on which of the pair of bit lines is connected. By reversing and storing, data can always be read with correct logic. Such a DRAM function will be referred to as a polarity inversion function. In the above, the case where each Y address is addressed by a pair of bit lines is shown, but each X address may be configured to be accessed by a pair of bit lines and read by a differential sense amplifier, or a combination thereof may be configured. There is also.

As the capacity of the DRAM becomes 4M bits and 16M bits, the coupling capacity between the bit lines increases, and the capacity of each memory cell decreases, so that the S / N of reading decreases.

In order to prevent this problem, a twisted pair of bit lines connected to each differential sense amplifier intersect each other at a plurality of portions to reduce coupling noise by bit lines approaching each other and to improve S / N. The bit line method is sometimes used.

This method has a problem in that the write control is complicated because the address for inverting the logic of data and the address for writing without inversion are mixed.

When testing a memory with a polarity inversion function, the test data is designated by simply giving a test pattern signal consisting of an address and data (consisting of test data and expected data) to the memory under test as in the prior art. Writes to and reads the data, and tests whether the read data matches the expected data, in addition to a memory area in which the polarity (i.e., logic) is inverted and written in the memory, and writing is performed without inversion. It is required to perform the test by writing so that the polarity distribution of the data in the storage area is the same, or by operating under extreme conditions in which " 1 " or " 0 "

Such a test can be executed by modifying the pattern generator program of the pattern generator that generates the test pattern, but the program modification is laborious and difficult. In addition, since the specifications of the memory under test are not constant and the polarity inversion area and the non-inversion area are not constant, it is cumbersome to modify the program to conform to each standard.

For this reason, a test is constructed so that the polarity inversion region of the memory under test is conventionally recognized by the test apparatus and the polarity of the test data signal can be "inverted" or "not inverted" freely when the polarity inversion region is accessed. The device is being built.

2 shows an example thereof.

10 shows a pattern generator. The pattern generator 10 includes an address generator 11 and a data generator 12 for generating test data and expected data. The address signal AD output from the address generator 11 includes the memory under test 20. The memory 20 to be accessed is provided to the address input terminal of < RTI ID = 0.0 >, < / RTI > and the test data signal TD is given to the accessed address by the data generator 12 to write and read.

The response output OD read out from the test memory 20 is supplied to the logic comparator 30, and is compared with the expected value data ED output from the data generator 12 in the logic comparator 30 to compare the result of the comparison (CR). ) Is output. When the comparison result indicates inconsistency, the memory under test 20 determines that it is bad. Alternatively, the comparison result CR is stored in a fail memory not shown for the poor analysis of the memory.

The passage 13 of the test data signal TD applied to the memory under test 20 by the data generator 12 and the passage of applying the expected data signal ED to the logical comparator 30 by the data generator 12. Polarity converters 15 and 16 are provided at 14. The polarity changers 15 and 16 are switched-controlled by the polarity change signal CS output from the polarity controller 40, and the polarity of the test data signal TD written in the memory under test 20 for each address area is set. It is configured to be selected.

The polarity controller 40 includes inverted region memories 41, 42, and 43 provided for recognizing the polarity inversion region of the memory under test 20, a test data signal TD and an expected data signal applied to the polarity inversion region. To an inversion data register 44 for storing inversion data for determining whether to reverse the polarity of ED) and an inversion data selector 45 for selecting and outputting inversion data stored in the inversion data register 44. It is composed by.

In this example, the address signals are the X address signal AX, the Y address signal AY, and the Z address signal AZ. These X address signals AX, the Y address signal * AY, and Z o are obtained. The dress signal AZ is divided into three inverted region memories 41, 42, and 43, and each inverted region memory 41, 42, 43 is divided into an X address signal AX, a Y address signal AY, and This is a case where the access is made by the Z address signal AZ.

For example, " 1 " logic is written in advance in the address in the polarity inversion area of the memory under test 20 of the inversion area memories 41, 42, 43. For example, for simplicity, the memory under test 20 has a capacity of 256 bits, and each memory cell has a 4-bit X address (AX = X ₀ X ₁ X ₂ X ₃ ) and a 4-bit Y address (AY = Y). ₀ Y ₁ Y ₂ Y ₃ ), and do not use the Z address. As shown in FIG. 3, the entire area of the memory 20 is divided into a polarity inversion area INV indicated by an oblique line and a non-inverted area NINV of a blank. In this case, as is apparent from the figure, the X address AX of the polarity inversion region INV is AX = ** 11, where * is represented by "0" or "1", and the Y address AY is AY = *. * 11 is displayed. Therefore, as shown in FIG. 4A, "1" is written in advance in the addresses "11" to "1111" in the X address region inversion memory 41, and in FIG. 4B in the Y address region inversion memory 42. As described above, "1" is written in advance in addresses "11" to "1111". Therefore, when the address in the polarity inversion area of the memory under test 20 is output to the address generator 11, " 1 " logic is read in each of the inversion area memories 41, 42, 43.

The data (x, y, z) read from the inversion area memories 41, 42, 43 are input to the inversion data selector 45 as a 3-bit selection signal. The inversion data selector 45 is stored in the inversion data register 44 according to the data (x, y, z) read out from the three inversion area memories 41, 42, 43, and whether or not to invert the test data signal. Select and pull out the inversion data to determine.

The inversion data register 44 can be constituted by an 8-bit register, for example, and when the selection signal xyz composed of data read from the three inversion area memories 41, 42 and 43 is 000 to 111. The inversion data selector 45 selects the first bit B ₁ to the eighth bit B ₈ of the inversion data register 44, respectively, as shown in FIG. When the memory under test 20 has the polarity inversion area INV shown in FIG. 3, the X address area inversion shown in FIGS. 4A and 4B is shown by the X address AX and the Y address AY. If at least one of the data (x, y) respectively read from the memory 41 and the Y address area inversion memory 42 is " 1 ", the memory cell designated by the X address AX and Y address AY is Since it is in the polarity inversion area INV, at least one of the bit positions of the inversion data register 44 selected by the selection signal xyz in which at least one of x and y in the selection signal xyz becomes " 1 " Please fill in in advance. As a result, for example, 0, 1, 1, 1, 0, 1, 1, 1 are written into an 8-bit register as shown in FIG. In other words, when the selection signal xyz is 000 and 001, the inverted digital data "0" of the first bit B ₁ and the fifth bit B ₅ is selected and taken out, respectively, and the inverted data is selected from the polarity changer 15, 16). In addition, the selection signal (xyz), 100, 010, 110, 101, 011, 111 when the inversion data selector 45 are each claim 2, 3, 4, 6, 7, 8-bit (B _2., B _3, The inversion data "1" of B ₄ , B ₆ and B ₈ ) is selected, and this inversion data of the "1" logic is given to the polarity changers 15 and 16.

In this example, the polarity changers 15 and 16 represent a case where an exclusive logical sum circuit is constituted, and the test data output from the data generator 12 when the inversion data of "0" logic is given to the inversion data selector 45. The signal TD and the expected value data signal ED are provided to the memory under test 20 and the comparator 30 with the same polarity without being reversed in polarity. On the other hand, if inverted data of " 1 " logic is input to the polarity changers 15 and 16, in this case, the test data signal TD and the expected value data signal ED generated by the data generator 12 are the polarity telephones 15. And 16), the polarity is reversed and applied to the memory 20 and the comparator 30 under test.

Therefore, in the above example, in the polarity inversion region INV shown in FIG. 3, the test data signal TD is inverted in logic so that writing is performed.

As apparent from the above, FIGS. 4A and 4B show data previously written to the X address region inversion memory 41 and Y address region inversion region memory 42, and / or the inversion data register shown in FIG. By changing the data to be written to (44) in advance, the area for inverting the polarity (logical) of the writing to the memory under test 20 can be changed.

In the example of the polarity inversion region (INV) shown in FIG. 3 the X address (AX = X ₀ X ₁ X ₂ X ₃₎ the upper two bits (X _2, X ₃₎ are both "1" in area and Y of The polarity inversion area (INV) is converted to the polarity inversion area in the area where the upper two bits (Y ₂ , Y ₃ ) of the address (AY = Y ₀ Y ₁ Y ₂ Y ₃ ) are both "1". It is specified by satisfying addresses AX, AY, and AZ.

1 = X ₂ X ₃ + Y ₂ Y ₃ . … … … … … … … … … … … … … … … … … (One)

However, in the conventional semiconductor test apparatus shown in FIG. 2 as represented by the example of this logical formula (1), the basic principles for specifying the polarity inversion region are X address (AX), Y address (AY), and Z address ( AZ) respectively designates the X address polarity inversion area, the Y address polarity inversion area, and the Z address polarity inversion area, respectively (for example, X ₂ X ₃ and Y ₂ Y _{3 in} logical formula (1)). Since the combination of the regions (logical sum or logical product, for example, the logical sum of X ₂ · X ₃ and Y ₂ · Y _{3 in} the above formula) is selected, the polarity inversion region that can be specified is limited to the simple one. For example, an address area whose diagonal area INV shown in FIG. 6 is a polarity inversion area is designated as an address that satisfies logical expression (2) after replacing X ₃ and Y ₂ in logical expression (1).

1 = X ₂ X ₃ + Y ₂ Y ₃ . … … … … … … … … … … … … … … … … … (2)

In the apparatus of FIG. 2, it is not possible to designate the polarity inversion region as shown in this logical formula (2). That is, the logical product between the X address (AX) and the Y address (AY), the logical product between the X address (AX) and Z address (AZ) and the logical product between the Y address (AY) and Z address (AZ). The polarity inversion region, represented by a logical expression including at least either, could not be specified except in special cases.

The inversion area memories 41, 42, and 43 have a large capacity since the bit capacity of all the address numbers determined by the address lengths (i.e., the number of bits) of the X, Y, and Z address signals AX, AY, and AZ is required. A memory of capacity is needed. For example, when each address (AX, AY, AZ) is 16 bits, 64K bits of memory are required for each (X, Y, Z) area inversion memory 41, 42, 43, respectively.

However, the Z address may not be necessary, and when used, it is often considerably shorter than the X and Y addresses.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory test apparatus for testing a memory having a polarity inversion function, wherein any shape region can be designated as an inversion region with a small amount of hardware.

According to the present invention, there is provided an address generator for generating an address signal applied to a memory under test, a data generator for generating a test data signal and an expected value data signal applied to the memory under test in synchronization with the address signal output by the address generator; A polarity inverter for matching the test data signal applied to the memory under test by the data generator to the polarity inversion area in the memory under test, and a polarity controller for providing a control signal for polarity inversion to the polarity inversion device; A memory test apparatus, comprising: a bit register circuit for storing a bit for selecting a region for inverting polarity among address signals outputted by an address generator from a polarity controller, and outputted from the address generator by bit data set in the bit register circuit; Predetermined address signal The polarity of the polarity inverter is detected by detecting that a bit selection circuit for extracting bits and an address signal in a region that is accessed by a composite address signal constituted by the bits selected by the bit selection circuit and polarity reversed to the memory under test are applied. An area inversion memory for providing an inversion signal is provided.

According to the configuration of the present invention, the bit position of the address signal which defines the polarity inverted area according to the format of the memory under test is set in the bit register circuit.

This set bit data is supplied to the bit selection circuit, and a predetermined number of bits set in the bit register circuit are extracted by this bit selection circuit, and supplied to the area inversion memory as a composite address signal. In the area inversion memory, the polarity inversion signal is written to an address corresponding to an area in which the polarity is reversed and writing is performed in the memory under test.

Therefore, according to the present invention, when the memory under test has its polarity reversed and the address area where writing and reading is performed is accessed, the polarity inversion signal is read from the area inversion memory at that time. This polarity inversion signal is applied to the polarity inversion polarity, the polarity of the data signal applied to the memory under test by the data generator is inverted, and the polarity of the data signal is inverted to write.

As described above, according to the present invention, the area inversion memory can be satisfied with a small memory since the area inversion memory is accessed by using a synthetic address signal having the minimum number of bits necessary to define the polarity inversion area of the memory under test. .

The polarity inversion signal can be generated in any address area by writing the polarity inversion signal to an arbitrary address of the area inversion memory. In addition, since there is no need to use a large memory as in the prior art, the amount of hardware can be reduced. Therefore, it is possible to obtain the advantage that it can be manufactured at low cost and that high speed processing is possible.

7 shows one embodiment of the present invention.

In FIG. 7, the same code | symbol is attached | subjected to the part corresponding to 2nd degree.

In the memory test apparatus for testing a memory having a polarity inversion function constituted by the pattern generator 10, the polarity controller 40, the polarity inverters 15 and 16, the comparator 30, and the like, in the present invention, The polarity controller 40 is constituted by the bit register circuit 46, the bit select circuit 47, and the area inversion memory 48.

The bit selection circuit 47 is inputted in parallel with all bits of the address signal (AD; X, Y, Z address AX, AY, AZ) from the address generator 11, and the desired ones of all the bits are inputted in parallel. The bits of the desired position of the number are selected and output in correspondence with the selection signal S provided by the bit register circuit 46. In the bit register circuit 46, bit data for outputting the number of selection signals S necessary for designating the bit positions to be selected in the bit selection circuit 47 are stored in advance. The composite address CA constituted by the bit selected by the bit selection circuit is given to the area inversion memory 48 and the polarity inversion control signal CS read out from the corresponding address is given to the polarity inverters 15 and 16. do.

8 shows a specific configuration example of the polarity controller 40 in FIG.

Bit select circuit 47 is pre-determined number; comprise a multiplexer (47 ₁ ~47 _n) of (n n is an integer of 2 or greater), the multiplexer (47 ₁ ~47 _n) are respectively all of the bits of the address signal (AD) Is input in parallel. The bit register circuit 46 has n registers 46 _{1 to} 46 _n , and bit selection data are stored, respectively. The bit selection data in the registers 46 _{1 to} 46 _n are applied to the selection control terminal SEL to the multiplexers 47 _{1 to} 47 _n corresponding to the selection signals S _{1 to} Sn, respectively, thereby inputting each multiplexer. The desired one bit specified in all the bits of the address AD is outputted. Wheat selected from tipeul Lexus (47 ₁ ~47 _n) outputs the n-bit data is given to the area inversion memory 48 as a composite address (CA) and the inverted control data is read out is output as the polarity inversion control signal (CS) .

In order to explain the operation of the memory test apparatus of the present invention of FIG. 7 as a simple example as in the case of FIG. 2, the memory under test 20 has a capacity having a polarity inversion region INV as shown in FIG. Use 256 bits of memory. The address AD for accessing the memory 20 is a 4-bit X address (AX = X ₀ X ₁ X ₂ X ₃ ) and a 4-bit Y address (AY = Y ₀ Y ₁ Y ₂ Y _3). ), Therefore, Z address is not used.

The polarity inversion region INV shown in FIG. 6 can be designated by all addresses satisfying the above logical formula (2). Therefore, the bits in the addresses required to designate this polarity inversion area INV are X ₂ , X ₃ , Y ₂ , and Y ₃ , and these bits are selectively output by the bit select circuit 47.

Thus, the number of portions corresponding to n showing the 4 numbered, respectively, the eighth degree of multiplexers (47 ₁ ~47 _n) and the register (46 ₁ ~46 _n) according to claim 8, also should be no. Each of the multiplexers 47 _{1 to} 47 _{n is} provided with all eight bits of the address signal AD in common, and one of them is selected, so each selection signal S _{1 to} S ₄ is composed of three bits.

Therefore, the registers 46 ₁ to _{4 4 4} are each a 3-bit register. A multiplexer (47 ₁ ~47 _4), the selection signal is specified by (S ₁ ~S _4), each bit _{(X 2, X 3, Y} 2, Y 3) for each selected output, and these bits are the address (CA) The area inversion memory 48 is provided.

As shown in FIG. 9, " 1 " is written to all addresses satisfying the logical expression (2) in the area inversion memory 48. As shown in FIG. Therefore, the bit (X ₂ , X ₃ , Y ₂ , Y ₃ ) of the 8-bit address signal (AD = X ₀ X ₁ X ₂ X ₃ Y ₀ Y ₁ Y ₂ Y ₃ ) generated by the address generator 11. If 1 satisfies the logical formula (2), " 1 " is read from the area inversion memory 48, and the read " 1 " And the logic of the expected value data signal ED are inverted and output. As a result, data is written to the polarity inversion area INV of the memory under test 20 in the same logic as that of the other areas, and inverted by the logic of the expected value data signal ED applied to the comparator 30.

Although the above example has been described with respect to the memory 20 having the polarity inversion region INV as shown in FIG. 6, the same bit as described above for the polarity inversion region INV of the memory shown in FIG. _{(X 2, X 3, Y} 2, Y 3) a multiplexer (47 ₁ ~47 ₄₎ and select the output, the composite address (CA = X ₂ X ₃ that has inverted domain memory 48 satisfy the logical expression (1) Y ₂ Y ₃ ) may be written as "1". The data written to the addresses 0000 to 1111 of the area inversion memory 48 are 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1.

For the sake of simplicity, the polarity controller 40 shown in FIG. 8 has been described in the range of n = 4 for simplicity, but the polarity inversion region of the DRAM having 16M bits and 32M bits is tested in an actual memory test apparatus. Even if it has a complex type, it is considered that there are 10 to 12 bits necessary for the logical expression to express it. Therefore, the actual value of n is selected to be about 10 to 12. Even if n = 12, the capacity required for the area inversion memory 48 is only 4K bits, which is much smaller than the dedicated amount required for the X, Y, and Z address area inversion memories in FIG.

As described above, according to the present invention, the polarity controller 40 is constituted by the bit register circuit 46, the bit selection circuit 47, and the area inversion memory 48, and the polarity selection circuit 47 uses the polarity. Since the bit necessary for the logic expression representing the inversion area can be freely selected and output from the input address, a complicated polarity inversion area can be specified. In particular, since the area reversal memories 41, 42, and 43 (refer to FIG. 2) need not be provided for each address signal AX, AY, and AZ as in the prior art, the cost can be greatly reduced.

In addition, the area reversing memories 41, 42, and 43 having large capacities do not have to be used, and the area reversing memories 48 used in the present invention can be used as small memories. Obtained.

Claims (4)

An address generator for generating an address signal to be provided to the memory under test, a data generator for generating a home data signal and an expected value data signal to be supplied to the memory under test in synchronization with the address signal output by the address generator; A polarity inversion device for polarizing the test data signal applied to the memory under test in the data generator according to the polarity inversion control signal, and a polarity controller for providing the polarity inversion control signal to the polarity inversion device; A memory test apparatus for testing a memory having a memory, wherein the polarity controller comprises: a bit register circuit for storing bit data for designating a plurality of bits required for a logic expression indicating the polarity inversion region among address signals output from the address generator; Set in the bit register circuit The polarity is accessed by a bit selection circuit for selectively outputting a designated bit among the address signals output from the address generator by bit data, and a composite address signal composed of the plurality of bits output by the bit selection circuit. And an area inversion memory for reading an inversion control signal and applying the inversion control signal to the polarity inversion. 2. The memory test apparatus according to claim 1, wherein the bit selection circuit includes a predetermined number of multiplexers, each of which the address signal is input, for selectively outputting a designated one of the address signals. 3. The memory test apparatus according to claim 1 or 2, wherein one of the polarity inversion control signals is stored in all addresses that satisfy the logic expression of the area inversion memory. The polarity inverter according to claim 1 or 2, wherein the expected value data is again provided, and another polarity inverter outputs the logic of the expected data inverted or non-inverted according to the logic of the polarity inversion control signal, and the another one. And a logic comparator configured to logically compare the output of the polarity reverse circuit and the data read from the memory under test and output a comparison result.

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