KR950000124B1 - Memory access method and data process system - Google Patents

Abstract

No content.

Description

Dynamic memory access method and data processing system construction method and data processing system

1 is a block diagram showing one embodiment of a microprocessor according to the present invention.

2 is a memory map showing an example of a state of division of an address space by an address setting register.

3 is a timing diagram showing timings of an address signal and a control signal when the dynamic RAM is accessed.

4 is a circuit diagram of an address multiplex.

5 is a circuit diagram of a control signal generation circuit.

6 and 7 are circuit diagrams of an inverter circuit and a clocked inverter circuit, respectively.

8, 9, 10 and 11 are timing diagrams of the circuits of FIGS. 4 and 5;

12 is a connection diagram of an external memory.

13 is a circuit diagram of another embodiment.

The present invention relates to a data processing technique, and furthermore, to a technique effective in application to a data processing system including a data processing apparatus (microprocessor) and a dynamic memory. In particular, the present invention relates to a data processing system including a data processing apparatus and a dynamic memory, wherein the dynamic memory access method by the data processing apparatus and the data processing apparatus make the data accessible by the data processing apparatus. The present invention relates to a valid technique applied to a method for constructing a processing system. The present invention also relates to a technique effective in application to a configuration of a data processing system including a dynamic memory of an address multiplex method and a memory of a method other than the address multiplex method (address non-multiplex method) and a data processing device. .

The microcomputer system is constituted by a microprocessor, a storage device such as a read only memory (ROM) or a random access memory (RAM), an input / output interface (I / O), or the like. In this case, there is an advantage that the system can be inexpensively configured to use a dynamic type rather than a static type as the RAM.

In addition, in the dynamic RAM, the address multiplex method is adopted, and the refresh operation is required, which makes the control more cumbersome than the ROM or the static RAM. Therefore, the conventional microprocessor was comprised so that a ROM and a static RAM could be directly accessed only. When configuring the system using the dynamic RAM, it is necessary to operate the dynamic RAM according to the clock signal or the control signal output from the microprocessor. (Low address strobe) signal or A signal indicating the refresh timing with the (Column Address Strobe) signal. Complicated external circuits, such as circuits that form a circuit board, must be prepared (see No. 6, pages 87 to 89, 1982, published by CQ Publishing Co., Ltd.).

As described above, when the dynamic RAM is used in the conventional microprocessor, the system design becomes cumbersome and the mounting area of the system becomes large.

In addition, some conventional microprocessors have a built-in refresh counter that generates a refresh address of a dynamic RAM. However, even in such a microprocessor, a RAS signal or a CAS signal must be generated by an external circuit.

It is an object of the present invention to provide a method of accessing a dynamic memory which makes it possible to appropriately access a dynamic memory used in a data processing system.

Another object of the present invention is to provide a method for constructing a data processing system so as to appropriately access a dynamic memory used in the data processing system.

It is another object of the present invention to provide a data processing system including a dynamic memory of an address multiplex method and a memory and data processing device other than the address multiplex method (address non-multiplex method), and having a reduced mounting area. It is.

The above and other objects and novel features of the present invention will become apparent from the features of this specification and the accompanying drawings.

The outline | summary of the typical thing of the invention disclosed in this application is as follows.

That is, the dynamic memory access method according to the present invention includes a write process for writing data corresponding to the capacity of the dynamic memory used in the data processing system to a register in the data processing apparatus via the data bus in the data processing apparatus. An output process of outputting the bit address controlled row address signal and column address signal to the dynamic memory in a time division manner according to the data written to the register after the write process and the row address signal controlled bit number And accessing the dynamic memory by a column address signal.

The write process executes a program in the read-only memory on the CPU to write data corresponding to the capacity of the dynamic memory used in the data processing system to a register in the data processing apparatus via the data bus in the data processing apparatus. It may be a light process.

According to the dynamic memory access method of the present invention, the data corresponding to the capacity of the dynamic memory used in the data processing system is written to a register in the data processing jack, and then bits are written according to the data written in the register. A number-controlled row address signal and a column address signal are supplied from the data processing device to the dynamic memory in a time division manner, and the dynamic memory is accessed by the data processing device.

Therefore, even when the capacity of the dynamic memory used in the data processing system is changed, it is necessary to access the changed dynamic memory by writing data corresponding to the changed memory capacity of the dynamic memory to a register in the data processing apparatus. The address output function of the data processing apparatus is changed so that the bit number of row address signals and column address signals can be output from the data processing apparatus. As a result, even if the memory capacity of the dynamic memory used in the data processing system is changed, it is possible to simply cope with the change.

Meanwhile, the method for constructing a data processing system according to the present invention is applied to a data processing system including a dynamic memory, a read-only memory, and a data processing apparatus, and resets the first bit of the register of the data processing apparatus. In response to the reset, accessing the read-only memory by a method other than the address multiplex method (address non-multiplex method) by the data processing apparatus, and accessing the read-only memory by the data processing apparatus. Supplying first data for indicating an address multiplex method from a read-only memory and second data relating to a storage capacity of a dynamic memory to an internal data bus of the data processing apparatus, the first data supplied to the internal data bus; 1 data in the register A first setting step of setting a function of the data processing apparatus so as to multiplex and output a row address signal and a column address signal to a dynamic memory by writing to the first bit, the first supply supplied to the data bus The number of bits of each of the row address signal and the column address signal output to the dynamic memory by writing the data to the second bit by the register is set in response to the second data. And a second setting step of setting the function.

According to the method for constructing the data processing system of the present invention, in constructing the data processing system, the address processing function is first set so that the data processing apparatus can first access the read-only memory of the address non-multiplex method. The address output function is set so that the dynamic memory of the address multiplex type can be accessed in accordance with the first data read from the read only memory.

Therefore, since the inexpensive general-purpose address non-multiplexed read-only memory can be used for constructing the data processing system, the cost of the data processing system itself can be reduced.

Also, by writing the second data read from the read-only memory to the internal register of the data processing apparatus, the data processing apparatus can output the row address signal and the column address signal of the number of bits necessary for accessing the dynamic memory. The address output function of the data processing apparatus is set.

Therefore, when the capacity of the dynamic memory used in the data processing system is changed, the address output function of the changed dynamic data processing apparatus outputs a row address signal and a column address signal of the number of bits necessary for accessing the changed dynamic memory. It can be set automatically as possible.

Further, the data processing system according to the present invention has a dynamic memory having an address terminal and a data terminal and accessed in an address multiplex method, and a method other than the address multiplex method with an address terminal and a data terminal (address non-multiplex method). A memory to be accessed and an external data bus coupled to a data terminal of the dynamic memory and a data bus of the memory, an external data terminal formed on a single semiconductor substrate and coupled to the external data bus and coupled to the external address bus And a data processing apparatus having an external address terminal and capable of accessing an address in an address space allocated to the dynamic memory and an address in an address space allocated to the memory. The data processing apparatus further includes an internal data bus coupled to the external data terminal, an internal address bus to which an address signal to be output to the external address bus is supplied, and an address switching circuit coupled between the address output terminal and the internal address bus. It includes.

In such a configuration, when the data processing apparatus accesses an address in the address space of the dynamic memory, the data processing apparatus transmits an address signal on the internal address bus by the address switching circuit to the first portion and the second portion. The data is divided into portions and time-divisionally outputted to the external address terminal. On the other hand, when the data processing apparatus accesses an address in the address space of the memory, the data processing apparatus outputs the address signal on the internal address bus to the external address terminal via the address switching circuit as it is.

According to the data processing system of the present invention, a dynamic memory accessed by an address multiplex method and a memory accessed by a method other than the address multiplex method have a configuration in which an external address bus and an external data bus are used in common. Therefore, since the configuration of the external address bus and the external data bus is simplified, it is possible to reduce the data processing system and facilitate the design of the data processing system.

Further, the external address bus commonly used is coupled to an external address terminal of the data processing apparatus, and the external data bus commonly used is coupled to an external data terminal of the data processing apparatus. Therefore, since the number of terminals of the external address terminal and the external data terminal of the data processing apparatus is reduced, the cost of the data processing system is also reduced.

Example 1

1 is a circuit block diagram of one embodiment in the case where the present invention is applied to a 16-bit microprocessor. In the same figure, the portion enclosed by the broken line A is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor manufacturing technique.

In Fig. 1, the circuit code CPU is a microprocessor unit. Since the CPU itself is not directly related to this microprocessor specific configuration, the details thereof are not shown, but for example, dedicated registers and work areas such as arithmetic logic units, program counters, stack pointers, and status registers. A control unit CONT comprising an execution unit EXEC consisting of a general-purpose register group used as a command, an instruction register into which microprogram instructions read from an external memory (not shown) are sequentially input, and a micro ROM in which micro instructions corresponding to each macro instruction are stored. It is composed by.

The execution unit EXEC is operated in an appropriate order determined by the control signal output from the control unit CONT. As a result, desired data processing is performed. The control unit CONT is coupled to an external terminal group CT to which an interrupt signal or reset signal is supplied.

In order to control the operation timing of the microprocessor part CPU, the oscillation circuit OSC and the clock generation circuit CPG are provided. The oscillation circuit OSC has its oscillation frequency determined by a circuit element such as a crystal oscillator or a ceramic oscillator (not shown) coupled between the external terminals XT ₁ and XT ₂ . Clock Generation Circuit The CPG oscillation circuit receives the oscillation output of the OSC and divides it appropriately to form the system clock Ø.

In this embodiment, a refresh counter RC for generating a refresh address of a dynamic RAM on the same reaction board as the microprocessor CPU, an address output from the refresh counter RC or the execution unit EXEC to the address bus line A-BUS. An address multiplexed MPX for selecting either of the two and a control signal generating circuit CSG for controlling the operation of the address multiplexed MPX are provided.

The refresh counter RC is operated by the operating clock signal Ø of the system, and is a synchronization signal indicating the timing of refreshing once every approximately 2 m seconds. Output Refresh Counter RC Asynchronous Signal An address signal for accessing each memory row of the dynamic RAM in the period of is formed. Synchronous signal Is supplied to the microprocessor CPU and the control signal generating circuit CSG.

Sync signal Is generated, the microprocessor CPU Access to the A-BUS is prohibited. A switching control signal as described in detail below is supplied to the address multiplex MPX from the control signal generation circuit CSG. By this switching control signal, the multiplex MPX selects the refresh address supplied from the refresh counter RC instead of the address signal on the address bus A-BUS. The address signal selected by the multiplex MPX is output to the external address bus A-BUSE via the address buffer A-BFF.

In addition, the synchronization signal supplied from the refresh counter RC to the control signal generation circuit CSG. Is a signal indicating the refresh timing with respect to the outside It is output as.

According to this embodiment, although not particularly limited, in order to be able to combine different types of memories at the same time with the external address terminal AT, data representing a plurality of address spaces corresponding to each memory and the attributes of each memory is stored in the microprocessor. Is set.

Although not particularly limited, the contents of the two address setting registers AR _1, AR ₂ , the address setting registers AR ₁ , AR ₂ , and the microprocessor unit CPU on the address bus A-BUS for identification of multiple address spaces. Compare with the output address, respectively, and two comparator COMP _1, COMP _2, the two comparison circuits address signal on the address bus a-bUS by a reference of the output of the COMP ₁ and COMP _2, to determine the magnitude which A judging circuit DCD for judging whether or not it is within the address range is provided. Each of the address setting registers AR ₁ and AR ₂ is controlled by a control signal outputted from the execution unit EXEC of the microprocessor unit CPU, and address data is written via the data bus D-BUS.

The data to be written to the address setting registers AR1 and AR2 is shown in the not shown ROM in the ROM whose address terminal is coupled to the external address bus line A-BUSE and whose data output terminal is coupled to the external data bus line D-BUSE. It is stored with the program to be executed by the processor. The set of data in the address setting registers AR ₁ and AR ₂ is, for example, as follows.

That is, the execution of the program for the data set is started, so that the data to be written to the register AR ₁ is read from a ROM (not shown), and is executed in the execution unit EXEC via the data buffer D-BFF and the internal data bus line D-BUS. It is written once to a working register not shown. Next, the data of the working register is output to the internal data bus D-BUS, and a control signal for writing data to the register AR ₁ from the execution unit EXEC is output. As a result, data on the data bus line D-BUS is written to the register AR ₁ . According to the same operation procedure, data is also written to the register AR ₂ .

In addition, although not particularly limited, the contents of each of the address setting registers AR ₁ and AR ₂ become readable via the data bus D-BUS.

By the data set in the two address setting registers AR ₁ and AR ₂ , the entire memory space can be divided into three. Although not particularly limited, the address data of the address setting register AR1 means the head address of the second address space in the first to third address spaces, and the address data of the address setting register AR2 means the head address of the third address space. do.

That is, the boundary between the first address space and the second address space can be identified by the data of the register AR ₁ , and the boundary between the second address space and the third address space can be identified by the data of the register AR 2. .

For example, if the address data of the address setting registers AR ₁ and AR ₂ are each " 400000 " and " B00000 " in hexadecimal, respectively, the first address space becomes an address range from " 0 " to " 3FFFFF " The address space ranges from "400000" to "AFFFFF". Likewise, the third address space is in the range of "B00000" to "FFFFFF".

The range of address data supplied from the CPU to the address bus line A-BUS is determined by the comparison circuits COMP ₁ , COMP ₂ and the determination circuit DCD.

The comparison circuit COMP ₁ compares the address data of the address bus line A-BUS with the data set in the register AR ₁ . The comparison circuit COMP ₁ outputs "1" if the address data of the address bus line A-BUS is larger than that of the register AR ₁ , and outputs "0" otherwise.

Similarly, the comparison circuit COMP ₂ outputs "1" if the address data of the address bus line A-BUS is larger than that of the register AR ₂ , and outputs "0" otherwise. In this way, the address space of the address data of the combined address bus lines A-BUS of the outputs of the comparator circuits COMP ₁ and COMP ₂ is one-to-one corresponded.

The decision circuit DCD consists essentially of a decoder which decodes the outputs of the comparison circuits COMP ₁ and COMP ₂ . The determination circuit DCD outputs three control signals indicative of the address space of the data on the address bus lines A-BUS in accordance with the outputs of the comparison circuits COMP ₁ and COMP ₂ . The output of the determination circuit DCD becomes the operation control signals of the selection circuits SEL ₁ and SEL ₂ described below.

And B _{0 to} B ₂ to which data representing attributes of a memory corresponding to the address range are written, corresponding to three address spaces or ranges divided by the address data set in the address setting registers AR ₁ and AR ₂ . The following registers (hereinafter, referred to as configuration registers) CR ₁ to CR ₃ are provided. The configuration registers CR _{1 to} CR ₃ are similar to the address setting registers AR ₁ and AR _2, and the set of data to each of them is controlled by the CPU. In other words, the data for configuration registers CR _{1 to} CR ₃ are supplied via the data bus D-BUS.

In these configuration registers CR _{1 to} CR ₃ , bits B ₀ become data corresponding to the addressing scheme of the memory to be externally connected via external bus lines A-BUSE and D-BUSE, and bits B ₁ and B ₂ are external. The data corresponds to the storage capacity of the memory to be connected.

Bit B ₀ is not particularly limited, but becomes " 1 " when the memory is an address multiplex method such as dynamic RAM, that is, a memory to which two types of address data such as row address and column address are supplied in a time division manner. When the memory is to be supplied simultaneously with two types of address data such as ROM or static RAM, the value is " 0 ".

Corresponds to four storage capacities of two bits consisting of bits B ₁ and B ₂ . For example, the combinations "0", "1", "10" and "11" of B ₁ and B ₂ correspond to storage capacities of 16k bits, 64k bits, 256k bits and 1M bits, respectively.

Here, for example, the address setting registers AR ₁ and AR ₂ are respectively set to "400000" and "B00000" in hexadecimal, and bit B ₀ of the configuration registers CR _{1 to} CR ₃ are set to "0", " Consider the case where "1" and "0" are set. Here, the bit B ₀ of "0" is "1" in that the address range of the dynamic non-type RAM, such as a ROM or the stay tick RAM as described above, and bit B ₀ means that the address range of the dynamic RAM do. Therefore, when the contents of the address setting registers AR ₁ , AR ₂ and the registers CR _{1 to} CR ₃ are set as described above, as shown in Fig. 2, the address range from the addresses "0" to "3FFFFF" The first address space or address area ASP ₁ performed in the static RAM or ROM, and the address range from address " 400000 " to " AFFFFF " becomes the second address space ASP ₂ directed to the dynamic RAM; The address range from B00000 "to" FFFFFF "becomes the third address space ASP ₃ directed to the ROM or the static RAM.

The information of each bit B ₀ of the configuration registers CR _{1 to} CR ₃ is selectively selected from the control signal generation circuit through one of the selection circuits SEL ₁ in which a switching operation therein is performed by the determination output signal of the determination circuit DCD. Supplied to CSG. That is, if the address output on the address bus A-BUS is between " 0 " and " 3FFFFF ", then the bit B of the configuration register CR ₁ by the selection circuit SEL ₁ controlled by the output of the determination circuit DCD at that time. The content of ₀ is supplied to the control signal generation circuit CSG. On the other hand, if the address on the address bus is between "400000" to "AFFFFF", the contents of bit B ₀ of configuration register CR ₂ are supplied to the control signal generation circuit CSG, and the address on the address bus is "B00000" to "FFFFFF. ", The contents of the configuration register CR ₃ are supplied to the control signal generating circuit CSG.

The address determination circuit is constituted by the determination circuit DCD, configuration registers CR _{1 to} CR _3, and the selection circuit SEL ₁ .

When the information of bit B ₀ supplied from the selection circuit SEL ₁ is " 0 ", the control signal generating circuit CSG transfers the address data A ₀ to A ₂₃ on the address bus A-BUS as it is through the address multiplex MPX. The control signal supplied to the planet is planetary and outputs it to the address multiplex MPX. On the other hand, when the information of the bit B ₀ supplied to the control scene generating circuit CSG is " 1 ", the upper bits necessary for access to the dynamic RAM among the address data output from the microprocessor CPU on the address bus A-BUS (or The signal corresponding to the lower bit) is latched by a latch circuit (not shown) in the address multiplex MPX, and the signal corresponding to the lower bit (or higher bit) of the address is left as it is. Pass it and output it as a row address signal. Subsequently, the upper bit (or lower bit) of the address already held in the latch circuit in the address multiplex MPX is sent from the address multiplex MPX to the address buffer A-BFF and output to the outside as a column address signal from the same address terminal.

As a result, when the address range of the dynamic RAM is accessed, the upper and lower bits of the address are output separately, that is, externally in an address multiplex method. In the case described above, when the low address signal is output from the address multiplex MPX, the control signal generating circuit CSG is synchronized with this and has a low level as shown in FIG. When a low address strobe signal is formed and output, and a column address signal is output from the address multiplex MPX, A (column address strobe) signal is formed and outputted.

The dynamic RAM connected to the microprocessor of this embodiment is Signal and In synchronism with the falling of the signal, the address being output at the address buffer A-BFF can be fetched and accessed, and desired data can be read.

The data bus D-BUS is connected to a data buffer D-BFF for performing data input / output between an external memory not shown and an external memory, not shown, as shown in the figure.

On the other hand, if an address signal other than the address range of the dynamic RAM is output from the microprocessor unit CPU, the address signal is simply output beyond the address multiplex MPX and output to the outside as it is.

The information of bits B1 and B2 of the configuration registers CR _{1 to} CR ₃ is sent to the control signal generation circuit CSG, one of them via the selection circuit SEL ₂ whose switching state is controlled by the output of the determination circuit DCD. When bits B ₀ of configuration registers CR _{1 to} CR ₃ are set to 1, the bits B ₁ and B ₂ are corresponding dynamic RAMs as described above, for example, if they are set to "0, 0". Indicates that the capacity of is 16k bits, and 64k bits for "0, 1" and 1M bits for "1, 0".

When the control signal generation circuit CSG is supplied with the information of bits B ₁ and B ₂ of the configuration registers CR _{1 to} CR ₃ , when it is "0, 0", 14 bits of signals on the address bus A-BUS (for example, A ₁ to A ₁₄ ) is recognized as a regular address of the dynamic RAM, and the first half (A _{8 to} A ₁₄ ) is latched among them by the address multiplex MPX, and the other half (A _{1 to} A ₇ ) is passed through as it is. Thereafter, half A _{8 to} A ₁₄ are output to the same external terminal.

When bits B ₁ and B ₂ are "0, 1", 16 bits (e.g., A _{1 to} A ₁₆ ) of signals on the address bus are recognized as regular addresses, and half of them (A _{9 to} A) are multiplexed by the multiplexed MPX. ₁₆ ) and latch the other half (A _{1 to} A ₈ ) as it is. Similarly, when bits B ₁ and B ₂ are "1, 0" and "1, 1", the 18-bit and 20-bit signals are halved, and are divided into two outputs.

The remaining bits, which are not used to access the dynamic RAM among the address signals A _{0 to} A ₂₃ output from the microprocessor unit CPU, are latched into the address multiplex MPX once, and the lower bits and the upper bits are sequentially output as described above. While being continuously output to the outside, the address decoder provided on the memory board, for example, forms a chip select signal to execute the selection of the dynamic RAM.

In this embodiment, a signal indicating information indicating whether or not the address range of the dynamic RAM supplied from the selection circuit SEL ₁ to the control signal generation circuit CSG is provided is provided. It is output as an external signal. this The signal tells whether the microprocessor is in the state of accessing the dynamic type, and at the same time, it can be used as a chip select signal of the dynamic RAM, or the ROM or static RAM can be deselected. have.

4 shows a specific circuit of the multiplex MPX. In the multiplex MPX, each input terminal is coupled to each of the address lines A _{1 to} A ₂₀ , A ₀ and A _{21 to} A ₂₃ constituting the address bus line, and each data fetch timing is controlled by the timing signal Øl. the latch circuit LT ₁ ~LT ₂₄ and the inverter circuit is composed of ⅳ ₁ ~Ⅳ _47.

In the inverter circuits IV ₁ to IV ₄₇ , IV ₁ to IV ₈ , IV _{13 to} IV ₂₇ , and IV _{38 to} IV ₄₇ are clocked inverters whose respective operations are controlled by the timing signals Ø _r0 , Ø _{c0 to} Ø _c6, and Ø _ref . It consists of a circuit.

Each clocked inverter circuit is not particularly limited, but as shown in FIG. 7, a P-channel output MOSFET Q ₃ , Q ₄ , an output terminal OUT and a ground point of the circuit connected in series between the power supply terminal V _DD and the output terminal OUT. connected in series between N-channel MOSFET Q _5, Q ₆ is composed of. MOSFET Q ₄ and Q ₅ are each gate coupled to input terminal IN, MOSFET Q ₆ has its gate coupled to control line Ø, MOSFET Q3 has its gate coupled to control line Ø exhausted from inverter circuit IV _to It is.

Each clocked inverter circuit of this configuration is operated according to the control signal supplied to the control line Ø (hereinafter referred to as control signal Ø) at a high level, and inverted with respect to the input signal supplied to the input terminal IN. The output signal of the level is output to the output terminal OUT. When the control signal Ø is at the low level, each clocked inverter circuit is latched. That is, the output of each clocked inverter circuit is maintained at the previous output level irrespective of the input signal level by a holding capacitor (not shown) consisting of stray capacitance coupled to the output terminal.

6 shows a circuit example of the inverter circuit. In FIG. 4, the clocked inverter circuits IV _{5 to} IV ₈ , IV ₁₄ , IV ₁₆ , IV ₁₈ , and IV _{22 to} IV ₂₇ can be regarded as column selection circuits, as will be apparent from the following description.

In FIG. 4, in the clocked inverter circuits IV ₃₈ to IV ₄₇ , each input terminal RA _{0 to} RA ₉ is coupled to the output terminal of the refresh counter RC of FIG.

Timing signals or control signals Ø _l , Ø _r0 , Ø _{c0 to} Ø _c6 and Ø _ref for the operation control of the multiplex MPX are generated from the control signal generation circuit CSG.

5 is a circuit diagram of a circuit of a part of the control signal generation circuit CSG.

The control signal Ø _ref supplied to the circuit of FIG. 5 is, for example, the refresh control signal output from the refresh counter RC of FIG. Is inverted by an inverter circuit.

The timing signal Ø _r0 is considered to be substantially the upper (or lower) bit select signal.

The timing signal Ø _r0 is clocked if the bit signal B ₀ output from the selection circuit SEL ₁ of FIG. 1 is "1", that is, if the bit B ₀ of the configuration register selected by the selection circuit SEL ₁ indicates the address multiplex method. In the first half period (hereinafter, referred to as a first period) in the period of the signal Ø, it is at a high level or a "1" level, and when the bit signal B ₀ is "0", the first period and a second period subsequent thereto are performed. In the high level. The timing signal Ø _r0 is also a refresh control signal. Indicates a low level, that is, a refresh operation level, the low level is set accordingly.

Although a circuit for forming such a timing signal Ø _ro is not shown, it is as follows, for example.

That is, the circuit forms a first clock signal having the first period and a second clock signal having the first and second periods by receiving the output of the clock pulse generation circuit CPG of FIG. , The bit signal B ₀ output from the selection circuit SEL ₁ , the first clock signal and the control signal A first gating circuit comprising an AND circuit for forming a logic signal of the inverted signal, an inverted signal of the bit signal B ₀ , a second clock signal, and a control signal And a second gate circuit comprising an AND circuit for forming an AND signal, and a third gate circuit for forming an OR signal of the outputs of the first and second gate circuits. Also, in the LSI technique, the AND circuit is composed of a NAND circuit and an inverter circuit, as is well known, and the OR circuit is composed of a NOR circuit and an inverter circuit.

The timing signal Ø _C0 is considered to be the lower (or higher) bit select signal. When the timing signal Ø _C0 is the high level in the second period when the bit signal B ₀ output from the selection circuit SEL ₁ of FIG. 1 is "1", the bit signal B ₀ is "0", and When the signal is at the low level ("0" level), the signal is at the "0" level or the low level accordingly.

The timing signal Ø _C0 is, for example, the first and second clock signals, the inverted signal of the bit signal B ₀ and the control signal. It consists of an AND circuit which forms an AND signal.

The method of claim 5, also, a gate circuit formed of the AND circuit G _11, if the bit signals B ₁ and B ₂ that is supplied from the SEL ₂ The selection of FIG. 1 circuit is "0", "0", i.e. bit signals B ₁ and B _If the combination of ₂ indicates a memory requiring a 14-bit address signal, such as a 16-bit memory in a 1-bit configuration, the output thereof is at " 1 " level or high level accordingly, and the gate circuit G ₁₁ is a bit signal B _{When 1} and B ₂ represent "1" and "0", i.e., a memory requiring a 16-bit address signal such as a 64-kbit memory in a 1-bit configuration, the level is "1" accordingly. Similarly, the outputs of the gate circuits G ₁₃ and G ₁₄ may represent a memory in which the bit signals B ₁ and B ₂ require an 18-bit address signal, such as a 256 K-bit memory in a 1-bit configuration, and a memory such as a 1 M-bit memory. When it is shown, each level is "1".

Since the gate circuit G ₁ composed of an AND circuit receives the output of the gate circuit G ₁₁ and the timing signal Ø _C0 , if the bit signals B ₁ and B ₂ represent a 16k bit memory, the output circuit Ø _C1 is synchronized with the timing signal Ø _C0 . This becomes the "1" level.

Since the gate circuit G ₂ receives the output of the OR gate circuit G ₇ which receives the outputs of the gate circuits G ₁₁ and G ₁₂ and the timing signal Ø _C0 , the bit signals B ₁ and B ₂ represent 16k bits and 64k bits of memory. At that time, its output Ø _C2 is brought to the "1" level in synchronization with the timing signal Ø _C0 .

Similarly, the timing signal Ø _C3 output from the gate circuit G ₃ is at " 1 " level in synchronization with the timing signal Ø _C0 if the combination of the bit signals B ₁ and B ₂ indicates 16k bits, 64k bits and 256k bits of memory. The timing signal Ø _C4 output from the gate circuit G ₄ is set to the "1" level in synchronization with the timing signal Ø _C0 when the bit signals B ₁ and B ₂ represent 64 k bits, 256 k bits, and ₁ M bit memory.

Timing signal Ø _C5 becomes "1" level in synchronism with timing signal Ø _C0 if bit signals B ₁ and B ₂ represent 256k bits and 1M bit memory, and timing signal Ø _C6 is set to bit signals B ₁ and B ₂ . If the 1M bit memory is shown, the level is set to "1" in synchronization with the timing signal Ø _C0 .

The operation of the address multiplexed MPX in FIG. 4 is as follows in response to a timing signal output from the control signal generation circuit CSG in FIG.

8 shows a timing diagram when 16k-bit DRAM is accessed. When 16k bit DRAM is used, the outputs a _{1 to a 7} of the multiplex MPX are supplied to the address terminals of such DRAM via the address buffer A-BFF and the external bus line A-BUSE in FIG. The circuit operation will be described below using the timing diagram of FIG.

The timing signal Ø ₁ for the latch circuits LT _{1 to} LT ₂₄ goes high in synchronism with the time when the address signal is supplied to the address bus lines A-BUS.

The latch circuit LT ₁ ~ LT ₂₄ is a timing signal such a timing signal Ø _l timing signal Ø _r0 is the person that therefore, one degree control signal generation circuit CSG bit signal B ₀ is "1" is supplied to the eighth degree a to As shown in the figure, the level becomes high during the period of time t _{0 to} t ₁ .

The clocked inverter circuits IV _{1 to} IV ₄ and IV _{19 to} IV ₂₁ shown in FIG. 4 are brought into an operating state when the timing signal Ø _r0 goes high. Accordingly, the outputs a _{1 to a 4} and a _{5 to a 7} of the multiplexed MPX are at levels corresponding to the address signals A _{1 to} A ₇ of the address bus lines A-BUS, respectively, as shown in FIG. 8F. do.

As shown in Fig. 8B, the timing signal Ø _C0 goes high in synchronization with the timing at which the timing signal Ø _r0 goes low.

The timing signals Ø _{C1 to} Ø _C3 are the bit signals B ₁ and B ₂ supplied to the control signal generation circuit CSG of FIG. 1 to become "0" and "0" representing 16k bit memory, as shown in FIG. 8D. The high level is synchronized with the timing signal Ø _C0 . The remaining timing signals Ø _{C4 to} Ø _C6 become low level irrespective of the timing signal Ø _C0 as shown in FIG. 8E.

The clocked inverter circuits IV _{5 to} IV ₈ of FIG. ₄ are operated by the timing signal Ø _C0 being high level, and the clocked inverter circuits IV ₁₄ , IV ₁₆ and IV ₁₈ are the timing signals Ø _C1 , Ø _C2. And Ø _C3 goes to the high level to enter the operating state.

Therefore, the respective levels of the outputs a _{1 to a 4} of the multiplex MPX are determined by the inverter circuits IV ₅ to IV ₈ . Similarly, each level of the outputs a ₅ to a ₇ is to be determined by the inverter circuits IV ₁₄ , IV ₁₆ and IV ₁₈ .

Since the inputs of the inverter circuits IV _{5 to} IV _{8 and} the inputs of IV ₁₄ , IV ₁₆ and IV ₁₈ are coupled to the latch circuits LT _{5 to} LT ₈ , LT ₉ , LT ₁₀ and LT ₁₁ , respectively, the output a ₁ of the multiplexed MPX. ˜a ₄ and a _{5 to a 7 correspond} to the address signals A _{11 to} A ₁₄ , A ₈ , A ₉ and A ₁₀ as shown in FIG. 8F as the timing signals Ø _{C0 to} Ø _C3 become high levels. The corresponding level is reached.

In addition, the timing signals Ø _r0 for the clocked inverter circuits IV _{1 to} IV ₄ and IV _{19 to} IV ₂₁ are clocked inverter circuits IV _{5 to} IV ₈ , IV ₁₄ , IV _16, and IV as shown in FIG. 8A. ₁₈ is at a low level in synchronization with the timing at which it is operated. Therefore, inverter circuits IV _{1 to} IV ₄ and IV _{19 to} IV ₂₁ do not affect the output levels of inverter circuits IV _{5 to} IV ₈ , IV ₁₄ , IV ₁₆ and IV ₁₈ .

By the above operation, the outputs a ₁ to a ₇ determined at time t ₀ become row address signals for 16k-bit DRAM, and the outputs a ₁ to a ₇ determined at time t ₁ become column address signals.

In addition, the outputs a _{1 to a 7} are equal to the stray capacitance present at each output even when the clocked inverter circuit IV ₅ becomes inoperative by the timing signals Ø _{C0 to} Ø _C3 returning from the high level to the low level. It is maintained at the previous level by the holding capacity. The outputs a _{1 to a 7} are updated by the timing signal Ø _r0 becoming high again.

As for the outputs a ₀ and a _{15 to a 23 where} no address multiplex is needed, each level is determined at time t ₀ as shown in FIG. 8G. That is, the outputs a ₀ and a _{15 to a 23} are the static inverter circuits IV ₃₄ , IV _{28 to} IV _33, and IV _{35 to} IV ₃₇ that receive the outputs of the latch circuits LT ₂₁ , LT _{15 to} LT _20, and LT _{22 to} LT ₂₄ . Each level is determined by.

In particular, but not limited to, output a ₈ ~a ₁₄ is in each of the corresponding level to the address signals a ₈ ~a ₁₄ at time t _0. Output a ₈ ~a ₁₄ is may be not supplied to the address input terminal of the 16k bit DRAM, is maintained at a level corresponding to the address signals A ₈ ~A _16.

In the case of the configuration of FIG. 4, the address signals A _{8 to} A ₁₄ are supplied to the outputs a ₁ to a ₇ after the respective positions are appropriately changed in order to simplify the circuit configuration. That is, for example, the address signal A ₈ is supplied to a ₅ , not the output a ₁ . The address signal A ₉ is supplied to a ₆ , not to the output a ₂ (not shown). However, this kind of change only means that the correspondence between the logical address indicated by the address signals A _{1 to} A ₁₄ and the physical address of the ERAM is changed.

9 shows a timing diagram when a 64k bit DRAM is accessed.

In this case, the timing signals Ø _C1 , Ø _C5 , and Ø _C6 are the timing signals Ø _C0 (ninth b) as the bit signals B ₁ and B ₂ are "1" and "0" (FIG. 9 c and d). Regardless of Fig.), They are kept at a low level, respectively, as shown in Figs. 9E and 9H. The timing signals Ø _C2 , Ø _C3 and Ø _C4 go high in synchronization with the timing signal Ø _C0 , as shown in FIGS. 9F and 9G.

As shown in FIG. 9i, the outputs a _{1 to a 8} of the multiplexed MPX become levels corresponding to the address signals A _{1 to} A ₈ as the timing signal Ø _r0 becomes high at time t ₀ . At the time t ₁ , the timing signals Ø _C0 and Ø _{C2 to} Ø _C4 become high levels, corresponding to the address signals A _{9 to} A ₁₆ .

Outputs a ₀ and a ₁₇ ~a ₂₃ is in, the level corresponding to the address signals A ₀ and A ₁₇ ~A ₂₃ as is illustrated in Fig. 9j.

10 shows a timing diagram during the refresh operation.

In this case, the timing signals Ø _r0 and Ø _C0 are kept at a low level, as shown in Figs. 10A and 10B. The clocked inverter circuits IV _{1 to} IV ₈ and IV _{13 to} IV ₂₇ coupled to the latch circuit of FIG. ₄ are in an inoperative state.

Refresh control signal at time t ₀ Ø _ref is when the high level as shown in the Figure 10c, it is therefore the degree to four clock Fig inverter circuit Ⅳ ₃₈ ~Ⅳ ₄₇ the operating state. As a result, the outputs a _{1 to a 10} of the multiplexed MPX become levels corresponding to the address signals RA ₀ to RA ₉ output from the refresh counter RC of FIG. 1 as shown in FIG. 10D. If the DRAM (not shown) coupled to the external busline A-BUSE of FIG. 1 is a 16k-bit DRAM requiring a 7-bit row address signal, the DRAM is caused by a ₁ to a ₇ of the outputs a ₁ to a ₁₀ . It works. Similarly, when a DRAM, not shown, requires a row address signal of 8, 9 or 10 bits, the DRAM is operated by outputs a _{1 to a 8} , a _{1 to a 9} or a _{1 to a 12} .

FIG. 11 shows a timing diagram when an SRAM or a ROM is accessed rather than the address multiplex method.

In this case, the timing signals Ø _C0 and Ø _{C1 to} Ø _C6 are kept at a low level as shown in Figs. 11B and 11C, respectively.

The output of the multiplex MPX a ₀ ~a _23, as shown in the Fig. 11d, the timing signal Ø When _r0 to the high level (Fig. 11a claim) according to the time t _0, therefore address signals A ₀ ~A ₂₃ The corresponding level is reached. As a result, the SRAM or ROM is accessed.

12 is a connection diagram of an external memory. Although not particularly limited, the external memories DM ₁ and DM ₂ include address terminals A _{0 to} A ₇ , data output terminals D out, and column address strobe terminals. , Reference potential terminal (earth terminal) V _SS , refresh control terminal Data input terminal Din, light enable terminal , Row address strobe terminal And a 64k-bit dynamic RAM having a power supply terminal V _CC . Memory DM ₁ and DM ₂ has the input and output of data of one bit is enabled. In this case, multiple inputs and outputs of multiple bits of data are required at the same time.

In the same figure, the external address bus A-BUSE is coupled to the external address terminal AT of FIG. 1, and the external data bus D-BUSE is coupled to the external data terminal DT of FIG.

Decoder DEC is a 1-bit address signal and terminal of FIG. 1 supplied via an external address bus A-BUSE. The row address strobe signal to be supplied to the memories DM ₁ and DM ₂ by the row address strobe signal supplied via To form.

The address terminals A _{0 to} A ₇ of the memories DM ₁ and DM ₂ are provided with a common address signal via an external address bus A-BUSE.

By this, the memory DM ₁ is a signal And the address signals applied to the address terminals A _{0 to} A ₇ , and likewise, the memory DM ₂ is a signal. And the signals of the address terminals A _{0 to} A ₇ .

Column address strobe terminals of memory DM ₁ and DM ₂ , Refresh control terminal And light enable terminals Are the terminals of Fig. 1, respectively. And Common connection to

The data output terminals D out of the memories DM ₁ and DM ₂ are commonly connected to the input terminals of the bus driver TSC, and the data input terminals D in are connected to the external data bus D-BUSE together with the output terminals of the bus driver TSC.

The bus driver TSC consists of a three-state circuit and the lead control signal supplied to it. When is low level, the output signal of the level corresponding to the input signal supplied to its input terminal is output to its output terminal. Output of bus driver TSC signal If is high level, high impedance state is obtained.

According to this embodiment, when the refresh counter RC is built in the microprocessor as shown in the first diagram, and the refresh address of the refresh counter RC is output to the outside, a signal indicating the timing is output. Is output. Therefore, it is not necessary to configure the complicated refresh control circuit which forms the refresh signal of the dynamic RAM with an external circuit.

In addition, a register for setting an address range of the dynamic RAM is provided inside the microprocessor of this embodiment, and the address is automatically multiplexed inside the chip when the address of the dynamic RAM is accessed.

Therefore, even when the system is formed by mixing the static RAM and the dynamic RAM, the dynamic RAM can be accessed as easily as the static RAM without providing any externally attached circuits.

In that case, the read control signal output from the microprocessor unit CPU And light control signal This performs read and write control of the dynamic RAM.

In the above embodiment, by resetting bit B ₀ of the configuration registers CR _{1 to} CR ₃ to "0" in the reset state, first executing the program in the ROM in the ROM access state, It is common to use the setting of the address setting registers AR ₁ and AR ₂ according to the system configuration.

However, it is also possible to change the address range of the dynamic RAM by changing the setting values of the address setting registers AR ₁ and AR ₂ during the program.

This makes it possible, for example, to construct a system in which the address area of the ROM and the address area of the dynamic RAM are overlapped, and use the ROM or use the RAM as an area if necessary. In addition, each address space set by the address setting registers AR ₁ and AR ₂ may correspond to various kinds of memories. For example, a ROM and a static RAM having the same addressing scheme may correspond to one address space. In this case, one partial address space in one address space corresponds to ROM, and the other partial address space corresponds to static RAM.

In the above embodiment, since the configuration registers CR _{1 to} CR ₃ are provided with bits B ₁ and B ₂ indicating the capacity of the dynamic RAM, the system can be configured using RAM having an arbitrary capacity of 16 k to ₁ M bits. have. However, the bits B ₁ and B ₂ of the configuration registers CR _{1 to} CR ₃ indicating the capacity of the dynamic RAM are not limited to two as in the above embodiment, but may be provided in one or three or more bits.

Similarly, the bit B ₀ indicating information of whether or not the address range of the dynamic RAM may be set to 2 bits instead of 1 bit so as to be able to distinguish between the address ranges of the ROM and the static RAM. In addition, bits responsible for the information other than the above in the configuration registers CR _{1 to} CR ₃ (for example, bits indicating whether the corresponding address area is read only or read / write, bits indicating whether it is a program or data, system area or user). Or a bit indicating whether or not it is an area.

In the above embodiment, two address setting registers are provided so that an address space having a microprocessor can be divided into three. However, the number of registers is not limited to two, but one or three or more may be provided.

In the above embodiment, the present invention has been described in the application to a 16-bit microprocessor, but the present invention can also be applied to an 8-bit microprocessor.

Example 2

13 is a circuit diagram of a part of the address multiplex MPX and the control signal generation circuit CSG of another embodiment.

In this embodiment, the timing signals Ø _r0 , Ø _C0 , Ø _re in the control signal generation circuit CSG become the same as those of the above embodiment.

In the control signal generation circuit CSG, the inverter circuit IV ₄₅ and the AND gate circuit G ₁ are composed of one bit when the bit signals B ₁ and B ₂ are "1" and "0", that is, the bit signals B ₁ and B ₂ are one bit. A decoder that forms a high level output signal when the same memory as the 64k bit memory is represented.

The high level is maintained regardless of the timing signal Ø _r0 output from the OR gate circuit G ₂ .

The timing signal Ør1 output from the OR gate circuit G ₆ becomes a high level in synchronism with the timing signal Ø _ro when the bit signals B1 and B2 represent the 64K bit memory, and the bit signals B ₁ and B ₂ represent the 64K bit memory. Otherwise, the timing signal Ø _r2 indicates that when the bit signals B ₁ and B ₂ are "0" and "1", that is, if the bit signals B ₁ and B ₂ represent the same memory as the 256k bit memory of 1 bit configuration, The high level is synchronized with the timing signal Ø _r0 , otherwise the high level is maintained regardless of the timing signal Ø _ro .

Similarly, OR gate circuit timing signal output from the G ₁₀ Ø _r3 is the beat signal B ₁ and B ₂ is "1" and "1" point, i.e. bit signals B ₁ and B ₂ are 1M bit of one-bit configuration, the memory and If the same memory is indicated, the high level is synchronized with the timing signal Ø _ro , otherwise, the high level is maintained.

The timing signal Ø _C1 output from the AND gate circuit G ₄ becomes a high level only when the bit signals B ₁ and B ₂ represent a 64k bit memory and the timing signal Ø _C0 goes high.

Similarly, the timing signal Ø _C2 output from the AND gate circuit G ₈ becomes a high level only when the bit signals B ₁ and B ₂ represent a 256k bit memory and the timing signal Ø _C0 goes high. The timing signal Ø _C3 becomes a high level only when the bit signals B ₁ and B ₂ represent a ₁ M bit memory and the timing signal Ø _C0 goes high.

In the multiplexed MPX, the clocked inverter circuits IV _{0 to} IV ₆ , IV _{24 to} IV ₃₀ , IV ₁₄ , which receive respective address signals A _{0 to} A ₂₃ of the address bus lines A-BUS shown in FIG. _{ⅳ 31, ⅳ 16, ⅳ 32} , ⅳ 18 ⅳ and _33, the inverter circuit _{ⅳ 7 ~Ⅳ 13, ⅳ 15,} ⅳ 17, ⅳ 19 ~Ⅳ 23 and a first-degree output of the refresh counter RC to the respective input terminals RA ₀ And a clocked inverter circuit IV _{34 to} IV ₄₃ which receives -RA ₉ .

According to this embodiment, when DRAMs requiring row and column address signals of seven bits are used, address signals A _{0 to} A ₆ are regarded as row address signals, and address signals A _{7 to} A ₁₃ are column addresses. Is considered a signal. In this case, outputs a _{0 to a 6} of the multiplex MPX are supplied to an address terminal of the DRAM.

Output a ₀ ~a ₆ is a timing signal Ø _r0 is set to high level when the inverter according Ⅳ ₀ ~Ⅳ ₆ is because the operating condition on it, and to a level corresponding to the address signals A ₀ ~A _6, the timing signal Ø _C0 is high When the level is reached, the inverter circuits IV _{24 to} IV ₃₀ are in operation, and therefore the level corresponding to the address signals A _{7 to} A ₁₃ is reached. At this time, the outputs a _{7 to a 23} are at levels corresponding to the address signals A _{7 to} A ₂₃ , respectively. That is, for example, the levels of the outputs a _{7 to a 13} are determined by the static inverter circuits IV _{7 to} IV ₁₃ . Ⅳ inverter circuits _{14, 16} and the like Ⅳ _r1 timing signal Ø, Ø _2, etc. Since the other level remains high regardless of the timing signal Ø _r0 is placed into an operating state. Therefore, the outputs a ₁₄ , a ₁₆ , and the like become levels corresponding to the address signals A ₁₄ , A _16, and the like.

When DRAMs requiring row and column address signals by 8 bits are used, address signals A _{0 to} A ₆ , and A ₁₄ are considered to be low row address signals, and A _{7 to} A ₁₃ and A ₁₅ are column address signals. Is considered. The address signals A _{7 to} A ₁₃ and A ₁₅ are supplied to the outputs a _{0 to a 6} and a ₁₄ at the timing of the timing signal Ø _C0 . Therefore, the outputs a _{0 to a 6} and a ₁₄ are supplied to the address input terminal of the DRAM via the address buffer A-BFF in FIG.

When DRAMs requiring row and column address signals of nine bits are used, address signals A _{0 to} A ₆ , A ₁₄ and A ₁₆ are regarded as row address signals, and address signals A _{7 to} A ₁₃ and A ₁₅ And A ₁₇ are regarded as column address signals. The address signals A _{0 to} A _6, A ₁₅ and A ₁₇ are supplied to the outputs a _{0 to a 6} , a ₁₄ , a ₁₆ and a ₁₈ at the timing of the timing signal Ø _C0 . Therefore, the outputs a _{0 to a 6} , a ₁₄ and a ₁₆ are supplied to the address terminals of the DRAM.

When DRAMs requiring 10-bit row and column address signals are used, address signals A _{0 to} A ₆ , A ₁₄ , A ₁₆ , and A ₁₈ are regarded as row address signals, and address signals A _{7 to} A ₁₃ , A ₁₅ , A ₁₇ and A ₁₉ are considered to be column address signals. The address signals A _{7 to} A ₁₃ , A ₁₅ , A ₁₇ and A ₁₉ are supplied to the outputs a _{0 to a 6} , a ₁₄ , a ₁₆ and a ₁₈ at the timing of the timing signal Ø _C0 . Therefore, the outputs a _{0 to a 6} , a ₁₄ , a ₁₆ and a ₁₈ are supplied to the address input / output terminals of the DRAM.

As for the refresh operation timing, the timing signals Ø _r0 and Ø _C0 become low level and the refresh control signal Ø _ref becomes high level similarly to the above embodiment. This Ⅳ to claim 13 degrees clocked inverter circuit ₃₄ according ~Ⅳ ₄₃ is an operating state, a first-degree output of the refresh counter RC RA ₀ ~RA ₉ through the inverter circuit ₃₄ Ⅳ ~Ⅳ ₄₃ outputs a ₀ ~a ₆ , a ₁₄ , a ₁₆ and a ₁₈ .

When the SRAM or ROM is to be accessed, the timing signal Ø _C0 in the circuit of FIG. 13 is kept at the low level as in the above embodiment. The timing signals Ø _{C1 to} Ø _C3 are kept at a low level in accordance with the timing signal Ø _C0 . As a result, the column selection circuits, i.e., the clocked inverter circuits IV _{24 to} IV ₃₀ and IV _{31 to} IV _33, are placed in an inoperative state. The outputs a _{0 to a 23} become levels corresponding to the address signals A _{0 to} A ₂₃ in synchronization with the timing signal Ø _r0 .

In the multiplex of the configuration of FIG. 13, the clocked inverter circuit in which each output terminal is commonly connected to each other in order to form one output is reduced to three.

According to the present invention, the following effects can be obtained.

(1) According to the dynamic memory access method of the present invention, data corresponding to the capacity of the dynamic memory used in the data processing system is written to a register in the data processing apparatus, and then bits are written according to the data written in the register. The number-controlled row address and column address signals are supplied from the data processing apparatus to the dynamic memory in a time division manner, and the dynamic memory is accessed by the data processing apparatus.

Therefore, even when the capacity of the dynamic memory used in the data processing system is changed, the bit required for access to the changed dynamic memory by writing data corresponding to the changed memory capacity of the dynamic memory to a register in the data processing apparatus. The address output function of the data processing apparatus is changed so that a number of row address signals and column address signals can be output from the data processing apparatus. As a result, even if the memory capacity of the dynamic memory used in the data processing system is changed, it is possible to simply cope with the change.

(2) According to the method for constructing the data processing system of the present invention, in the construction of the data processing system, the address processing function is first set so that the data processing apparatus can first access the read-only memory of the address non-multiplex method. Then, its output function is set so that the dynamic memory of the address multiplex method can be accessed in accordance with the first data read from the read-only memory.

Therefore, since the inexpensive general-purpose address non-multiplexed read-only memory can be used for constructing the data processing system, the cost of the data processing system itself can be reduced.

Also, by writing the second data read from the read-only memory to an internal register of the data processing apparatus, the row address signal and the column address signal of the number of bits necessary for accessing the dynamic memory can be outputted from the data processing apparatus. The address output function of the data processing apparatus is set.

Therefore, when the capacity of the dynamic memory used in the data processing system is changed, the address output of the data processing apparatus is stored in advance by storing the second data corresponding to the memory capacity of the changed dynamic memory in the read-only memory in advance. The function can automatically set the row address signal and the column address signal of the number of bits necessary for accessing the changed dynamic memory thereof to be outputable.

(3) According to the data processing system of the present invention, the dynamic memory accessed by the address multiplex method and the memory accessed by the method other than the address multiplex method have a configuration in which the external address bus and the external data bus are used in common. Therefore, the configuration of the external address bus and the external data bus is simplified, thereby reducing the cost of the data processing system and facilitating the design of the data processing system.

Further, the external address bus commonly used is coupled to an external address terminal of the data processing apparatus, and the external data bus commonly used is coupled to an external data terminal of the data processing apparatus. Therefore, since the number of terminals of the external address terminal and the external data terminal of the data processing apparatus is reduced, the chip area of the data processing apparatus is reduced. As a result, the cost of the data processing apparatus itself is also reduced, and the cost of the data processing system is also reduced.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the Example, this invention is not limited to the said Example, Of course, it can change variously in the range which does not deviate from the summary. For example, in the above embodiment, the address range of the dynamic RAM is variable by registers. However, it is also possible to provide means for generating a fixed address instead of registers and to fix the division of the address space.

Also, the configuration registers CR _{1 to} CR ₃ themselves are omitted, and the memory of the address range divided by the address setting registers AR ₁ and AR ₂ belongs to the memory of the judging circuit DCD. May be operated.

In the above description, the invention made mainly by the present inventors has been described in application to a single-chip microprocessor, which is the background of use, but is not limited thereto, and can be used in the case of constituting a multi-chip microprocessor.

Claims (27)

The number of bits is controlled in accordance with the write process for writing data corresponding to the capacity of the dynamic memory to be used to a register in the data processing apparatus via the data bus in the data processing apparatus, and after the write process, the data written to the register. An output process of outputting the row address signal and the column address signal from the data processing apparatus to the dynamic memory in a time division manner; and accessing the dynamic memory by the row address signal and the column address signal whose bit number is controlled. Access method of a dynamic memory including a. The method of claim 1, wherein the write process is executed by a CPU. The method of claim 2, wherein the CPU is provided inside the data processing apparatus. 4. The method of claim 3, wherein the data processing device is formed on a single semiconductor substrate. 2. A method according to claim 1, wherein said output process is performed by an address switching circuit in said data processing apparatus. A method of accessing a dynamic memory coupled to a data processing device, comprising: executing a program in read-only memory on a CPU to write data corresponding to the capacity of the dynamic memory to be used in a register in the data processing device. An output step of outputting from the data processing apparatus to the dynamic memory in a time-division manner a bit number controlled row address signal and a column address signal according to the data written to the register after the write step and the write step; And accessing the used dynamic memory by a controlled row address signal and a column address signal. 7. The method of claim 6, wherein the write process includes a step of reading the data from the read-only memory. 8. The method of claim 7, wherein the write process includes supplying the data to the register via a data bus in the data processing device. The method of claim 8, wherein the CPU is provided inside the data processing apparatus. 10. The method of claim 9, wherein the data processing device is formed on a single semiconductor substrate. 7. A method according to claim 6, wherein said output process is performed by an address switching circuit in said data processing apparatus. A dynamic memory accessed by the address multiplex method, accessed by a method other than the address multiplex method, and further storing first data for indicating the address multiplex method and second data about the capacity of the dynamic memory. A method of constructing a data processing system capable of accessing the dynamic memory by the data processing apparatus in a data processing system comprising a read only memory, the dynamic memory and a data processing apparatus coupled to the read only memory. And resetting the first bit of a register of the data processing apparatus and accessing the read-only memory in a manner other than the address multiplex method by the data processing apparatus in response to the reset. Supplying the first data and the second data to the data bus of the data processing apparatus in the read only memory by accessing the read only memory at The first setting step of setting the function of the data processing device to multiplex and output a row address signal and a column address signal to the dynamic memory by writing to the first bit of the register, to the data bus. By writing to the second bit of the supplied second data the register so that the number of bits of each of the row address signal and the column address signal output to the dynamic memory is set in response to the second data; Setting the function of the data processing apparatus How to build a data processing system comprising a second setting step. 13. The method of claim 12, wherein said first and second setting steps are executed by a CPU. The method of claim 13, wherein the CPU is provided inside the data processing apparatus. 15. The method of claim 14, wherein said data processing device is formed on a single semiconductor substrate. A dynamic memory having an address terminal and a data terminal and accessed in an address multiplex manner, a memory having an address terminal and a data terminal and accessed in a manner other than the address multiplex method, an address terminal of the dynamic memory and the memory An external address bus coupled to an address terminal, an external data bus coupled to a data terminal of the dynamic memory and a data terminal of the memory, an external data terminal formed on a single semiconductor substrate, coupled to the external data bus, and And a data processing apparatus having an external address terminal coupled to an external address bus and capable of accessing an address in an address space allocated to the dynamic memory and an address in an address space allocated to the memory. An internal data bus coupled to the external data terminal, an internal address bus to which an address signal to be output to the external address bus is supplied, and an address switching circuit coupled between the address output terminal and the internal address bus, the data When the processing apparatus accesses an address in the address space of the dynamic memory, the data processing apparatus divides the address signal on the internal address bus into a first portion and a second portion by the address switching circuit to time-divisionally When outputting to an external address terminal and the data processing device accesses an address in the address space of the memory, the data processing device transfers the address signal on the internal address bus as it is via the address switching circuit to the external address. A data processing system for outputting to the terminal. 17. An address determination circuit according to claim 16, wherein said data processing apparatus responds to an address determination circuit and an output signal of said address determination circuit for determining whether an address signal on said internal address bus represents an address in an address space allocated to said dynamic memory; And further including a control circuit for controlling the address switching circuit, when it is determined by the address determination circuit that the address signal on the internal address bus indicates an address in an address space allocated to the dynamic memory. And a control circuit controls the address switching circuit so that an address signal on the internal address bus is divided into a first portion and a second portion and output time-divisionally to the external address terminal. 18. The data processing system of claim 17, wherein the first portion is a row address signal of a dynamic memory and the second portion is a column address signal of a dynamic memory. 19. The apparatus of claim 18, wherein the data processing device further comprises a register coupled to the internal data bus, wherein data corresponding to the capacity of the dynamic memory is written in the internal data bus, and the control circuitry is configured to the register. And the number of bits of each of the row address signal and the column address signal supplied to the dynamic memory are set in accordance with the data written to the register in response to the written data. 19. The apparatus of claim 18, wherein the data processing apparatus is coupled to a control signal generation circuit for generating a row address strobe signal and a column address strobe signal, the dynamic memory, and outputs the row address strobe signal to the dynamic memory. An external terminal coupled to an external terminal and the dynamic memory, for outputting the column address strobe signal to the dynamic memory, wherein the data processing device accesses an address in an address space allocated to the dynamic memory; The control signal generating circuit outputs the row address strobe signal in synchronization with the output of the row address signal and simultaneously outputs the column address strobe signal in synchronization with the output of the column address strobe signal. Get processing system. 19. The data processing system according to claim 18, wherein said data processing apparatus further comprises means for forming refresh information for instructing a refresh operation of a dynamic memory. 17. The data processing system of claim 16, wherein the data processing apparatus further includes a CPU coupled to the internal address bus and the internal data bus, wherein the CPU outputs an address signal to the internal address bus. 17. The apparatus of claim 16, wherein the first portion is a row address signal of a dynamic memory, the second portion is a column address signal of a dynamic memory, and the data processing device is coupled to the internal data bus. And a control circuit for controlling the address switching circuit in response to the data written in the internal data bus and the data corresponding to the capacity of the dynamic memory, and the data supplied to the dynamic memory. And the number of bits of each of the row address signal and the column address signal is set in accordance with the data written to the register. 24. The apparatus of claim 23, wherein the data processing apparatus further includes a CPU coupled to the internal address bus and the internal data bus, the CPU outputs an address signal to the internal address bus, and the CPU outputs the data to the internal address bus. Data processing system that writes to registers. 25. The apparatus of claim 24, wherein the data processing apparatus is coupled to a control signal generation circuit for generating a row address strobe signal and a column address strobe signal, the dynamic memory, and outputs the row address strobe signal to the dynamic memory. And an external terminal coupled to an external terminal and the dynamic memory, for outputting the column address strobe signal to the dynamic memory, wherein the data processing device accesses an address in an address space allocated to the dynamic memory. The control signal generating circuit outputs the row address strobe signal in synchronization with the output of the row address signal and simultaneously outputs the column address strobe signal in synchronization with the output of the column address signal. System. 17. The data processing system of claim 16, wherein the memory is a read only memory. 17. The data processing system of claim 16, wherein the memory is a static memory.