KR940023290U - Video memory access control circuit - Google Patents

Video memory access control circuit

Info

Publication number
KR940023290U
KR940023290U KR2019930003028U KR930003028U KR940023290U KR 940023290 U KR940023290 U KR 940023290U KR 2019930003028 U KR2019930003028 U KR 2019930003028U KR 930003028 U KR930003028 U KR 930003028U KR 940023290 U KR940023290 U KR 940023290U
Authority
KR
South Korea
Prior art keywords
control circuit
access control
memory access
video memory
video
Prior art date
Application number
KR2019930003028U
Other languages
Korean (ko)
Other versions
KR950006177Y1 (en
Inventor
문병도
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019930003028U priority Critical patent/KR950006177Y1/en
Publication of KR940023290U publication Critical patent/KR940023290U/en
Application granted granted Critical
Publication of KR950006177Y1 publication Critical patent/KR950006177Y1/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)
KR2019930003028U 1993-03-03 1993-03-03 Video memory access control circuit KR950006177Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019930003028U KR950006177Y1 (en) 1993-03-03 1993-03-03 Video memory access control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019930003028U KR950006177Y1 (en) 1993-03-03 1993-03-03 Video memory access control circuit

Publications (2)

Publication Number Publication Date
KR940023290U true KR940023290U (en) 1994-10-22
KR950006177Y1 KR950006177Y1 (en) 1995-08-04

Family

ID=19351479

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019930003028U KR950006177Y1 (en) 1993-03-03 1993-03-03 Video memory access control circuit

Country Status (1)

Country Link
KR (1) KR950006177Y1 (en)

Also Published As

Publication number Publication date
KR950006177Y1 (en) 1995-08-04

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