KR940023007A - Feed-Forward Linearization Circuit of Power Amplifiers - Google Patents

Feed-Forward Linearization Circuit of Power Amplifiers Download PDF

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Publication number
KR940023007A
KR940023007A KR1019930004882A KR930004882A KR940023007A KR 940023007 A KR940023007 A KR 940023007A KR 1019930004882 A KR1019930004882 A KR 1019930004882A KR 930004882 A KR930004882 A KR 930004882A KR 940023007 A KR940023007 A KR 940023007A
Authority
KR
South Korea
Prior art keywords
signal
adjusting
adjusted
phase
phase shifter
Prior art date
Application number
KR1019930004882A
Other languages
Korean (ko)
Other versions
KR950003278B1 (en
Inventor
박종호
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930004882A priority Critical patent/KR950003278B1/en
Publication of KR940023007A publication Critical patent/KR940023007A/en
Application granted granted Critical
Publication of KR950003278B1 publication Critical patent/KR950003278B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
    • H03F1/3229—Modifications of amplifiers to reduce non-linear distortion using feed-forward using a loop for error extraction and another loop for error subtraction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
    • H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
    • H03F2201/3218—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion the main amplifier or error amplifier being a feedforward amplifier

Abstract

본 발명은 전력증폭기의 피드 포워드 선형화 회로에 관한 것으로, 이는 원신호 경로외에 왜곡신호 경로를 통해 처리한 후, 다시 원신호와 결합시켜 출력신호의 상호 변조잡음 성분을 감소시킴으로써, 디지탈 셀룰라 또는 개인 통신망과 같은 디지탈 통신 시스템에서 사용하는 전력증폭기의 선형화를 이룰 수 있게 한 것이다.The present invention relates to a feed forward linearization circuit of a power amplifier, which is processed through a distortion signal path in addition to the original signal path, and then combined with the original signal to reduce the intermodulation noise component of the output signal. The linearization of power amplifiers used in digital communication systems such as

Description

전력증폭기의 피드 포워드 선형화 회로Feed-Forward Linearization Circuit of Power Amplifiers

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 전력증폭기의 피드 포워드 선형화 회로도.2 is a feed forward linearization circuit diagram of a power amplifier of the present invention.

Claims (1)

구주파 입력단자(RF IN)를 통해 입력된 두 입력신호를 분배하는 전력분배기(1)와; 이 전력분배기(1)에서 분배된 원신호를 증폭하는 고전력 증폭기(2)와; 이 고전력 증폭기(2)에서 증폭된 신호를 왜곡신호 경로를 거친 신호가 처리되어 합쳐지기 전까지 지연시키는 지연기(3A)와; 상기 전력 분배기(1)에서 분배된 상호 변조성분이 없는 입력신호를 샘플링하여 지연시키는 지연기(3B)와; 이 지연기(3B)에서 지연된 신호의 위상을 조정하는 위상천이기(4A)와; 이 위상천이기 (4A)에서 조정된 신호위상의 진폭을 조정하는 레벨조절기(5A)와; 이 레벨조정기 (5A)에서 조정된 신호를 상기 고전력 증폭기(2)에서 증폭된 신호와 합성하는 가산기(6)와; 이 가산기(6)에서 합성된 신호를 증폭하는 증폭기(7A), (7B)와; 상기 증폭기(7A),(7B)에서 증폭된 신호의 위성을 조정하는 위상천이기(4B)와; 이 위상천이기(4B)에서 조정된 신호위상의 진폭을 조정하는 레벨조절기(5B)와; 이 레벨조절기 (5B)에서 조정된 신호를 상기 지연기(3A)에서 지연된 원신호와 결합시켜 상호 변조잡음을 감소시키는 결합기(9)로 구성함을 특징으로 하는 전력증폭기의 피드 포워드 선형화 회로.A power divider 1 for distributing two input signals inputted through a square wave input terminal RF IN; A high power amplifier 2 for amplifying the original signal distributed by the power divider 1; A delayer 3A for delaying the signal amplified by the high power amplifier 2 until the signal passing through the distortion signal path is processed and combined; A delay unit (3B) for sampling and delaying an input signal having no intermodulation component distributed in the power divider (1); A phase shifter 4A for adjusting the phase of the signal delayed by this delayer 3B; A level adjuster 5A for adjusting the amplitude of the signal phase adjusted by this phase shifter 4A; An adder (6) which combines the signal adjusted by the level adjuster (5A) with the signal amplified by the high power amplifier (2); Amplifiers 7A and 7B for amplifying the signal synthesized in this adder 6; A phase shifter (4B) for adjusting the satellites of the signals amplified by the amplifiers (7A) and (7B); A level adjuster 5B for adjusting the amplitude of the signal phase adjusted by this phase shifter 4B; And a combiner (9) for reducing the intermodulation noise by combining the signal adjusted by the level regulator (5B) with the original signal delayed by the delay unit (3A). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930004882A 1993-03-27 1993-03-27 Feed forward linearization circuit for power amplifier KR950003278B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930004882A KR950003278B1 (en) 1993-03-27 1993-03-27 Feed forward linearization circuit for power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930004882A KR950003278B1 (en) 1993-03-27 1993-03-27 Feed forward linearization circuit for power amplifier

Publications (2)

Publication Number Publication Date
KR940023007A true KR940023007A (en) 1994-10-22
KR950003278B1 KR950003278B1 (en) 1995-04-07

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ID=19352888

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930004882A KR950003278B1 (en) 1993-03-27 1993-03-27 Feed forward linearization circuit for power amplifier

Country Status (1)

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KR (1) KR950003278B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100309808B1 (en) * 1996-07-23 2001-09-29 스펙트리안 Rf amplifier having adaptative predistortion circuit
US6891259B2 (en) 2001-11-03 2005-05-10 Samsung Electronics Co., Ltd. Semiconductor package having dam and method for fabricating the same
KR101530881B1 (en) * 2013-11-21 2015-06-24 주식회사 쏠리드 System for reducing papr and method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100309808B1 (en) * 1996-07-23 2001-09-29 스펙트리안 Rf amplifier having adaptative predistortion circuit
US6891259B2 (en) 2001-11-03 2005-05-10 Samsung Electronics Co., Ltd. Semiconductor package having dam and method for fabricating the same
KR101530881B1 (en) * 2013-11-21 2015-06-24 주식회사 쏠리드 System for reducing papr and method therefor

Also Published As

Publication number Publication date
KR950003278B1 (en) 1995-04-07

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