KR940022289A - Self-assignment device and method for input / output address for ISA bus - Google Patents
Self-assignment device and method for input / output address for ISA bus Download PDFInfo
- Publication number
- KR940022289A KR940022289A KR1019940004756A KR19940004756A KR940022289A KR 940022289 A KR940022289 A KR 940022289A KR 1019940004756 A KR1019940004756 A KR 1019940004756A KR 19940004756 A KR19940004756 A KR 19940004756A KR 940022289 A KR940022289 A KR 940022289A
- Authority
- KR
- South Korea
- Prior art keywords
- interface module
- address
- base address
- communication bus
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0669—Configuration or reconfiguration with decentralised address assignment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
Abstract
이더네트 인터페이스 모듈은 AT 버스와 외부 이더네트 통신버스 사이에 인터페이스를 제공하는 IBM AT 또는 AT 호환 컴퓨터의 AT 버스에 대한 애드-온 카드이다. 컴퓨터가 하드웨어 리셋 명령을 내리면 이더네트 인터페이스 모듈은 EEPROM 으로 부터의 구멍 바이트를 시리얼 레지스터/카운터에 로딩한다. 구성 바이트는 이더네트 인터페이스 모듈용의 메모리와 I/O 베이스 어드레스를 포함한다. 구성 바이트의 로딩과 동시에 중앙처리장치(CPU)는 부트업된다. 부트업 후 CPU는 이더네트 인터페이스 모듈이 부트업 메모리와 이더네트 인터페이스 모듈의 메모리 베이스 어드레스가 다른 애드-온 모듈의 어드레스와 충돌하면 이더네트 인터페이스 모듈의 메모리 베이스 어드레스는 컴퓨터로부터 모듈을 제거하고 제2컴퓨터에 EEPROM을 재프로그래밍함으로써 반자동적으로 재구성된다. 제1시스템에 모듈을 재설치한 후 CPU는 재부팅되고 메모리 베이스 어드레스는 충돌에 대하여 재검사된다. 만약 어떤 메노리 베이스 어드레스의 충돌도 검출되지 않으면 CPU 는 충돌에 대한 입출력 베이스 어드레스를 검사한다. 만약 입출력 베이스 어드레스의 충돌이 검출되면 CPU는 소정의 메모리 위치로부터 판독을 수행한다. 그 판독에 응답하여 이더네트 인터페이스 모듈은 자동으로 그 입출력이 베이스 어드레스를 증가시킨다. CPU는 다시 충돌을 검사하며, 이 과정은 입출력 베이스 어드레스 충돌이 검출되지 않을 때까지 반복된다. 새로운 메모리 및 입출력 어드레스는 EEPROM에서 새로운 구성의 부분으로서 저장된다.The Ethernet interface module is an add-on card for the AT bus of an IBM AT or AT compatible computer that provides an interface between the AT bus and an external Ethernet communication bus. When the computer issues a hardware reset command, the Ethernet interface module loads a hole byte from the EEPROM into the serial register / counter. The configuration byte contains the memory for the Ethernet interface module and the I / O base address. At the same time as the configuration byte is loaded, the CPU is booted up. After boot-up, the CPU determines that the Ethernet interface module has a boot-up memory and the memory interface address of the Ethernet interface module collides with another add-on module address. It is semi-automatically reconfigured by reprogramming the EEPROM into the computer. After reinstalling the module in the first system, the CPU is rebooted and the memory base address is rechecked for conflicts. If no conflict in the memory base address is detected, the CPU checks the input / output base address for the conflict. If a conflict of the input / output base address is detected, the CPU performs reading from a predetermined memory location. In response to the read, the Ethernet interface module automatically increments its base address. The CPU checks for collisions again, and this process is repeated until no I / O base address conflicts are detected. The new memory and input / output addresses are stored as part of the new configuration in the EEPROM.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 원리에 따른 컴퓨터도,1 is a computer diagram in accordance with the principles of the invention;
제2도는 제1도에 도시된 컴퓨터용 이더네트 인터페이스 모듈의 기능 블록도,2 is a functional block diagram of the Ethernet interface module for a computer shown in FIG.
제9도는 시스템 파워업시 또는 시스템 하드웨어 리셋 명령의 수행시 ID 메모리로부터 시프트 레지스트/카운터로 구성 바이트의 판독 및 부트 메모리 충돌의 해소에 대한 흐름도,9 is a flowchart for reading configuration bytes from the ID memory to the shift register / counter and resolving boot memory conflicts when the system is powered up or performing a system hardware reset command.
제10도는 AT 버스용 메모리 베이스 어드레스의 설명도.10 is an explanatory diagram of a memory base address for an AT bus.
Claims (23)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3118093A | 1993-03-12 | 1993-03-12 | |
US08/031,180 | 1993-03-12 | ||
US8/031180 | 1993-03-12 | ||
US11951193A | 1993-09-10 | 1993-09-10 | |
US08/119,511 | 1993-09-10 | ||
US8/119511 | 1993-09-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940022289A true KR940022289A (en) | 1994-10-20 |
KR100276496B1 KR100276496B1 (en) | 2000-12-15 |
Family
ID=26706922
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940004756A KR100276496B1 (en) | 1993-03-12 | 1994-03-11 | Interface control device |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP3588139B2 (en) |
KR (1) | KR100276496B1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016098027A (en) * | 2014-11-25 | 2016-05-30 | 富士フイルム株式会社 | Wraparound case |
-
1994
- 1994-03-11 KR KR1019940004756A patent/KR100276496B1/en not_active IP Right Cessation
- 1994-03-14 JP JP06815794A patent/JP3588139B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR100276496B1 (en) | 2000-12-15 |
JP3588139B2 (en) | 2004-11-10 |
JPH076120A (en) | 1995-01-10 |
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