JPH076120A - Interface control device - Google Patents

Abstract

PURPOSE:To change the memory address and I/O address of an extended module without using a jumper, to automate the steps of the change and to reduce also the number of steps. CONSTITUTION:This interface control device includes a decoder for decoding a constitutional base address for determining an inherent address to which a corresponding interface module is to respond and a changed constitutional address to be used for the corresponding interface module at the time of determining the inherent address for the response of the module and a changing means for automatically changing the constitutional base address when the constitutional base address is the same as the inherent address of any one of other interface modules. The changing means includes a means for responding to a prescribed address on a communication bus and a reading instruction in order to change the constitutional base address to a different constitutional address.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to add-on cards for personal computers, and more particularly to International Business Machines (IBM) AT for connecting an AT bus to an external Ethernet network.
An extension interface card for a compatible personal computer.

[0002]

[Prior Art and Problems to be Solved by the Invention] IBM AT
Personal computers and AT compatible personal computers use the AT standardized bus system for internal communications.
The AT bus is commonly referred to as the Industry Standard Architecture (ISA) bus for 8- and 16-bit systems and the Extended Industry Stair for 32-bit systems.
Called andard Architecture (EISA). This AT bus standard is based on "AT Bus Design", Edward Solari (Annabooks,
1990), the subject matter of which is incorporated herein by reference. The AT bus is an interface between various functional units of a computer, such as a central processing unit (CPU) memory and interfaces for various input / output (I / O) devices. The AT bus uses the system clock, storage, read / write access, and I / O.
O Provides the necessary logic to control read / write cycles, data bus direction, data and interrupt requests, and speaker driver. The storage device includes a hard disk, a floppy disk, an electrically erasable programmable read only memory (EEPROM), and a random access memory (RAM). The I / O device is a printer, a modem, an Ethernet communication network,
including.

Personal computers are modular card racks for holding and interconnecting electronic modules.
It has a housing that houses (module card rack). When the housing is open, the electronic module is inserted into the rack and connected to a motherboard located at the end of the computer housing opposite the opening in the housing. This motherboard provides the electrical interconnection between the in-computer modules including the AT bus and power and ground. A user can change the capabilities of his or her personal computer by installing or removing computer modules in or from the computer housing. For example, RAM (Random A
The memory capacity can be increased by inserting a ccess Memory) module into the housing.

Each device connected to the AT bus and having a storage device has a memory base which defines the memory space used by that device so that the CPU can command a read or a write to that storage device. It must also have an address (base address). Each storage device must have a unique memory base address so that only one device responds to such read and write instructions. The AT bus standard assigns a particular memory address to a particular device. More specifically, the hard disk drive, floppy disk drive, and RAM memory are each assigned a unique memory base address range. Therefore, every personal computer uses these addresses for communication between the hard disk drive, floppy disk drive and RAM memory. In contrast, when a new device is connected to the personal computer,
The memory base address of the new device must not be one of the addresses already assigned to the other device, but can be any address in the address range that has not yet been assigned. However, when multiple devices are added, each with its own storage device and its corresponding unique memory base address, more than one device may have the same memory base address. When this happens, the CPU sends out addresses corresponding to two or more separate devices during the initialization routine at system power up. These two or more separate devices each respond to address commands and all of these devices attempt to read or write to memory. Such multiple responses cause conflicts on the data portion of the bus. In some cases, the CPU may detect the above conflict on the bus, because the data read may differ from the system expected value, for example at system startup or during reading.

In current systems, one type of add-on card is an Ethernet interface module for interfacing between the AT bus and an Ethernet network system. Ethernet standard is In
stitute of Electrical and Electronics Engineers, In
"Information Processi" published in 1989 by c.
ng Systems-Local Area Networks-Part 3: Carrie
r sense multiple access with collision detection
(CSMA / CD) access method and physical layer specific
ations ", International Standard ISO, 8902-3: 1989,
It is described in detail in ANSI / IEEE Std 802.3-1988, the subject matter of which is hereby incorporated by reference. Further, in the current system, when a memory address conflict is detected, the system is powered off, the add-on card that is suspected of causing the conflict is removed from the system, and any module installed on the module is removed. By means of changing the configuration of that card, then re-installing the expansion card in the system,
It is necessary to power up the system and retest the operation of the module. (The means used in current systems to change the base address is a moveable jumper or switch.) The CPU goes through its initialization routine again, and if another memory base address conflict is detected, The process of removing the module and physically changing the memory base address is repeated until the memory conflict is removed. When no memory conflict is detected, the CPU continues to execute its initialization routine.

The plurality of I / O interface devices connected to the AT bus each have an I / O base address. These I / O interface devices respond to instructions on the bus when they detect their I / O base address on the bus. As with the memory base address above, each I / O interface device must have a unique I / O base address. Like the memory address, the AT bus standard
O Assign an address range to a specific device. Therefore, these I / O addresses are used only by these devices. However, when other devices are added to the AT bus, each device must have its own I / O address. However, as with memory base addresses, these devices do not have pre-allocated addresses. Therefore, the AT bus standard assigns I / O address ranges to these new devices.

However, when a new device is connected to the AT bus, the system will keep two or more devices on the AT bus the same I / O until the CPU finishes its initialization routine.
O It never knows if it is using the base address. Therefore, when the CPU sends one I / O bus address to two or more devices on the AT bus that use the same address, all of these two or more devices will respond, and the Create a conflict.

Current systems with EEPROM-based configurations resolve conflicts in I / O base addresses in a manner that is similar to how address conflicts are resolved by jumper or switch-based designs. In detail, in the case of an Ethernet module having an EEPROM-based configuration, the computer user first turns on the computer. If a conflict of I / O memory addresses is detected during the initialization routine of the CPU, the user removes the module from the first computer and the second system that does not have the I / O base address conflict occurs. You must insert the module into. Then the user can rewrite the EEPROM of that module to
It is possible to change the I / O address of the module. Afterwards, the module, whose initial configuration has already been modified, can be reinstalled in the original system.

The above methods for resolving address conflicts are cumbersome, expensive and subject to operator error. The task is to remove the module from the first computer and the module to the second
The second computer, powering on the second computer and reconfiguring the module in the second system, removing the module from the second system, and removing the module from the second system. Reinsert into the first system and retest, and repeat this process until all conflicts are removed,
Need. Each of these steps is labor intensive to perform and is therefore time consuming. The additional time for setup, testing and rework increases the cost of the module. Moreover, the numerous steps described above increase the potential for errors during rework and the potential for damage to the module or computer by repeated removal and installation of modules within the two computer systems.

It is required to change the memory address and I / O address of the extension module without jumpers, and to automate the steps in the change and reduce the number of steps.

[0011]

Briefly stated, one embodiment of the present invention is an interface controller for an addressable interface module. The interface module is adapted to be coupled with the other addressable interface module via a communication bus to the central processing unit. Each interface module is provided on the communication bus by the central processing unit for reading the data from the interface module to the communication bus, with a unique base address for each interface module provided on the communication bus by the central processing unit. Read instructions or write instructions provided on the communication bus by the central processing unit for writing data from the communication bus to the interface module. The interface control device is
It has a stored configuration base address for determining the unique address to which the corresponding interface module must respond. The interface controller also has a decoder for decoding the base address including the modified configuration address for use by the corresponding interface module when determining the unique address for the response by the corresponding interface module. The interface controller includes circuitry for automatically changing the stored configuration base address when the stored configuration base address is the same as the unique address for any one of the other interface modules. The circuit responds to a predetermined address and a read command on the communication bus to change the stored configuration base address to a different configuration address.
Including the circuit. In one particular implementation, the first circuit includes a counter for incrementally adjusting the value represented by the configuration base address.

Briefly, one embodiment of the present invention will be described.
One is the first connected to that bus to eliminate conflicts with a second module connected to the same bus.
Is a method for adaptively adjusting the first identification code of the module in response to a start command. The first identification code is stored in one register. A commanded identification code is received over the bus. The stored first identification code is compared to the commanded identification code received over the bus. Data is sent out on the bus in response to a match between the first identification code and the commanded identification code. Expected data is generated. The data sent out is compared to the expected value of that data, and if the data sent out does not match this expected data, the result is identified as a mismatch. The first identification code stored in the register is
Changes are made in response to this identified discrepancy. The above process is repeated iteratively until no discrepancies are identified between the date sent and the expected data, such that the first module is uniquely identified by the first identification code.

Preferably, the bus is an IBM AT bus, the identification code is an input / output base address, and the start instruction is a hardware reset instruction.

In order to avoid a conflict with a second module connected to the same bus, the first identification code of the first module connected to that bus is adaptively adjusted in response to the start command. A circuit is provided for. The circuit is instructed with a first identification code, a means for storing a first identification code, a means for comparing the first identification code in the storage means with a commanded identification code. A means for sending out data in response to the match between the identification code and both the first module and the second module responding to the match between the first identification code and the commanded identification code. Means for detecting whether or not to send data by means of, and for generating a conflict signal when there is no match, and a first identification code and an instructed identification code in response to the conflict signal. So that both the first module and the second module do not send data when a match occurs between
Means for changing the first identification code.

In a particular embodiment, the interface module transfers data between the Industry Standard Architecture (ISA) bus and the Ethernet network.
The ISA bus transfers a first group and a second group of addresses and a reset instruction from a central processing unit (CPU) to the interface module and data from the interface module to the CPU. This interface module has an adaptive identification code.
The interface module includes a register for storing the adaptive identification address. A decoder is coupled to this register for decoding the adaptive identification address from the CPU and the first group of addresses. A buffer memory is coupled to this decoder and the ISA bus. This buffer memory sends data to the ISA bus in response to the first group of decoded addresses when the selected address in the first group of decoded addresses contains an adaptive identification address. Or receive data from the ISA bus. In response to the second group of addresses from the CPU and the reset instruction, the counter modifies the adaptive identification address stored in the register.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 illustrates an Ethernet according to the principles of the present invention.
FIG. 6 is a functional block diagram illustrating a computer that uses an Ethernet interface module to communicate with an AT bus. The computer 10 has a central processing unit (CPU) module 12 connected to an AT bus 14. This CPU
12 is preferably comprised of a 486 type microprocessor chip manufactured by Intel Corporation, Santa Clara, California. As mentioned above, the AT bus 14 is a standard bus used by IBM AT personal computers and AT compatible personal computers. The AT bus 14 is also connected to a plurality of storage devices including a hard disk 16, a floppy disk 18 and a random access memory (RAM) 20. Although some storage devices are shown,
The present invention does not require all of these devices.
The printer interface module 22 includes the AT bus 14,
It is connected to the printer 23, which is external to the computer 10. Keyboard interface module 24 is AT bus
Connected to 14 and keyboard 25. The keyboard 25 provides the commands selected by the user to the computer 10. Ethernet interface (I / F) module 26
Provides an interface for communication between the AT bus 14 and the Ethernet network 27. Alternatively, the interface module 26 may interface to other buses. As mentioned above, Ethernet is typically a Local Area Network.
A standardized communications network used for (LAN). Ethernet interface module 26
Are preferably packaged on one module.

The power-up sequence for IBM AT computers is well known in the art. Briefly, at power up, the CPU 12 is instructed to instruct each module in the computer 10 to start an initialization routine.
Sends a hardware reset to all modules in computer 10. CPU 12 is a programmable read-only memory (PRO) located on its CPU module.
From M) read the instructions for the basic input / output system (BIOS). After executing the initialization routines from the BIOS, the CPU 12 reads the utility program from the memory. This utility program identifies the modules that are pre-stored in one of the storage devices (preferably the hard disk 16) and are expected to be connected to the AT bus 14, these modules and those modules for the AT bus. The initialization routine and the diagnostic routine are executed with respect to the interface.

FIG. 2 is a functional block diagram of the Ethernet interface module 26 for the computer shown in FIG. Ethernet interface control signals are sent from the CPU 12 through the AT bus 14 on line 102 to the interface controller 32, while vice versa.
2 sent on. CPU 12 is a boot programmable read-only memory (PROM) through AT bus 14 and system address bus 116.
System address instructions are provided to 34 and interface controller 32. The address of the Ethernet interface module functions as an identification code for identifying the module. Upon receiving an instruction address that matches the address of its Ethernet interface module 26, module 26 responds to the requested function.
The boot PROM 34 contains the startup program for the Ethernet interface module 26. This boot PROM 3
4 is, for example, a hard disk 16 or a floppy disk
Diskless system without 18
Can be used in this case, in which case the driver program is loaded from Ethernet 27. The interface controller 32 has an AT bus 14 and an Ethernet 2
It provides a control circuit for interfacing with. Interface controller 32 provides PROM control signals over line 114 to enable boot PROM 34 and control its output. Boot PROM 34 is the bus
Data is provided to the interface controller 32 through 110.

In the first direction, the CPU 12 is the AT bus.
14 and then through the system data bus 106,
For 16-bit AT bus 14, system data bus high by byte transceiver
te transceiver) 40 and system data bus low (low)
Byte transceiver (system data bus low byte transc
eiver) 42 and system data, and 8 bit AT
For bus 14, only system data bus low byte transceiver 42 provides system data. In addition to this, the transfer of instructions and status is done through the system data bus 106. On the contrary, the CPU 12 causes the system data bus 106 and subsequently the AT bus 14 in the second direction.
Through 16 to receive system data from both system data bus high byte transceiver 40 and system data bus low byte transceiver 42 for 16-bit AT bus 14, or 8-bit AT bus 14 to
System data bus receives system data from low byte transceiver 42 only. The system data bus high-order byte transceiver 40 optionally
Provide data to the interface controller 32, or
In the opposite direction, data is received from the interface controller 32. Interface controller 32 provides transceiver control signals on line 104 to control data transmission through system data bus high byte transceiver 40. Similarly, the system data bus low byte transceiver 42 optionally
Provide data to the interface controller 32, or
In the opposite direction, data is received from the interface controller 32. Interface controller 32 provides transceiver control signals on line 112 to control data transmission through system data bus low byte transceiver 42.

Clock 118 provides a clock signal to interface controller 32 via line 238. The interface controller 32 provides control signals to the light emitting diodes (LEDs) 144 through line 143,
144 provides a visual indication of the status of the Ethernet interface module 26. For example, the LED 144 can indicate receive, transmit, collision, link test pass. ID memory 36 provides jumperless form identification information and node identification information to interface controller 32 via line 122 in response to ID memory control signals from interface controller 32 on line 120. In the boot PROM configuration, the ID memory 36 provides storage for the boot PROM address. ID memory 36
Is an electrically erasable programmable read-only memory (EEP
ROM) is preferred. In another embodiment, the form identification and node identification may be stored in the ID PROM which provides this data directly to the buses 108, 110. The interface controller 32 sends the buffer control signal 142 and the buffer storage bus address signal 140 to the buffer storage 138.
Supply to static random access memory (SRAM)
This buffer store 138 is preferably an AT
It provides memory storage for data transferred through the data bus 136 between the bus 14 and the Ethernet 27. SR
AM 138 is typically 8 or 32 kilobytes.

Connector interface 30 comprises several types of mechanical connectors for electrically connecting Ethernet interface module 26 to Ethernet 27. More specifically, the Ethernet interface module 26 has an Attach interface for the AUI interface.
ment unit interface (AUI) connector 128, a coaxial transceiver interface 130 for signal communication through a coaxial line, and a twisted pair connector 134 for twisted pair interface. Interface controller 32 provides a transmit pair signal over line 124 for both AUI connector 128 and coaxial transceiver interface 130. Each of AUI connector 128 and coaxial transceiver interface 130 receives receive / collision pairs signals to interface controller 32 via line 126.
give. Interface controller 32 and twisted pair connector 134 provide differential pair signal (differe pair) over line 132.
Communicate with each other by sending ntial pairs signals).

FIG. 3 is a functional block diagram of the interface control device shown in FIG. The interface controller 32 has five functional blocks: a system interface 146, a buffer controller 152, a control and status register 150, a transmitter circuit 154, and a receiver circuit 156.

The system interface 146 communicates with the AT bus 14 using the signals on lines 102, 104, 108, 110, 112, 114, 116 as described above. The system interface 146 is a buffer register 148 for holding data during communication between the AT bus 14 and the Ethernet 27.
Have. The system interface 146 bidirectionally communicates with the buffer controller 152, and the buffer controller 152
Is a buffer controller 152, a buffer register 148,
ID memory 36, SRAM 138, receiving circuit 156, and transmitting circuit 15
Controls data transfer between and. The control and status register 150 receives control and status information from the system interface 146, buffer controller 152, transmitter circuit 154 and receiver circuit 156, and sends control and status information to the system interface 146 and buffer controller 152.

The transmitter circuit 154 has a transmitter circuit controller 158 for controlling the encoding of the data from the buffer controller 152 in the encoder 160. The encoded data is processed by the pulse shaping circuit and filter 162 and then amplified in the transmitter circuit amplifier 166 and provided to the connector interface 30 (see FIG. 2). Conversely, the receiver circuit 156 receives the data signal from the connector interface 30 and amplifies it in the receiver circuit amplifier 174. The amplified data signal is processed in the receiver circuit slicer 172 and then decoded by the decoder 170. After that, the decoded data signal is sent to the receiving circuit control device 168, and further, the buffer control device 168.
Sent to 152. Collision circuit 164
By processing the decoded signal from decoder 170 and the encoded signal from encoder 160, collisions between reception and transmission on Ethernet 27 are resolved.

FIG. 4 is a functional block diagram of a specific implementation of Ethernet interface module 26 for computer 10 shown in FIG.

The CPU 12 sends a system address (System Address) (S) to the Ethernet interface module 26 and other modules on the AT bus 14 via the AT bus 14.
YSADDRESS) signal. More specifically, on the Ethernet interface module 26, the SYSADDRESS signal is provided on line 116 to the boot PROM 34 address input and the interface controller 32 address input. CPU 12 issues these system address instructions to define the memory address space and the I / O address space. This addressing is described in detail below in conjunction with Figures 9-12. In addition, the AT bus 14 is system coupled to both the output enable (OE bar) input of the boot PROM 34 and the interface controller 32 through line 176, which is part of the Ethernet interface control signal line 102 (FIG. 2). Memory read (System Memo
ry Read) (SMEMR bar) command is given. (Arrangement for the overline (bar) of the signal name is that the signal is in the low state.
Represents that it will be asserted in). The SMEMR bar instruction is used for active low (active low) (a
ctive low) signal, which indicates that the current bus cycle is a memory read operation, and the AT bus 14
Through the Ethernet interface module 26 requesting to output data from the storage device. Although the instructions are described herein as active high and low signals, the invention is not so limited. Ethernet interface module 26 can be designed for either active low signals or active high signals.

Further, the CPU 12 controls the system data (System
Data) (SYSDATA) bus 106 to enable the transfer of all data, commands and status, or to command other devices to send all data, commands and status to the Ethernet interface module 26 over the AT bus 14. More specifically, the system data bus high byte transceiver 40
A SYSDATA bus line 106 to the first bidirectional input / output terminals of both the system data bus low byte transceiver 42 and the system data bus is connected to the AT bus 14. The system data bus, except that the CPU 12 controls the data flow direction through the system data bus high byte transceiver 40, while the interface controller 32 controls the data flow direction through the system data bus low byte transceiver 42. Both high byte transceiver 40 and system data bus low byte transceiver 42 operate in the same manner. System data bus High-order byte transceiver
40 is Input / Output Read from CPU 12
(IOR bar) instructions are received via the AT bus 14 and line 178 via the direction control (DIR) input terminal of this transceiver. This active high signal on the DIR pin causes the system to transfer data from the system data bus 106 to the buffer system data (BSD) bus 180 (including buses 108 and 110 (FIG. 2)) for write operations. Switch data bus high byte transceiver 40. This buffer system data (BSD) bus 180 is an internal data bus on the Ethernet interface module 26.
An active low signal on the DIR input terminal switches transceiver 40 to transfer data in the reverse direction from the BSD bus to the system data bus for read operations. IO
The R bar instruction is an active low signal from CPU 12,
This signal indicates that the current bus cycle is an I / O read operation and requires the Ethernet interface module 26 to output data on the system data bus 106 of the AT bus 14.

Buffer system data bus (BSD <15: 0>
) 180 interconnects the boot PROM 34, system data bus high byte transceiver 40, system data bus low byte transceiver 42, and controller chip 32. (The convention used here to define the bits on the signal line is to enclose the number of bits in <> symbols separated by colons. For example, BSD <15: 0> is bit 15- of the BSD bus. Represents 0.) System data bus transceiver
40 and 42 are 74ALS245 tristate bus transceivers (t
ri-state bus transceiver). The output of the jumper buffers 38 and 39 is also the BSD bus to the second bidirectional input / output terminal of the system data bus high-order byte transceiver 40 and the system data bus low-order byte transceiver 42.
<15: 0> given on 180.

The interface controller 32 enables (enables) the system data bus high byte transceiver 40.
e) Give the Enable Data High Byte (ENHB Bar) command to the (EN Bar) input via line 182. The enable data high byte signal is an active low signal that enables or disables the system data bus high byte transceiver 40. More specifically, the enable data high byte instruction disables system data bus high byte transceiver 40 to disconnect SYSDATA bus 106 from buffer system data bus 180.

Ethernet interface module 26
The system data bus low byte transceiver 42 is controlled in a similar manner for control of system data flow by. However, both control signals for the system data bus low byte transceiver 42 are provided by the interface controller 32. More specifically, the enable data low byte (Enabl
e Data Low Byte (ENLB bar) signal to enable the system data bus low byte transceiver 42 and the low byte direction (L) on line 186.
The Ethernet interface module 26 outputs data on the system data bus 106 by controlling the direction of data flow from the buffer system data bus 180 to the system data bus 106 by sending the ow Byte Direction (LBDIR bar) signal. .

As described in detail below, the Ethernet interface module 26 has a jumper mode.
(jumper mode) and no jumper mode
It is possible to work with either. In jumpered mode, the configuration of the Ethernet interface module is defined by configuration jumpers 188-195, which are the physical wires on this module. Jumpers 188, 19
2 defines the I / O base address, jumpers 189 and 193 define the memory base address, and jumpers 190 and 194 are DM.
A (Direct Memory Access) Acknowledge
(DACK) and jumpers 191, 195 define interrupts. The DACK signal is an active low signal, which indicates that the external DMA controller (not shown) is ready to transfer data between the host system and the Ethernet interface buffer memory.
The I / O base address, memory base address, and interrupt signal are defined below in conjunction with Figures 9-12. The configuration jumper is connected at one end to ground or a voltage source (VCC) (not shown) and at the other end to the inputs of the configuration jumper buffers 38, 39.
Alternatively, the configuration jumpers 192-195 may be used to define configurations other than those described above. The interface controller 32 is provided with a set of mode jumpers 235 that define whether the EEPROM or the ID PROM stores the initial parameters and whether the operation is jumpered or jumperless. To be

In the jumpered mode, the logic level of each configuration jumper is provided on the buffer system data bus 180. Ethernet interface module 26
When the interface controller 32 asks to read the state of the configuration jumper, the interface controller 32 issues a Select Configuration Register 1 instruction on line 196 to the enable (EN bar) input of the jumper buffer 38.
(SEL12) and the jumper buffer 38 responds by sending the configuration jumper signal to the buffer system data bus 18
Give to 0. The SEL 12 instruction is not used in jumperless mode. Instead, jumper buffer 39 uses Select Configuration Register 2 on line 198 provided by interface controller 32 to the enable (EN bar) input of configuration jumper buffer 39.
Enabled by instruction (SEL13). As explained below, the SEL13 instruction is used in jumperless mode to read from the shift register / counter 48. The configuration jumper buffers 38, 39 are preferably 74LS244 tristate buffers. A logic one level is the SEL12 signal on line 196 and SEL1 on line 198.
For either of the three signals, switch its corresponding buffer output to a high impedance state, disconnecting the jumpered input from the output on the bus. Conversely, logic 0
For both the SEL12 instruction 196 and the SEL13 instruction 198, the level switches its corresponding buffer 38, 39 to each and provides the signals corresponding to the configuration jumpers 188-195 to the buffer system data bus 180.

The ID memory 36 stores the configuration bytes for the Ethernet interface module 26. The ID memory 36 is a Nati with 256, 512 or 1024 bits each.
It is preferably a serial EEPROM such as the onalSemiconductor NMC93C06, C26 or C46 series. Serial EEPR
The OM has three inputs from the interface controller 32, a serial data input, a serial data clock or shift clock (SK), and a chip select (CS). The ID memory 36 has a single serial data output (D
O) is applied to the interface controller 32 via line 206. All instructions, addresses, and write data are provided as input to ID memory 36 through line 200 to the input terminals of ID memory 36. Read data of the serial EEPROM and status information are output from the serial data output terminal. Interface controller 32 provides a chip select signal to ID memory 36 via line 202. Serial EEPROM is the shift clock (SK) on line 204 from interface controller 32.
Shifts data in (shift-i
n) or shift out (shif-out).

In another embodiment, the ID PROM 208 is a line
Data is provided to and received from the buffer system data bus 180 through 210. The interface controller 32 has ID P
A PROM chip select signal is provided on line 212 to enable ROM 208 and a latched address signal is provided on line 213 to address ID PROM 36.

The buffer storage memory 138 (also called SRAM 138) and any additional buffer storage memory 138 'are
An address signal 140 is received from the interface controller 32 to select a storage location within that memory. Interface controller 32 provides a buffer chip select signal to each chip enable input terminal on SRAM 138, 138 'through lines 224, 226 to enable the selected chip. Further, the interface controller 32
Provides a write enable (WE bar) signal on line 228 to both SRAMs 138 and 138 'and an output enable on line 230.
(OE bar) Give a signal. Buffer data is bidirectionally communicated via the bus 232 between the SRAMs 138, 138 'and the interface controller 32. Bit 7 of buffer data
0 is provided to SRAM 138. Bit 15 of buffer data
~ 8 is given to SRAM 138 '.

The interface controller 32 and the connector interface 30 communicate via the lines 124, 126, 132 described above. The connector interface 30 is coupled to the Ethernet 27. The interface controller 32 provides the system request to the AT bus 14 via the line 222,
Receive system control signals from AT bus 14 through 220. Lines 220 and 222 are part of line 102 (FIG. 2).

The I / O base address jumper can be connected to line 216 to replace bits 2-0 of the configuration byte to define the I / O base address in jumpered mode. Similarly, the memory base address jumper can be connected to line 218 to replace bits 5-3 of the memory base address or bits 7-6 of the interrupt request (described below). Interrupt request 0 is provided to interface controller 32 via line 214.

FIG. 5 is a functional block diagram of the address decoding circuit and the constituent byte processing circuit of the interface control device shown in FIG.

The jumper mode decoder 44 has a first input (shown collectively as line 235) and a first input (shown collectively as line 235) selectively connected to either ground or a voltage source (VCC) (not shown). It has a mode jumper 235 with two inputs. One output of jumper mode decoder 44 is line 23
7 Jumper / No Jumper (JP / JPLESS) signal above, which indicates whether the module will be reconfigured by changing jumper wires or by software (described below). Is shown to the interface controller 32. For example, when connecting the second input 235 to a voltage source (VCC), use JP / JPL on line 237.
The ESS signal is a logic 1 indicating that the module is operating in jumperless mode. On the contrary, the first
When connecting the input 235 of the to 235 to ground, the JP / JPLESS signal is a logic zero indicating that the module is operating in jumpered mode.

The serial data output on line 206 from the ID memory 36 is coupled to the first input of a data select multiplexer (MUX) 46 in the interface controller 32 and to the shift register /
Given to both counter 48. The shift register / counter 48 is an 8-bit serial input / bit having bits 7-0.
It includes a parallel output shift register. Bits 2-0 (I / OSEL
<2: 0>) defines the I / O base address. Bits 5-3 (also called MSEL <2: 0>) define the memory base address. Bits 7-6 (also called IRQ <3: 0>) define the interrupt line configuration. The decoding of these bits is described in detail below. The shift register / counter 48 has bits 2-0 as described below.
Also functions as a counter for.

Data Select MUX 46 selectively controls the data provided to BSD bus 180. In addition, bits 7-0 of shift register / counter 48 are connected to the second input of data select MUX 46. System Data Output High / Low bus (System Data Out
put High / Low bus) (SDOHL <7: 0>) signal is the data selection MU
Given to the third input of X 46.

The signal provided by the data select MUX 46 is controlled by the control logic circuit 58. FIG. 6 is a schematic diagram of a control logic circuit for controlling the data provided to the buffer system data bus by the data select MUX 46. With / without jumper on line 237 (JP / JPLE
The SS) signal is provided by jumper mode decoder 44 to a first input of control logic circuit 58. Buffer register 148
The READ 13 _- instruction for read address 13 (FIG. 3) is provided to the second input of control logic 58. JP / JPL
ESS signal and READ 13 _- and is, JPLS applied to data selection MUX 46 _- in order to generate a READ 13 signals are taken to NOR (NOR) in the control logic circuit within 58.

A READ 11 command for reading the data output from the ID memory 36 is also given to the data selection MUX 46. Table I shows a truth table for the outputs selected for the data selection MUX 46. Table I READ 11 JPLS _- READ 13 Data out from MUX46 1 0 Do 0 1 Shift register / counter 48 <7: 0> 0 0 SDOHL <7: 0>

The output of the data selection MUX 46 is connected to the bidirectional tristate buffer 50. The bidirectional input / output port of the bidirectional tristate buffer 50 is connected to the buffer system data bus (BSD <15: 0>) 180 as described above. Bidirectional tri-state buffer 50 selectively controls the direction of data flow between buffer system data bus 180 and interface controller 32. The unidirectional output from the bidirectional tri-state buffer 50 is the System Data Input Low (SDAIL <6: 5>).
Flip-flop 52 separately by signal and SDAIL <7>
And a flip-flop 54. The direction of data flow in bidirectional tristate buffer 50 is controlled by control logic circuit 56.

FIG. 7 is a schematic diagram of a control logic circuit for controlling a bidirectional tristate buffer. As shown in FIG. 6, the control logic circuit 58, SEL 13 _- in order to generate a signal, JP / JPLESS signal and READ 13 _- ANDs the signal (the AND), the SEL 13 _- signal, It is provided to the configuration jumper buffer 39 and the control logic circuit 56. Next, referring to FIG. 7, the SEL 13 _- signal is used to generate the Tri _- Out signal.
_{ant Bit) (SYS - LSB -} ) signal inverted NAND of (NAND)
The Tri _- Out signal directs data to flow from the interface controller 32 to the BSD bus 180 in the first logic state (eg, logic "1"), while vice versa. BS in state (eg logic "0")
Instruct that data flow from the D bus 180 to the interface controller 32. The SYS _- LSB _- signal is provided by an internal FIFO or register (not shown) and is a modifier. Therefore, the data selection MUX 46 is
Selected to output data on BSD line 180 from either the shift register / counter 48 or the SDOHL bus.

Hardware reset on line 236 (Har
dware Reset) signal, the JP / JPLESS signal on line 237, and the 20 MHz clock.
ess state machine) 60 to the first, second and third inputs. Ethernet interface module 26
It operates on a 20 MHz clock signal on line 238 from clock 118 (FIG. 2). The first output signal of the jumperless state machine 60, the enable counter (Enable Coun
ter) (EN CNTR) signal is provided to shift register / counter 48 on line 244 to instruct shift register / counter 48 to operate as a shift register or a counter. In addition to this, the shift register clock (SRCLK) signal also shifts data in the shift register / counter 48.
in) to be given. The jumperless state machine 60
The hardware controlled data-in (har
dware controlled data in) (HARD DI) signal on line 239
To the ID memory control MUX 62 through the ID memory control MUX
62 is HARDDI selectively through line 200 to ID memory 36
Give a signal. The jumperless state machine 60 receives the hardware controlled shift clock (hardware controlled) from its third output.
A controlled shift clock (HARD SK) signal is applied to the ID memory control MUX 62 via line 241 to control the ID memory control MUX 62.
HARD SK to ID memory 36 via line 204
Give a signal. The jumperless state machine 60 selects the hardware controlled chip select (hardware contro
lled chip select) (HARD CS) signal on line 242
ID memory control MUX 62, ID memory control MUX 62
The memory 36 is selectively provided with the HARD CS signal via line 202. The jumperless state machine 60 starts from its fifth output
A MUX hardware select (MUXHW) signal is provided on line 243 to the ID memory MUX control circuit 69.

FIG. 8 is a schematic diagram of the ID memory MUX control circuit shown in FIG. MUXHW control signal ID on line 243
The MUXHW signal is supplied to the memory MUX control circuit 69, and the MUXHW signal is inverted and logically ANDed with the JP / JPLESS signal in the ID memory MUX control circuit 69 to form the SEL _-- MUX signal.
Referring again to FIG. 5, the SEL _- MUX signal is selected on line 246 to select either the signal from jumperless state machine 60 to ID memory 36 or the signal from flip-flops 52, 54. Given to memory control MUX 62.

The software controlled chip select signal, the software controlled shift clock signal, and the software controlled data-in signal are applied to flip-flops 52 and 54. In particular, SDAIL <6: 5> and SDAIL <7> are provided separately from buffer system data bus 180 to flip-flops 52, 54 as described above. Furthermore, WRITE10
The signal and the WRITE 11 signal are separately supplied to the flip-flops 52 and 54.

Bit 2 of shift register / counter 48
0 is connected as I / OSEL <2: 0> to the first input of the decoder select MUX 64. Bits 5-3 of the shift register / counter 48 are signal MSEL <to the second input of the decoder select MUX 64.
Given as 2: 0>. I / defined by jumper
The OSEL <2: 0> instruction sends the decoder select MU through line 216.
Given to the third input of X64. The fourth input of the decoder select MUX 64 is connected to the bidirectional tristate buffer 72. The bidirectional port of the bidirectional tri-state buffer 72 has a signal line that carries either the MSEL <2: 0> instruction defined by the jumper as an input or the interrupt request (IRQ <3: 0>) signal as an output. Connected. The input to the bidirectional tri-state buffer 72 is the interrupt request decoder 70.
Is the first output of The second output of interrupt request decoder 70 is interrupt request 0. Shift register / counter 48
Bits 7-6 of the are also provided to the two inputs of the interrupt request decoder 70. Bidirectional tri-state buffer 72 is controlled by the JP / JPLESS instruction on line 237 from jumper decoder 44. The output of the decoder select MUX 64 is connected to the memory address decoder 66 and the I / O address decoder 68. The outputs of memory address decoder 66 and I / O address decoder 68 are connected to SRAM 138 (FIG. 3). The decoder selection MUX 64 is also controlled by the JP / JPLESS instruction from the jumper decoder 44. Decoder Select MUX 64 is a logic 1
From the shift register / counter 48 or jumper in response to a JP / JPLESS instruction or a JP / JPLESS instruction of logic 0, respectively.
It is possible to switch between outputting MSEL <2: 0> and outputting I / OSEL <2: 0>.

The operation of the Ethernet interface module 26 will now be described with reference to the hardware defined above with reference to FIGS. FIG. 9 is a flow chart of reading the configuration byte from the ID memory to the shift register / counter and resolving the memory address conflict when the system power is turned on or at some other time when the System Hardware Reset command is issued. Is. When the system power is turned on (step 300), the CPU
12 includes an Ethernet interface module 26
System Hardware for each module on AT bus 14
Send the Reset command as a start command or initial setting command. After reset, CPU 12 becomes the first AT bus owner. Furthermore, for example, the control (Ctr
The l) key, the ALT key, and the delete (Del) key are pressed by the user at the same time, so that the hardwa
It is also possible that a re Reset command is sent out. The following description describes the operation of the system in terms of hardware resets that are delivered at system power up for typical purposes. However, the present invention is not limited to this.

At the time of hardware reset, the jumperless state machine 60 determines whether the system configuration indicated by the JP / JPLESS signal from the jumper decoder 44 (FIG. 5) is the jumpered system configuration or the jumperless system configuration. judge.
The operation of the Ethernet interface module 26 as a jumperless module will first be described next.

If the system is a jumperless system, the jumperless state machine 60 (FIG. 5) will be on line 202.
The ID memory control MUX 62 is instructed to select the ID memory 36 by setting the Chip Select signal above (FIG. 4) to a high state. The Shift Clock instruction on line 204 (FIG. 4) is set to shift data from the ID memory 36 to the shift register / counter 48 on the serial data output 206. In addition, a jumperless state machine 60 is provided on line 244 to command shift register / counter 48 to operate as a shift register and clock in serial data output 206 from ID memory 36.
Send instructions to shift register / counter 48 through (FIG. 5).

To read the configuration byte from location Ox11 of the ID memory 36 and load it into the shift register / counter 48, the no-jumber state machine 60 generates an appropriate signal (step 302). Bits 5 through 5 as above
3 determines the memory base address (step 304).
FIG. 10 is a map of memory base addresses for the AT bus. The memory address is 0 (00 0000 Hex) to 16384 K (FF
FFFF Hex). Actually the address is 16384
K minus 1, but to make the explanation easier to understand,
This -1 is omitted from addresses with the suffix "K". Within this address range, multiple subranges
Are allocated or reserved for platform memory and BI0S. Address 0 (00 0000 Hex) -5
12 K (06 FFFF Hex) is a reserved location for platform memory. Address 512K (07 0000 Hex) −
640K (09 FFFF Hex) is the address range for platform memory. Address range 100000 (Hex) − F
D FFFF (Hex) is reserved for slot memory. Within this address range, Ethernet interface module 26 preferably has an address range of C4000-DFFFF. The addresses assigned to the base address bits are shown in Table II below. Table II Bit 5 Bit 4 Bit 3 Address (Hex) 0 0 0 0XC4000-0XC7FFF 0 0 1 0XC8000-0XCBFFF 0 1 0 0XCC000-0XCFFFF 0 1 1 1 0XD0000-0XD3FFF 1 0 0 0XD4000-0XD7FFF 1D 0X 04000 0 0XDC000-0XDFFFF 1 1 1 ROM BIOS None-Decryption disabled

Referring again to FIG. 9, as shown in this figure, the Ethernet interface module 26
Load the configuration byte from ID memory 36. The process of reading the configuration byte from the ID memory 36 is started when the system power is turned on, and is in parallel with the above-mentioned initial setting and inspection when the system BIOS is started. Parallel reading of configuration bytes is
To scan the ROM location for a valid boot ROM. If the system starts up properly (step
306), the boot ROM initialization code initializes its resources and replaces the desired interrupt vector (step
307), return system control to the system BIOS,
The initial setting is completed (step 308).

On the other hand, if the system does not boot properly, it is considered that there is a memory address conflict between the Ethernet interface module 26 in the computer 10 and another expansion module (step 3).
06). CPU 12 hangs during system power up if there is a memory conflict. To eliminate this conflict, Ethernet interface module 26
Is removed from computer 10 (step 310),
Installed in the second computer system (step 312). This second system is used to determine if the Ethernet interface module 26 operates properly by reducing the likelihood of memory base address conflicts. This second system has the same basic configuration as the first system, but preferably does not include any add-on modules, thereby eliminating memory conflicts between the Ethernet interface module 26 and the add-on modules. In addition to this, in the no-japper mode, a second system is used to reprogram the ID memory 36 with a different memory base address, as described below. Ethernet interface module
After inserting 26 into the second system, the second system is powered up. If the second system boots properly (step 314), the Ethernet interface module 26 is operational and the problem with the first system is considered to be a memory conflict. Therefore, it is necessary to reallocate the memory base address location of the Ethernet interface module 26 to eliminate this conflict (step 316).

In the jumper mode, the memory base configuration jumper 18 of the Ethernet interface module 26 is added by physically adding or changing jumper wires.
By changing 9 (FIG. 4), the memory base address location is reallocated. In contrast, jumperless mode preferably addresses 0X13 of ID memory 36.
By reprogramming the configuration byte in
The memory base address location is changed. For example, if the memory base address location of the Ethernet interface module 26 initially stored in bits 5-3 of the configuration byte is 000, the address range corresponding to this value 000 is as shown in Table II above. In the range 0XC4000
(Hex)-It is 00XC7FFF (Hex). If there is an address conflict, the Ethernet interface module 26
Both the second expansion module on the AT bus 14 will work. The memory base address of the Ethernet interface module 26 is reallocated by changing bits 5-3 of the configuration byte. For example, by incrementing bits 5-3 from 000 to 001, the corresponding memory base address range is 0XC as shown in Table II.
Increments to the range of 8000 (Hex)-0XCBFFF (Hex).

To reprogram the ID memory 36, the CP
U 12 must first read the configuration byte in order to know the current state of the configuration byte. CPU 12
Issue a request for memory read for the address of the constituent byte at memory location 0X13 of ID memory 36. CPU 12
Sends an I / O read (IOR bar) signal to the system data bus transceiver 40 to communicate the data address and the requested instruction to the ID memory 36 through the system data bus.
The interface controller 32 uses the system data bus 180 to flip-flop 52,
Interface controller 32 to supply data to 54
Command to the bidirectional tri-state buffer 50 (FIG. 5). The ID memory 36 provides the requested configuration byte from its data output port to the data select MUX 46, which in turn outputs the data on the buffer system data bus 180, the Ethernet interface module. Ordered by 26. The interface controller 32 operates from the buffer system data bus 180 to the AT bus 14
The system data bus transceiver 40 is instructed to supply data to the system data bus 106 and the CPU 12 via, and the system data bus transceiver 40 is further disabled. Thereafter, the CPU 12 increments bits 5-3 of the configuration byte, thereby generating a new memory base address, and thereafter, in the manner described above, the location.
Ethernet interface module to write that new configuration byte into ID memory 36 at 0X13
Order 26. In a similar manner to the CPU 12 reading the configuration byte from the ID memory 36, the CPU writes the incremented configuration byte to the 0X13 memory location by giving the appropriate instruction to the ID memory 36 through the system data bus 106. Command to the Ethernet interface module 26.

Referring again to FIG. 9, as shown in this figure, after the Ethernet interface module 26 has been reprogrammed with a configuration byte having a new memory base address, the Ethernet interface module 26 is transferred to the first computer. Installed in the system (step 317), this first system is brought up again by repeating step 300. This first system completes its start-up routine and loads the configuration byte from the ID memory 36 into the shift register / counter 48 as described above with respect to step 302. The interface controller 32, using the decoders 66, 68, steps the configuration byte.
Decrypt at 04. If the system boots properly in step 306, then the memory location reallocation made in step 316 is correct and the Ethernet interface module 26 proceeds as described above.
Proceed to 307. On the other hand, if the reconfigured Ethernet interface module does not boot properly in step 306, remove the Ethernet interface module from the first system (step 310) and test the module in the second system (step 310).
312) is repeated.

If the second system does not boot properly in step 314, then the constituent bytes of its memory are reconstructed (step 316) as described.
318). At step 314, the second system startup is attempted again. Alternatively, instead of reconfiguring the memory location in step 318, the Ethernet interface module is inserted into another system (step 320) and this other system is brought up again as described above with respect to step 314. Is also possible.

Ethernet interface module to eliminate all memory base address conflicts
After 26 is reconfigured, it is determined if there is an I / O base address conflict. Briefly, if all memory base address conflicts have been resolved as described above when the system was booted, the system will start from several predetermined register locations on the Ethernet interface module 26. Check the I / O base address by reading the contents and comparing these contents with its expected value.
In another embodiment, the Ethernet interface module does not include boot memory. In this embodiment, it is not necessary to resolve the memory conflict, since there is no memory on the Ethernet interface module that may cause a conflict. If the above comparison shows a match, then there is no I / O base address conflict. On the other hand, the system considers a conflict if the comparison does not show a match. At this time, the system will read a dummy read from the predetermined register location.
(dummy read) In response, Ethernet interface module 26 increments its I / O base address. The system reads and compares the contents of the register location at the new address and again determines if there is a conflict. The system repeats this process until no conflicts are detected.

I / O addressing will now be described with reference to FIG. 11 which shows the I / O address base for the AT bus 14.
This I / O address can range from 0 (0000 Hex) to 64 K (FFFF Hex).
x) range. Within this address range, 1 K each
The range is divided into two subranges. The first subrange is the lower 256 bytes of memory and is used by the interrupt controller and DM.
Reserved for I / O platform resources such as the A controller. The second subrange is the remaining upper 768 bytes, which are available for general purpose I / O dependent modules.

In the preferred embodiment, as described below, the Ethernet interface module 26 is between 0x260 (Hex) and 0x3FF (Hex) within the second subrange.
Has an I / O address range. As mentioned above, bits 2-0 (also called I / OSEL <2: 0>) of the configuration byte are I / O
Determine the base address. Table III shows 0x260 (Hex) ~ 0x
I / O for the configuration byte within the address range of 3FF (Hex)
Indicates address decoding. Table III Bit 2 Bit 1 Bit 0 Address (Hex) 0 0 0 0X260-0X27F 0 0 1 0X280-0X29F 0 1 0 0X2A0-0X2BF 0 1 1 0X240-0X25F 1 0 0 0X340-0X35F 1 0 1 0X320-0X33F 1 0 0X380-0X39F 1 1 1 0X300-0X31F

Referring now to FIG. 12, in this figure, I / O
The process of the base address conflict routine is described. At this stage, the memory base address conflict is considered to have already been resolved, as described above in Figures 9-10. (Alternatively, in another embodiment where the Ethernet interface module has no boot memory, it is unnecessary to resolve memory conflicts as described above.) The computer is booted and described above with respect to step 300 of FIG. The initialization routine is performed as described above (step 330). The interface controller 32 loads the configuration byte from the ID memory 36 into the shift register / counter 48 in a manner similar to step 302 described above with respect to FIG. 9 (step 332). At the completion of this read, the shift register / counter 48 is set to counter mode by the shampooless state machine 60. In this mode, only bits 2-0 of the configuration byte that determine the I / O base address of the Ethernet interface module 26 are incremented by the counter. The remaining bytes of the configuration byte are left unchanged. The interface controller 32, in a manner similar to that described with respect to step 304 of FIG.
Decode the configuration byte into an I / O base address, a memory base address and an interrupt (step 334). In addition to this, a "dirty bit" in a register within the Ethernet interface module 26 is assigned for register / counter mode monitoring of that particular cell. Then CPU 12 reads from memory within the initial range (step 336). More specifically, the CPU 12
Enters its I / O program to read the contents of the eight registers of interface controller 32. Preferably each register has 8 bytes. Reading the eight registers is provided as an example only. The invention is not limited to reading only eight registers. To determine if there is a conflict
Software programmers need to ensure that the two different expansion modules on the AT bus 14 will not have the same value stored in register locations read by the CPU 12 from accidental coincidence. It is possible to read as many registers as

When the system power is turned on, the eight registers of the interface controller 32 are assigned a module identifier or "company code" as a part of the utility program recorded on the hard disk 16.
Is set to a predetermined value that is also stored as.
The module identifier preferably uniquely identifies the module to other modules on the AT bus 14.
This module identifier is preferably the initial value stored in the first eight registers of the Ethernet interface module 26. These eight registers
After CPU 12 reads, CPU 12 executes a software utility that reads the module identifier from hard disk 16 and compares this identifier with the readings from the first eight registers (step 338). Since the CPU 12 expects the read value to match the value of this module identifier, it interprets the difference between these two values as an I / O base address conflict. If there is a match between the reading and the module identifier (step 340), the CPU 12
Interprets this match as the absence of an I / O base address conflict between the Ethernet interface module 26 and other modules on the AT bus 14, as well as the unique I / O for the Ethernet interface module 26. Interpret the base address as found by that CPU 12 (step 342).

On the other hand, the above 8 read by the CPU 12
If the contents of one register differ from the expected value (step
340), the system interprets this mismatch as an I / O base address conflict, or that the Ethernet interface module 26 is not at the I / O address that the CPU 12 just read. To do. The system ignores the presence of Ethernet module 26 by ignoring the data provided on AT bus 14, but the software utility continues by attempting to read from a predetermined memory location (step 344). This predetermined memory location is preferably at address 0X12 (Hex). CPU
Reads are preferred because the Ethernet interface module 26 can be physically damaged by conflicting addressing if the 12 attempts to write to some type of storage. This read is a "dummy raed" because the shift register / counter 48 is set for counter mode and the CPU 12 has no knowledge of what is actually being read. In counter mode, every time a dummy read is performed, the shift register / counter 48
Increments the value of bits 2-0 by 1 so that I /
O Jump the base address to the next address range as defined in Table III. The initial I / O base address range is bits 2-0 of the configuration byte with the value 111
It is preferably set to 0X300 (Hex) to 0X31F (Hex) defined by When the counter is incremented by reading from memory location 0X12, bits 2-0 of the configuration byte change to a value of 000, which corresponds to the new address range of 0X260 (Hex) to 0X27F (Hex). The utility program reads the interface controller 32 for the proper module identifier each time the shift register / counter 48 counts up to the next base I / O address. This allows the Ethernet interface module 26 to dynamically reconfigure itself to a conflicting I / O base address. However, after the seventh increment, bits 2-0 return to the value 111. After the eighth memory read, there is no Ethernet interface module 26 in the system or all I / O base addresses are unavailable. CPU 12 determines if the module location is within the range of memory being read (step 346). If the module location is not within the above memory range, the value of its configuration byte is not incremented (or counted) and the system increments the I / O base address (step 353) and registers at the incremented address. Read (step 348) and loop back to step 338 to compare the reading with the expected value.
back) If no match is found in step 340,
CPU 12 loops back to step 344. When a match is obtained, CPU 12 loops back to step 342. The CPU 12 sends a write command to a predetermined address, and the interface control unit 32 sets the shift register / counter 48 in the count mode to set the user mode.
Switch to (user mode) and allow the user to access the ID memory from the system side if necessary.

On the other hand, if the address of the Ethernet interface module is within the range of memory read in step 346, CPU 12 determines whether it is the last increment in the range (step 350). If so, all I / O base address range slots are unavailable, or the Ethernet interface module 26 is not installed in the system (step 354). On the other hand, if the memory read is not the final memory increment of the memory range, the controller chip 32 increments the I / O base address of the Ethernet interface module 26 by incrementing bits 2-0 of the shift register / counter 48. Increment (step
352). The CPU increments the I / O base address (step 3
53), then read from the eight registers at the incremented I / O base address (step 348). CP
U 12 loops back to comparing the reading with the expected value in step 338.

Software feature deterrence is provided to prevent accidental modification of the constituent bytes in shift register / counter 48 from accidental writes to address 0X12. The shift register / counter 48 is disabled by setting the I / O base unlock bit in the data link register to 0 until a system hardware reset is reissued. This reset command sets the unlock bit to 1, allowing the Ethernet interface module 26 to dynamically reconfigure itself to a conflicting I / O base address.

Once the I / O address conflict is resolved, the software can continue with the initialization routine. The Ethernet interface module 26 resets the shift register / counter 48 to register mode by setting / resetting the so-called "dirty bit". Immediately after that, the utility program reads the new configuration byte from the shift register / counter 48 and identifies it with the new base address.
It is possible to reprogram the configuration byte stored in memory 36.

Now, the interrupt will be described after the I / O address program is completed. As above, bits 7-6
Are used only for interrupt line configurations. The interrupt signal allows the expansion card to request interrupt service by the CPU 12. These bits are programmable to select any one of the four interrupt lines available on the host interface side of the Ethernet interface module 26. The user has the option to connect said interrupt line to any set of four system interrupt lines (interrupts 0-3) available to the system user. The above utility tests the interrupt configuration and, if there is a conflict, the next available interrupt option determines the ID memory 36
Reprogram, reboot the system, and retest the configuration.

Table IV below is a list of interrupt bit definitions. Table IV Bit 7 Bit 6 Description element 0 0 Interrupt 0 0 1 Interrupt 1 1 0 Interrupt 2 1 1 Interrupt 3

Memory base address conflict and I /
No additional reprogramming of the configuration byte is required after the ID memory 36 has been reprogrammed to resolve O base address conflicts and interrupt conflicts. Subsequent use of the thus configured computer 10 will cause no conflicts.

Having thus described the invention and described the preferred embodiments thereof, it is anticipated that other modifications and applications will occur to those skilled in the art. Therefore, it is intended that the present invention be limited only by the claims herein.

As described above, according to the present invention, the memory address and I / O address of the extension module are changed without jumpers, the steps in the change are automated, and the number of steps is reduced. effective.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a computer according to the principle of the present invention.

2 is a functional block diagram of an Ethernet interface module for the computer shown in FIG. 1. FIG.

3 is a functional block diagram of the interface control device shown in FIG. 2. FIG.

4 is a functional block diagram of a particular embodiment of an Ethernet interface module for the computer shown in FIG.

5 is a functional block diagram of an address decoding circuit and a constituent byte processing circuit of the interface control device shown in FIG.

FIG. 6 is a schematic diagram of control logic circuitry for controlling data provided to a buffer system data bus by a data selection MUX.

FIG. 7 is a schematic diagram of a control logic circuit for controlling a bidirectional tristate buffer.

FIG. 8 is a schematic diagram of the ID memory MUX control circuit shown in FIG.

[Figure 9] System power-on or System Har
6 is a flowchart of reading the configuration bytes from the ID memory to the shift register / counter and resolving boot memory conflicts at other times when the dware Reset instruction is issued.

FIG. 10 is a map of a memory base address for the AT bus.

FIG. 11 is a map of an I / D base address for the AT bus.

12 is a flowchart showing a procedure used in reconfiguring an I / O base address of the Ethernet interface module shown in FIG.

[Explanation of symbols]

 10 ... Computer 12 ... Central processing unit module 14 ... AT bus 16 ... Hard disk 18 ... Floppy disk 20 ... Random access memory 22 ... Keyboard interface module 26 ... Ethernet interface (I / F) module 27 ... Ethernet network 32 ... Interface control device

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 23, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0073

[Correction method] Change

[Correction content]

[0073]

As described above, according to the present invention,
There is an effect that the memory address and the I / O address of the extension module are changed without jumpers, the steps in the change are automated, and the number of steps is reduced.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Wen-Feng Chan, California 95070, Saratoga, Elisa Avenue 19724 (72) Inventor Faisal Abbas USA, California 95123, San Jose, Curry Drive 535

Claims (23)

[Claims] 1. An interface controller for an addressable interface module, the interface module being adapted to be coupled to a central processing unit via a communication bus together with other addressable interface modules. , Each of the interface modules has a unique base address unique to the interface module provided on the communication bus by the central processing unit and for reading data from the interface module to the communication bus,
Adapted to respond to a read instruction provided by said central processing unit on said communication bus or a write instruction provided by said central processing unit for writing data from said communication bus to said interface module. A stored configuration base address for the interface controller to determine a unique address to which the corresponding interface module must respond, and the unique address for a response by the corresponding interface module. A decoder for decoding the base address, including the modified configuration address for use by the corresponding interface module upon determination of the address; and the stored configuration base address of any of the other interface modules. Solid for Change means for automatically changing the stored configuration base address when the stored configuration base address is the same as the existing address, the changing means changing the stored configuration base address to a different configuration address. An interface controller for responding to a predetermined address on the communication bus and the read command. 2. The interface controller according to claim 1, wherein the interface controller is composed of a single integrated circuit chip. 3. The interface controller according to claim 1, wherein the changing unit includes a counter for incrementally adjusting a value represented by the configuration base address. 4. The interface controller comprises a memory for initially storing the configuration base address,
4. The counter is coupled to receive the configured base address from the memory prior to incremental adjustment.
The interface control device described in. 5. The interface controller includes a mode selector for selectively enabling or disabling the altering means to alter the configuration base address, and a mode selector for disabling the altering means when the altering means is disabled. A jumper controller for selecting the unique address for use by the corresponding interface module, and the interface controller according to claim 1, claim 3 or claim 4. 6. A state machine for controlling the reading of the configuration base address from the memory and the loading of a signal corresponding to the configuration base address into the counter. Interface controller. 7. The stored configuration base address is first
Of base addresses and a second base address, the first base address being the base address to be changed,
The second address is a base address for a memory address space, and the decoder provides the first base address and the second base address to provide different base addresses to the interface controller. An interface controller according to claim 1, including means for decoding both. 8. An auto-reconfigurable addressable interface module for coupling between a communication network and a communication bus with other addressable interface modules and a central processing unit, each of said interface modules. On the communication bus by the central processing unit for reading a data from the interface module to the communication bus, and a unique base address specific to the interface module provided on the communication bus by the central processing unit. Adapted to respond to a read command provided or a write command provided on the communication bus by the central processing unit for writing data from the communication bus to the interface module, Automatic reconfigurable A memory module for storing data unique to the auto-reconfigurable interface module, and a configuration for determining a unique base address to which the auto-reconfigurable interface module should respond. Responsive to a register for storing a base address and a predetermined address on the communication bus and one of the read instructions for changing the configuration base address stored in the register to a different configuration address. Means and a decoder for decoding the configuration address modified by the means for use by the interface module in determining the unique address for a response by the auto-reconfigurable interface module. , Said auto-reconfigurable interface A source module is responsive to one of the read instructions on the communication bus to read the unique data from the memory onto the communication bus for comparison with expected data by the central processing unit, automatically reconfigurable. Interface module. 9. The auto-reconfigurable interface module also has additional memory for data sent on the communication bus, and the register stores an additional base address for the additional memory. , The decoder is
9. The auto-reconfigurable interface module according to claim 8, further comprising means for decoding the additional base address in the form of separate base addresses for addressing the additional memory. 10. The auto-reconfigurable interface module of claim 8, wherein the auto-reconfigurable interface module is adapted to provide an interface between the communication bus and the communication network. 11. The automatically reconfigurable interface module of claim 10, wherein the automatically reconfigurable interface module is adapted to interface with a local area network. 12. The auto-reconfigurable interface module of claim 11, wherein the auto-reconfigurable interface module is adapted to interface to an Ethernet network. 13. The automatically reconfigurable interface module of claim 8, wherein the automatically reconfigurable interface module is adapted to couple to an AT communication bus. 14. A system interface coupled to the communication bus for controlling communication with the communication bus; communicated between the automatically reconfigurable interface module and the communication bus or the communication network. A buffer memory for storing data, a buffer controller for controlling data transfer from the buffer memory, and for processing and supplying data to the communication network in response to a command from the buffer controller. 9. The automatically reconfigurable interface module according to claim 8, further comprising: a transmitter circuit for receiving the data from the communication network; and a receiver circuit for receiving and processing data from the communication network. 15. A microprocessor system including a communication bus, a plurality of addressable interface modules each coupled to the communication bus, and a central processing unit coupled to the communication bus, the interface comprising: Each of the modules is provided by the central processing unit to the unique base address unique to each of the interface modules provided on the communication bus by the central processing unit and for reading data from the interface module to the communication bus. A read command provided on a communication bus or a write command provided by the central processing unit for writing data from the communication bus to the interface module, the interface module being adapted to respond to the read command. At least 1 Includes an automatic reconfigurable interface module, the automatic reconfigurable interface module, a memory for storing data unique to the automatic reconfigurable interface module, the automatic reconfigurable interface module A register on the communication bus for storing a configuration base address for determining a unique address to respond to, and a register on the communication bus for changing the configuration base address stored in the register to a different configuration address. Means for responding to a predetermined address and one of the read instructions, for use by the auto-reconfigurable interface module in determining the unique address for response by the auto-reconfigurable interface module, By said means A decoder for decoding the updated configuration address, wherein the automatically reconfigurable interface module retrieves the unique data from the memory to the communication bus for comparison with expected data by the central processing unit. A microprocessor system responsive to the read command on the communication bus for reading. 16. A data bus coupled to pass data on the communication bus between the central processing unit and the auto-reconfigurable interface module, the central processor comprising: 16. The microprocessor system of claim 15, comprising: an address bus coupled to pass address signals on the communication bus from a processing unit to the automatically reconfigurable interface module. 17. The auto-reconfigurable interface module includes additional memory for data to be passed on the communication bus, and the register sets a basis for a memory space of the additional memory. 16. storing additional base addresses of the decoder, the decoder being further adapted to decode the additional base addresses in the form of another base address for addressing the additional memory. The microprocessor system according to. 18. A method for automatically generating a unique address for an addressable interface module having an interface controller, said addressable interface module together with another addressable interface module. Each of the interface modules adapted to be coupled to a central processing unit via a communication bus,
A unique base address specific to the interface module provided on the communication bus by the central processing unit and provided on the communication bus by the central processing unit for reading data from the interface module to the communication bus. A read command or a write command provided by the central processing unit for writing data from the communication bus to the interface module, the method being adapted to respond to the interface controller. Storing a configuration base address therein and reading the predetermined address and the predetermined address on the communication bus when the unique address and the configuration base address for the interface module having the interface controller are the same. With one of the instructions To answer,
Changing the configuration base address stored in the step to a different configuration address, for use by the interface module having the interface controller in determining the unique address for a response by the interface module. And decoding the modified configuration address. 19. The method of claim 18, wherein the step of modifying the stored configuration base address further comprises an incremental adjustment step of incrementally adjusting a value represented by the configuration base address in a counter. 20. The interface controller comprises a memory, the method first storing the configuration base address in the memory, and the configuration base address from the memory prior to the increment adjusting step. 20. The method of claim 19, further comprising: receiving in the counter. 21. The interface module comprises the interface controller including a mode controller and a jumperless controller, and the method further includes changing the configuration base address under the control of the mode controller. 19. The method of claim 18, further comprising the steps of: selectively enabling or disabling the switch, and selecting the unique address under the control of the jumper controller when the changes are disabled. The method according to claim 19 or claim 20. 22. The interface controller having the interface controller includes a state machine, the method further providing a signal corresponding to the configuration base address to the counter when the counter makes the incremental adjustment. 21. The method of claim 20, further comprising a control step of using the state machine to control the reading of the configured base address from the memory according to. 23. The stored configuration base address is
Including a first base address and a second base address, the first base address being a base address to be modified, and the method further comprising the first base address to provide another base address. 19. The method of claim 18, also including the step of decoding both and the second base address.