KR940020748A - Signal Processing Method of Phase Synchronous Loop (PLL) Frequency Synthesizer of Digital Cordless Telephone - Google Patents

Signal Processing Method of Phase Synchronous Loop (PLL) Frequency Synthesizer of Digital Cordless Telephone Download PDF

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Publication number
KR940020748A
KR940020748A KR1019930003020A KR930003020A KR940020748A KR 940020748 A KR940020748 A KR 940020748A KR 1019930003020 A KR1019930003020 A KR 1019930003020A KR 930003020 A KR930003020 A KR 930003020A KR 940020748 A KR940020748 A KR 940020748A
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KR
South Korea
Prior art keywords
frequency
pll
processing method
signal processing
cordless telephone
Prior art date
Application number
KR1019930003020A
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Korean (ko)
Inventor
조성우
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930003020A priority Critical patent/KR940020748A/en
Publication of KR940020748A publication Critical patent/KR940020748A/en

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  • Mobile Radio Communication Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

본 발명은 채널간격이 100kHz이고 50kHz의 배수인 반송주파수를 사용하는 디지탈 무선 전화기의 위상 동기루프(PLL) 주파수 합성장치의 신호처리방법에 관한 것으로서, 중간 주파수(Fif)를 정수배가 아닌 주파수(150.15MHz)로 형성함으로써, 주파수 합성수단의 기준신호(Fin)의 최대 가능 주파수를 100kHz로 사용 가능하게 하여 PLL 루프대역폭이 증가되고 동기시간을 빠르게 하며 노이즈 및 스퓨리어스(Spurious)특성이 개선된 출력신호를 얻기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing method of a phase locked loop (PLL) frequency synthesizing apparatus of a digital cordless telephone using a carrier frequency having a channel interval of 100 kHz and a multiple of 50 kHz. MHz), which enables the maximum possible frequency of the reference signal Fin of the frequency synthesizing means to be 100 kHz, thereby increasing the PLL loop bandwidth, speeding up the synchronization time, and improving the output signal with improved noise and spurious characteristics. Is to get.

Description

디지탈 무선 전화기의 위상동기루프(PLL) 주파수 합성장치의 신호처리방법Signal Processing Method of Phase Synchronous Loop (PLL) Frequency Synthesizer of Digital Cordless Telephone

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 베이스유닛과 무선 전화기간의 송수신 방법을 보인 도면.1 is a diagram showing a transmission and reception method between a base unit and a wireless telephone.

제2도는 디지탈 무선 전화기의 블럭도.2 is a block diagram of a digital cordless telephone.

Claims (2)

반송파 주파수(fe)가 ｛fn+0.05+(0.1*n)｝MHz (fn;임의의 정수, n; 0부터 n까지의 정수로서 채널번호를 나타냄)로 결정되어 있는 디지탈 무선전화기에 있어서, 위상동기신호와 수신 입력신호에 의해 형성되는 중간 주파수(Fif)를 정수배가 아닌 주파수로 형성함으로써, 주파수 합성수단의 기준신호(Fin)의 최대 가능 주파수를 100kHz로 사용 가능하게 하는 것을 특징으로 하는 디지탈 무선 전화기의 위상 동기루프(PLL) 주파수 합성장치의 신호처리방법.In a digital radiotelephone having a carrier frequency (fe) determined by? Fn + 0.05 + (0.1 * n)｝ MHz (fn; any integer, n; represents a channel number as an integer from 0 to n). A digital radio, characterized in that the maximum possible frequency of the reference signal Fin of the frequency synthesizing means can be used at 100 kHz by forming the intermediate frequency Fif formed by the synchronization signal and the received input signal at a frequency not an integer multiple. Signal processing method of a phase locked loop (PLL) frequency synthesizer of a telephone. 제1항에 있어서, 상기 중간 주파수(Fif)는 ｛fn+0.05+(0.1*m)｝(여기서, 상기 fIF는 중간 주파수를 설정하기 위한 임의의 정수이고 m은 채널번호 의미)로 설정되는 것을 특징으로 하는 디지탈 무선전화기의 위상 동기루프(PLL) 주파수 합성장치의 신호처리방법.The method of claim 1, wherein the intermediate frequency (Fif) is set to ｛fn + 0.05 + (0.1 * m)｝ (where fIF is any integer for setting the intermediate frequency and m is the channel number meaning) A signal processing method of a phase locked loop (PLL) frequency synthesizing apparatus of a digital radio telephone. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003020A 1993-02-27 1993-02-27 Signal Processing Method of Phase Synchronous Loop (PLL) Frequency Synthesizer of Digital Cordless Telephone KR940020748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930003020A KR940020748A (en) 1993-02-27 1993-02-27 Signal Processing Method of Phase Synchronous Loop (PLL) Frequency Synthesizer of Digital Cordless Telephone

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930003020A KR940020748A (en) 1993-02-27 1993-02-27 Signal Processing Method of Phase Synchronous Loop (PLL) Frequency Synthesizer of Digital Cordless Telephone

Publications (1)

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KR940020748A true KR940020748A (en) 1994-09-16

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KR1019930003020A KR940020748A (en) 1993-02-27 1993-02-27 Signal Processing Method of Phase Synchronous Loop (PLL) Frequency Synthesizer of Digital Cordless Telephone

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