KR940020677A - Phase control circuit - Google Patents

Phase control circuit Download PDF

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Publication number
KR940020677A
KR940020677A KR1019930001633A KR930001633A KR940020677A KR 940020677 A KR940020677 A KR 940020677A KR 1019930001633 A KR1019930001633 A KR 1019930001633A KR 930001633 A KR930001633 A KR 930001633A KR 940020677 A KR940020677 A KR 940020677A
Authority
KR
South Korea
Prior art keywords
comparison
voltage
outputting
signal
phase
Prior art date
Application number
KR1019930001633A
Other languages
Korean (ko)
Other versions
KR950004635B1 (en
Inventor
박종철
정오장
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930001633A priority Critical patent/KR950004635B1/en
Publication of KR940020677A publication Critical patent/KR940020677A/en
Application granted granted Critical
Publication of KR950004635B1 publication Critical patent/KR950004635B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions

Abstract

본 발명은 연산 증폭기와 미적분기로 구성된 위상 제어 회로에 관한 것으로 특히 입력되는 전압을 증폭하여 셋팅 전압과 비교하여 위상을 제어할 수 있도록 한 위상 제어 회로에 관한 것으로, 회로 소자에 의한 오차값에 대한 출력 파형의 왜곡을 보상시켜 주므로 원하는 출력파형을 얻을 수 있으며, 펄스 발생기를 사용하지 않게 되어 필요한 소자를 줄일 수 있고 미세한 감지 센서로부터 인가되는 입력 전압은 증폭되어 셋팅값과 비교하여 정확한 위상 제어를 통해 왜곡없는 출력 파형을 얻을 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control circuit composed of an operational amplifier and a calculus. More particularly, the present invention relates to a phase control circuit that amplifies an input voltage to control a phase in comparison with a setting voltage. By compensating for the distortion of the waveform, the desired output waveform can be obtained, and the pulse generator is not used to reduce the necessary elements, and the input voltage applied from the fine sensing sensor is amplified and compared with the setting value, and it is distorted through accurate phase control. This has the effect of obtaining a missing output waveform.

Description

위상 제어 회로Phase control circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 다른 위상 제어 회로도.1 is a phase control circuit diagram according to the present invention.

제2도는 본 발명의 다른 실시예시도.2 is another exemplary embodiment of the present invention.

Claims (1)

외부로부터의 위상을 검출하여 출력하는 위상 검출수단(10), 상기 위상 검출수단(10)으로부터 인가된 검출 신호를 인가 받고 이용 전압 이상 또는 이하의 전압을 제거하는 클리퍼(30), 상기 클리퍼(30)에 연결되고 외부로부터 계단파 위상/톱니파 상승 포인트 조절신호를 인가 받아 구형파로 변환하기 위한 구형파 변환수단(40), 상기구형파변환수단(40)의 출력신호를 미분하기 위한 미/적분수단, 외부로부터의 입력전압을 증폭하여 옵셋 전압을 조정하고 증폭률 조정 및 리딩 전압을 조정하여 출력하는 입력증폭수단(100), 상기 입력증폭수단(100)의 출력신호를 인가 받고 외부로부터의 셋팅된 전압을 인가 받아 상호 비교 신호를 출력하기 위한 제1비교수단(110), 상기 미적분수단으로부터의 적분신호와 상기 제1비교수단(110)으로부터의 비교신호를 인가 받아 상호 위상을 비교하여 비교 출력을 내는 제2비교수단(70), 상기 제2비교수단(70)으로부터의 출력신호를 미분하는 미분수단(80), 상기 미분수단(80)을 거친 출력신호를 인가 받아 원하는 펄스를 발생하여 출력하는 펄스 발생수단(90)을 구비하는 것을 특징으로 하는 위상 제어 회로.Phase detection means 10 for detecting and outputting a phase from the outside, a clipper 30 for receiving a detection signal applied from the phase detection means 10 and removing a voltage above or below a used voltage, and the clipper 30 Square wave converting means 40 for converting a stepped wave phase / sawtooth rising point control signal from the outside into a square wave, differential / integrating means for differentiating an output signal of the square wave converting means 40, Input amplification means 100 for amplifying the input voltage from the input voltage to adjust the offset voltage and adjusting the amplification rate and the leading voltage and outputting the output signal of the input amplifying means 100 and applying a set voltage from the outside. A first comparison means 110 for receiving and outputting a mutual comparison signal, and receiving an integration signal from the calculus means and a comparison signal from the first comparison means 110. A second comparison means 70 for comparing the phases and outputting a comparison output, a differential means 80 for differentiating the output signal from the second comparison means 70, and an output signal passing through the differential means 80 And a pulse generating means (90) for generating and outputting a desired pulse. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930001633A 1993-02-06 1993-02-06 Phase control circuit KR950004635B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930001633A KR950004635B1 (en) 1993-02-06 1993-02-06 Phase control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930001633A KR950004635B1 (en) 1993-02-06 1993-02-06 Phase control circuit

Publications (2)

Publication Number Publication Date
KR940020677A true KR940020677A (en) 1994-09-16
KR950004635B1 KR950004635B1 (en) 1995-05-03

Family

ID=19350494

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930001633A KR950004635B1 (en) 1993-02-06 1993-02-06 Phase control circuit

Country Status (1)

Country Link
KR (1) KR950004635B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101120474B1 (en) * 2010-11-24 2012-02-29 주식회사 이피코 Apparatus to detect phase of input power for pulsewidth modulation converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101120474B1 (en) * 2010-11-24 2012-02-29 주식회사 이피코 Apparatus to detect phase of input power for pulsewidth modulation converter

Also Published As

Publication number Publication date
KR950004635B1 (en) 1995-05-03

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