KR940017875A - Memory parallel processing method and apparatus for motion compensation of high definition television - Google Patents

Memory parallel processing method and apparatus for motion compensation of high definition television Download PDF

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Publication number
KR940017875A
KR940017875A KR1019920027178A KR920027178A KR940017875A KR 940017875 A KR940017875 A KR 940017875A KR 1019920027178 A KR1019920027178 A KR 1019920027178A KR 920027178 A KR920027178 A KR 920027178A KR 940017875 A KR940017875 A KR 940017875A
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KR
South Korea
Prior art keywords
memory
parallel processing
definition television
motion compensation
processing method
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Application number
KR1019920027178A
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Korean (ko)
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KR100243866B1 (en
Inventor
김범수
이진학
구경봉
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920027178A priority Critical patent/KR100243866B1/en
Priority to JP5337989A priority patent/JPH077725A/en
Publication of KR940017875A publication Critical patent/KR940017875A/en
Application granted granted Critical
Publication of KR100243866B1 publication Critical patent/KR100243866B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation

Abstract

본 발명은 고화질 텔레비젼의 움직임 보상을 위한 메모리 병렬 처리방법 및 그 장 치에 관한 것으로써, 특히 휘도, 색차신호를 분리하지 않고 메모리를 8단 병렬처리하여, 데이타 처리에 요구되는 속도를 휘도, 색차신호를 분리한 구조의 경우 보다 1/6 낮은 속도로 데이타를 처리하여 고화질 텔레비전과 같이 메모리의 최고 처리속도 보다 빠른 고속의 데이타 처리를 기존의 법용 메모리로도 제작가능하게 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory parallel processing method and a device for compensating for motion of a high definition television. In particular, the present invention relates to an eight-stage parallel processing of memory without separating luminance and color difference signals, thereby reducing the luminance and color difference required for data processing. In the case of the signal separation structure, the data is processed at 1/6 times lower speed, so that high-speed data processing faster than the maximum processing speed of the memory, such as a high-definition television, can be produced with conventional legal memory.

Description

고화질 텔레비젼의 움직임 보상을 위한 메모리 병렬처리 방법 및 장치Memory parallel processing method and apparatus for motion compensation of high definition television

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 고화질TV의 움직임 보상을 위한 회로 구조도, 제2도는 본 발명의 메모리 구조도(256K×32), 제3도는 본 발명에 의한 휘도, 색차 신호분리를 위한 메모리 어드레스 사용법도이다.1 is a circuit structure diagram for motion compensation of a high-definition TV, FIG. 2 is a memory structure diagram (256K × 32) of the present invention, and FIG. 3 is a memory address usage diagram for separation of luminance and chrominance signals according to the present invention.

Claims (3)

고화질 텔레비전의 움직임 보상회로 구조중 메모리의 병렬 처리방법에 있어서, 4개의 화소단위(32비트)를 입력순서에 따라 짝수, 홀수 메모리(256K×32)에 분리하여 저장처리하는 과정으로 이루어진 것을 특징으로 하는 고화질 텔레비전의 움직임 보상을 위한 메모리 병렬 처리방법.A parallel processing method of a memory in a motion compensation circuit structure of a high-definition television, comprising: separating and storing four pixel units (32 bits) into even and odd memories (256K × 32) according to an input order. Memory parallel processing method for motion compensation of high definition television. 휘도, 색차 신호를 분리하는 메모리 어드레스 사용방법에 있어서, U신호는 수직 어드레스의 최상위 비트 2비트와 수평어드레스 최상위 비트 1비트를 1로 하여 휘도, 색차신호를 분리하는 과정으로 이루어진 것을 특징으로 하는 고화질 텔레비전의 움직임 보상을 위한 메모리 병렬 처리방법.In the method of using a memory address for separating luminance and chrominance signals, the U signal comprises a process of separating luminance and chrominance signals by setting the most significant bit of the vertical address and the most significant bit of the horizontal address as 1 bit. Memory parallel processing method for motion compensation of television. 수평 어드레스 8 비트, 수직 어드레스 10 비트를 이용하여, 메모리에 휘도, 색차를 분리하도록 하는 메모리의 구조를 갖는 것을 특징으로 하는 고화질 텔레비전의 움직임 보상을 위한 메모리 병렬 처리장치.A memory parallel processing apparatus for motion compensation of a high-definition television having a structure of a memory for separating luminance and color difference into a memory by using a horizontal address 8 bits and a vertical address 10 bits. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027178A 1992-12-31 1992-12-31 Memory parallel processing method and apparatus for moving compensating of hdtv KR100243866B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920027178A KR100243866B1 (en) 1992-12-31 1992-12-31 Memory parallel processing method and apparatus for moving compensating of hdtv
JP5337989A JPH077725A (en) 1992-12-31 1993-12-28 Method of parallel processing and use of memory for movement compensation in high image quality television

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027178A KR100243866B1 (en) 1992-12-31 1992-12-31 Memory parallel processing method and apparatus for moving compensating of hdtv

Publications (2)

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KR940017875A true KR940017875A (en) 1994-07-27
KR100243866B1 KR100243866B1 (en) 2000-03-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030018605A (en) * 2001-08-30 2003-03-06 김희석 Memory interface and parallel processing for motion compensation of MPEG core

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030018605A (en) * 2001-08-30 2003-03-06 김희석 Memory interface and parallel processing for motion compensation of MPEG core

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