JPH077725A - Method of parallel processing and use of memory for movement compensation in high image quality television - Google Patents

Abstract

PURPOSE: To attain a high speed data processing faster than the highest processing speed of a memory by storing luminance signals and chrominance signals in the same memory by dividing four pixel units into even and odd memories according to an input sequence. CONSTITUTION: A memory part 250 gathers pixel unit inputs by four pixel units, and stores it in a unit memory for reducing the memory processing speed. Thus, the data processing speed of the memory 250 can be reduced by 1/4 compared with the case for storing the data by pixel units. However, it is necessary to add data extraction necessary for movement compensation, and the frame memory is divided into two parts according to the input sequence. That is, the four picture elements are stored in even and odd memories according to the input sequence of the data, and the data extraction necessary for movement estimation and display by four pixel units is operated by 8 pixel units. Thus, the data processing can be operated at a high speed faster than the highest processing speed of the memory for the movement compensation of a high quality television.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a motion compensation circuit design of high definition (High Definition Television Set) in which memories are arranged in parallel, and is capable of high-speed data processing faster than the maximum processing speed of the memory. The present invention relates to a memory parallel processing method and a memory using method for motion compensation of a high-definition television which can be manufactured by a memory.

[0002]

2. Description of the Related Art In the case of motion compensation of an image, a memory having a frame capacity is required because the image signal of the transfer frame is used.

The pixel processing speed of a high quality television is about 5
Although it is 0 MHz, when designing a motion compensation circuit that processes on a pixel-by-pixel basis, the memory processing speed is the pixel processing speed when considering memory storage, motion compensation, and display (in the case of a structure in which luminance and color difference signals are separated). Three times 150
Should be processed above MHz. However, it is impossible to manufacture a memory operated at such a high speed with the current technology.

Further, although a motion estimation and compensation method is widely used at present as a compression method of a digital video signal,
As an example, MPEG (Moving Picture Eyperts Grom)
p), HDTV (High Definition Television), multi-media (Multi-Media), etc. When the motion compensation circuit is implemented by hardware, data processing using memory is important.

Therefore, the structure and usage of the memory form the skeleton of the overall design, and how effectively the memory is used affects the design and manufacturing cost.

Generally, when the amount of data is small such as karaoke or MPEG phase 1, the data in pixel units is used by using the structure in which the luminance and color difference signals are separated according to the size of the data in the existing video memory or general-purpose memory. Although processing is possible, in the case of a high quality TV, data processing in pixel units is not possible due to the enormous amount of data.

That is, in the case of a video signal, one pixel is represented by an 8-bit digital video value. Therefore, in the case of a high quality TV, the data processing speed is 6 ns or less in order to store one frame and perform motion compensation processing. It requires more than 14 megabits of memory.

Therefore, although development of the memory of the currently required specifications is in progress, it is impossible to manufacture it in the near future due to technical problems. Therefore, the size of the general memory or the structure of the memory is changed. Adjusting the data processing speed by transforming is an important factor in design.

Further, when the brightness and the color difference are separately stored in separate memories due to the large difference in the data amount of the brightness and color difference signals, there is a disadvantage that the efficiency of the memory sharply decreases.

On the other hand, generally, in using a memory for motion compensation, a memory having a capacity of 2 frames is required. That is, the necessary data is extracted by the transfer frame memory using the motion bettor, the extracted image data and the difference image are added, and then stored in the current frame memory. In the case of a high-definition TV (HDTV), a memory of about 14 megabits or more is used per frame due to the enormous amount of data, but if 1 megamemory is used when manufacturing a decoder, a minimum of 28 memories is required. Yes, when using 4 mega memories, four for each frame, a total of eight or more are required.

Therefore, the motion compensation method using a memory having a capacity of 2 frames increases not only the cost of manufacturing the decoder but also the size of the PCB because the cost of the memory used for manufacturing the decoder increases. The problem of downsizing the size of the decoder also occurs due to the increase in size.

Further, there is a non-interlace high-definition TV capable of adding various effects on a still screen of an exhibition such as a museum or a museum.
It is known in Japanese Patent No. 97, but it is difficult to show a moving image by a technique using a buffer memory so that flicker can be eliminated while adding a rendering function to a still image.

[0013]

In order to solve such a problem, the present invention provides a method for processing data at a high speed faster than the maximum processing speed of the memory by configuring the memories in parallel.

[0014]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention relates to a method of using a memory in a motion compensation circuit structure of a high quality television, wherein four pixel units are converted into an even number memory and an odd number memory according to an input order. It is a memory parallel processing method for motion compensation of a high-definition television, characterized in that it is performed in a process of separately storing luminance and color difference signals in the same memory.

According to the present invention, the method of using the memory address in which the luminance and color difference signals are stored in the memory so that they can be separated is as follows.
In the case of the V signal, the luminance is set with the vertical address most significant bit 1 bit and the horizontal address most significant bit 2 bits being 1.
A memory parallel processing method for motion compensation of a high-definition television, which is characterized in that it is performed in the process of separating color difference signals.

Further, according to the present invention, a high-definition television having a structure of a memory for separating a luminance and a color difference of a memory by utilizing a horizontal address for luminance and a color difference of 8 bits and a vertical address of 10 bits. This is a memory parallel processing method for John's motion compensation.

The present invention for solving the above-mentioned object also provides
In compensating the motion of a high-definition television, parallel processing is performed using a memory for one frame, four pixel units are separated into even and odd memories according to the input order and stored, and a second memory is stored in a blank memory. A method of using a memory for motion compensation of a high-definition television, characterized in that a frame memory is stored and data can be processed with a memory capacity of one frame.

In the present invention, the memory storage method for the second frame stores the motion-compensated data by utilizing the empty space of the luminance and color difference signals, and the horizontal address generation is the same as the whole frame memory address generation method. However, the vertical address generation is characterized by adding the vertical address generated last in all frames together with the vertical address generated using the pointer and storing it in the memory. This is a method of using a memory for motion compensation of a television.

[0019]

The present invention configured as described above is intended to provide a method capable of high-speed data processing by using a currently available general-purpose memory, without separating luminance and color difference signals. By processing the memory in 8 stages in parallel, the speed required for data processing can be processed at a speed of about 27 MHz, which is 1/6 lower than in the case of a structure in which luminance and color difference signals are separated. It can be used for digital video signal processing that requires high-speed memory processing.

Further, it is possible to provide a motion compensation method in which the amount of memory used is reduced by half, and the motion compensation method is performed in which a memory for one frame capacity is used instead of the motion compensation method for manufacturing using a memory of two frame capacity. That is, when the frame memory is manufactured by hardware, the size of the manufactured memory is larger than the data amount of the luminance and color difference signals that are actually used for decoding. The memory is adapted to store data, and the memory does not separate the data according to the luminance and the color difference and processes the data in parallel in 8 steps in the order of the input data.

[0021]

[Embodiment] In the present invention, a memory is used according to brightness and color difference.
The data is processed in parallel in 8 steps in order of input data without separation, but the data processing speed of the memory is 35 ns.
Lower to a certain degree. The basic principle is to input 4 pixels
By storing the data collectively for each pixel, the data processing speed can be reduced by 1/4, and
By using the memory of 2 frame capacity to store and output data independently, the speed is reduced to 1/6 in total. However, when performing storage processing in units of 4 pixels,
Since additional data extraction necessary for motion compensation is required,
In the present invention, the frame memory is further divided into 2 depending on the input order.
It has a structure that divides it into two parts. Therefore, data is stored in the memory in units of 4 pixels, and data required for motion estimation and display is extracted in units of 8 pixels.

In order to manufacture the hardware of the present invention, first,
Determine the size of the frame memory. In the case of a high-definition TV, a luminance Y signal of about 1/30 seconds per frame is approximately 1.4 megabytes, and U and V signals of color difference signals are each 0.9 megabytes.

Therefore, 1Meg memory (256K
In the case of storing the data in a 32-bit data unit of 4 pixels in the memory by using (4), 16 memories are required for each frame.
Two memories are needed. The memory is configured to be stored in units of 32 bits of data, which is four pixels, in order to reduce the memory processing speed to 1/4 as described above, and eight 1 mega memories are connected in parallel. Is the same as.

Further, each frame memory is further divided into an odd number and an even number according to the input order, and the video signal of each frame is divided into two memories, an even number memory and an odd number memory, and stored.
As a result, the data processing speed is reduced to 1/6 in total by independently storing the data in the frame, motion compensation and outputting the video signal for the display. The memory calculation formula required for the frame memory production is as follows.

Size of video signal data used for one frame Y: 1408 × 960 = 1,351,680 Byte =
10,813,440 Bit U, V: 352 × 480 = 168,960 Byte =
1,351,680 Bit Size of even / odd memory data required for 4-pixel unit processing 1) Even memory data; Yeven + Ueven + Veven = 844,800
Byte = 6,758,400 Byte 2) Odd memory data; Yodd + Uodd + Vodd = 844,800 Byte
e = 6,758,400 Bites, odd and even memories required for hardware production = 1M Bit (256K ×
4 bit) × 8, total 2 frame memory = 1 mega memory is 32.

FIG. 1 is a circuit structure diagram for motion compensation of a high-definition TV, in which eight even and odd memories (256K × 32) having the same structure are connected in parallel and processed independently.

For example, the four pixels input first are stored in the even memory address 0, and the four pixels input subsequently are stored in the odd memory address 0.

Therefore, when addressing the memory at address 0, eight consecutive pixels can be obtained. At this time, in the case of a memory of 1 megabit (256K × 4), the memory is controlled by using a total of 18 memory address buses. In the present invention, 10 of the 18 memory addresses are vertical addresses and 8 of them are vertical addresses. Used as horizontal address.

Further, as described above, in the present invention, since the luminance and the color difference signals are stored in the same memory, the even number of frames,
It is necessary to separate the luminance and color difference signals stored in the odd memory. Therefore, each even and odd memory (256K
X32) is separated into luminance and color difference signals by a memory structure as shown in FIG. FIG. 3 shows the brightness like the memory structure of FIG.
In the memory address usage method for separating the color difference signals, the U signal has 1 most significant bit of the vertical address as 0, and the U signal has 1 most significant bit of the vertical address and 2 most significant bits of the horizontal address.

As another example of parallel processing of the memory in eight stages without separating the luminance and color difference signals of the present invention, FIGS.
Can be illustrated. FIG. 4 is a circuit diagram showing another example of the present invention, which includes an address controller (100) for instructing input / output of data to / from a memory unit (250) using a motion Victor and a control signal; A memory unit (250) for separately storing the video signal of the memory into even and odd memories; and a memory unit (25
0) The 1/0 controller (400) controlling the input / output of the memory data; and the address controlled by the 1/0 controller (400) so that the memory data of the memory section (250) can be extracted and displayed. A display control (500) for controlling; and a motion compensating unit (600) for extracting the separated frame data, adding it to a difference image (DCT coefficient) and converting it to an image signal.

The basic memory structure of the memory unit (250) is to reduce the processing speed of the memory.
First, the input in pixel units is collected into four pixel units and stored in the unit memory.

As a result, the data processing speed of the memory unit (250) is ¼ lower than that in the case of storing and processing in pixel units, but since data extraction necessary for motion compensation is additionally required, the frame memory is further input. It has a structure divided into two according to the order.

That is, four pixels are divided into even-numbered memory and odd-numbered memory according to the data input order and stored. In this way, data is stored in units of 4 pixels, and data extraction necessary for motion estimation and display is 8 pieces. This is performed for each pixel.

For example, when four input pixels are stored in the even-numbered memory address 0, four pixels input next are stored in the odd-numbered memory address 0, and the address 0 memory is addressed continuously. It is possible to obtain 8 pixels.

In the case of a high quality TV, the 1/30 second frame luminance Y signal is approximately 1.4 megabytes, and the color difference signals U and V
Each signal uses 0.9 megabyte.

Therefore, 1Meg memory (256K
In the case of storing a 32-bit data unit of 4 pixels in a memory by using (4), it is the same as a parallel connection of 8 horizontal and vertical 1 mega memories. A total of 16 memories are used.

The memory structure of the memory unit (250) is based on the frame memory structure shown in FIG. 2, but a space is used in the memory. At this time, if there is a blank, the amount of memory used for manufacturing the decoder is about 20% or more larger than the amount of luminance and color difference signal data used for actual decoding.

As an example, as shown in FIG. 5, a memory blank of 64 lines is generated in the case of the luminance signal in the vertical direction, and a memory blank of 32 lines is generated in the case of the U and V signals.

The present invention is a system for sequentially storing the motion-compensated current frame data in a memory blank which is not used as described above. The detailed method is as follows.

1) First, the luminance and color difference signal data of the first frame are stored as in the memory structure of FIG. Also, the storage speed in the memory and the output speed of the memory for the display should be the same as the processing speed in units of pixels.

2) When the data processing of the first frame is completed, the motion-compensated data is stored from the second frame using the empty space of the luminance and color difference signals of FIG.
At this time, the horizontal address generation of the memory output for memory storage, motion compensation and display is controlled by the same method as the memory address generation method in 1) above, and the vertical address generation is also controlled in 1) above. It is generated by the same method as the memory address generation method, but the vertical address generated last in 1) above is added every time together with the vertical address generated using the pointer. When the empty space of the vertical address of the luminance and color difference signals of the memory is completely filled, it is used by being overlapped with the vertical address at the beginning of the memory as shown in FIG.

3) When the data processing of the second frame is completed, the data processing of the third frame sequentially stores data in the memory space of FIG. The data processing of etc. is the same as 2) and 3).

[0043]

As described above, when the present invention is used, the memory is processed in eight stages in parallel without separating the luminance and color difference signals to separate the luminance and color difference signals at the speed required for data processing. By the data processing method at a speed 1/6 lower than that of the above structure, it becomes possible to manufacture high-speed data processing faster than the maximum processing speed of the memory even with the existing general-purpose memory, as in the high-quality TV.

Further, according to the present invention, in the use of the memory for processing the memory in 8 stages and 8 parallels, the use of the memory can be improved by utilizing the space outside the data space used for the two actual decoding and utilizing it for the data storage space. Therefore, it is possible to reduce the cost of manufacturing the decoder and reduce the size of the decoder.

[Brief description of drawings]

FIG. 1 is a circuit structure diagram for motion compensation of a high quality TV.

FIG. 2 is a memory structure diagram of the present invention (256K × 32).

FIG. 3 is a diagram showing a memory address usage diagram for separating luminance and color difference signals according to the present invention.

FIG. 4 is a structural diagram of a motion compensation circuit showing another example of the present invention.

FIG. 5 is an exemplary diagram of a memory used for processing luminance and color difference signals according to the present invention.

FIG. 6 is an exemplary view of a memory illustrating a memory storage process of a second frame according to the present invention.

[Explanation of symbols]

 100 ... Address controller 250 ... Memory section 400 ... Controller 500 ... Display controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Lee Jin-saku, 217, 4 Kurata, Icheon-eup, Icheon-gun, Gyeonggi-do, Republic of Korea (72) Inventor ▲ Kei ▼ Min Songpa-gu Goto-dong Ivory Part 9 Seoul, Republic of Korea -706

Claims (5)

[Claims] 1. A method of using a memory in a motion compensation circuit structure of a high-definition television, wherein four pixel units are divided into even-numbered memory and odd-numbered memory according to an input order and luminance and color difference signals are stored in the same memory. A memory parallel processing method for motion compensation of a high-definition television characterized by the above. 2. A method of using a memory address for storing luminance and chrominance signals in a memory so that they can be separated, the U signal is set to 0 for the most significant bit of the vertical address, and the V signal is for 1 bit of the most significant bit of the vertical address. 2. The memory parallel processing method for motion compensation of a high-definition television according to claim 1, which is performed in the process of separating the luminance and color difference signals by setting the two most significant bits of the horizontal address to 1. 3. A horizontal address for luminance and color difference is 8 bits,
2. The memory parallel processing method for motion compensation of a high quality television according to claim 1, wherein the vertical address has a memory structure for separating memory luminance and color difference using 10 bits. 4. In compensating the motion of a high-definition television, parallel processing is performed using a memory for one frame, four pixel units are separated into even and odd memories according to the input order, and storage processing is performed. A method of using a memory for motion compensation of a high-definition television, characterized in that the memory of the second frame is stored in the memory of the above so that the data can be processed with the memory capacity of one frame. 5. The second frame memory storage method stores the motion-compensated data by utilizing the empty space of the luminance and color difference signals, and the horizontal address generation is the same as the full frame memory address generation method. 5. The method of controlling the vertical address generation according to claim 4, wherein the vertical address generation is performed by adding the vertical address generated last in the entire frame together with the vertical address generated using the pointer and storing the result in the memory. Memory usage for motion compensation in high definition television.