KR940017254A - Variable length decoding apparatus and method - Google Patents

Variable length decoding apparatus and method Download PDF

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Publication number
KR940017254A
KR940017254A KR1019920026038A KR920026038A KR940017254A KR 940017254 A KR940017254 A KR 940017254A KR 1019920026038 A KR1019920026038 A KR 1019920026038A KR 920026038 A KR920026038 A KR 920026038A KR 940017254 A KR940017254 A KR 940017254A
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South Korea
Prior art keywords
bit
variable length
code word
length decoding
memory
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KR1019920026038A
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Korean (ko)
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KR960008744B1 (en
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김경진
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배순훈
대우전자 주식회사
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Priority to KR92026038A priority Critical patent/KR960008744B1/en
Publication of KR940017254A publication Critical patent/KR940017254A/en
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Publication of KR960008744B1 publication Critical patent/KR960008744B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

본 발명은 가변길이 복호화 장치에 관한 것으로서, 본 발명에 따른 가변길이 복호화 장치는 가변길이 부호화되어 입력되는 비트열로부터 부호어(code word)를 분리하여 상기 부호어를 가변길이 복호화시키는 것으로서, 상기 부호어를 어드레스로 사용하기 위하여 상기 부호어에 대응된 가변길이 복호화를 위한 테이블을 저장하고 있는 메모리와, 다수의 부호어들로 이루어진 상기 비트열로부터 각각의 부호어중에서 최초의 비트 1를 검출하고, 상기 비트 1 이전의 비트 0들로서 상기 메모리의 상위 어드레스를 발생시키고, 상기 0비트들의 수에 따라 기설정된 상기 비트 1 이후의 비트들로 상기 메모리의 하위 어드레스를 발생시키는 어드레스 발생수단을 포함한다.The present invention relates to a variable length decoding apparatus. The variable length decoding apparatus according to the present invention is to perform variable length decoding on a code word by separating a code word from a bit string that is input by variable length encoding. A first bit 1 of each code word is detected from a memory having a table for variable length decoding corresponding to the code word to use the word as an address, and the bit string consisting of a plurality of code words, Address generating means for generating an upper address of the memory as bit 0s before the bit 1 and generating a lower address of the memory with bits after the bit 1 preset according to the number of the 0 bits.

Description

가변길이 복호화 장치 및 방법Variable length decoding apparatus and method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 재배치된 VLC 부호어 테이블을 도시하는 도면, 제2도는 본 발명에 따른 가변길이 복호화 장치의 블록도, 제3도는 비트 1 검출 및 유지부의 회로도.1 is a diagram showing a rearranged VLC codeword table according to the present invention, FIG. 2 is a block diagram of a variable length decoding apparatus according to the present invention, and FIG. 3 is a circuit diagram of bit 1 detection and holding unit.

Claims (2)

가변길이 부호화되어 입력되는 비트열로부터 부호어(code word)를 분리하여 상기 부호어를 가변길이 복호화시키는 것으로서, 상기 부호어를 어드레스로 사용하기 위하여 상기 부호어에 대응된 가변길이 복호화를 위한 테이블을 저장하고 있는 메모리와, 다수의 부호어들로 이루어진 상기 비트열로부터 각각의 부호어중에서 최초의 비트 1를 검출하고, 상기 비트 1 이전의 비트 0들로서 상기 메모리의 상위 어드레스를 발생시키고, 상기 0비트들의 수에 따라 기설정된 상기 비트 1 이후의 비트들로 상기 메모리의 하위 어드레스를 발생시키는 어드레스 발생수단을 포함하는 가변 길이 복호화 장치.A variable length decoding is performed by separating a code word from a bit string input by variable length coding and inputting the code word. A table for variable length decoding corresponding to the code word is used to use the code word as an address. A first bit 1 of each code word is detected from the stored memory and the bit string consisting of a plurality of code words, and the upper address of the memory is generated as bit 0s before the bit 1, and the 0 bit And address generating means for generating a lower address of the memory with bits set after the bit 1 according to the number of bits. 가변길이 부호어에 대응된 가변길이 복호화를 위한 테이블을 이용하여, 가변길이 부호화되어 입력되는 비트열로부터 부호어(code word)를 분리한 후, 상기 부호어를 가변길이 복호화시키는 것으로서, 다수의 부호어들로 이루어진 상기 비트열로부터 각각의 부호어중에서 최초의 비트 1를 검출하는 단계와; 상기 비트 1 이전의 비트 0들로서 상기 메모리의 상위 어드레스를 발생시키는 단계와; 상기 0비트들의 수에 따라 기설정된 상기 비트 1 이후의 비트들로 상기 메모리의 하위 어드레스를 발생시키는 단계를 포함하는 가변 길이 복호화 방법.By using a table for variable length decoding corresponding to a variable length codeword, separating codewords from a bit string input by variable length encoding and then variable length decoding the plurality of codes. Detecting the first bit 1 of each code word from the bit string consisting of words; Generating an upper address of the memory as bit 0s prior to the bit 1; And generating a lower address of the memory with bits after bit 1 preset according to the number of 0 bits. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92026038A 1992-12-29 1992-12-29 Variable length decoding apparatus and method KR960008744B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92026038A KR960008744B1 (en) 1992-12-29 1992-12-29 Variable length decoding apparatus and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92026038A KR960008744B1 (en) 1992-12-29 1992-12-29 Variable length decoding apparatus and method

Publications (2)

Publication Number Publication Date
KR940017254A true KR940017254A (en) 1994-07-26
KR960008744B1 KR960008744B1 (en) 1996-06-29

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