KR940012857A - Two-Step Parallel Analog-to-Digital Converter - Google Patents

Two-Step Parallel Analog-to-Digital Converter Download PDF

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Publication number
KR940012857A
KR940012857A KR1019920022276A KR920022276A KR940012857A KR 940012857 A KR940012857 A KR 940012857A KR 1019920022276 A KR1019920022276 A KR 1019920022276A KR 920022276 A KR920022276 A KR 920022276A KR 940012857 A KR940012857 A KR 940012857A
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KR
South Korea
Prior art keywords
adc
reference voltage
digital data
voltage set
digital
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KR1019920022276A
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Korean (ko)
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KR950004642B1 (en
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최명준
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김광호
삼성전자 주식회사
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Priority to KR1019920022276A priority Critical patent/KR950004642B1/en
Publication of KR940012857A publication Critical patent/KR940012857A/en
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Publication of KR950004642B1 publication Critical patent/KR950004642B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

이 발명의 투스텝 병렬 아날로그/디지탈 변화기 (Two step parallel A/D converter)는 아날그 입력신호를 제1기준전압세트와 비교하여 상위 비트에 해당하는 디지탈 데이타를 출력하는 상위 ADC와, 아날로그 입력신호를 제2기준전압세트와 비교하여 하위 비트에 해당하는 디지탈 데이타 및 에러 교정을 위한 디지탈 신호를 출력하는 하위ADC와, 상기 상위ADC에 제1기준전압세트를 제공하여 주고 상기 상위 ADC의 디지탈 데이타 출력에 따라 상기 하위 ADC에 제2기준전압세트를 제공하여 주는 기준전압부와, 상기 상위 ADC의 상위 비트 디지탈 데이타출력과 상기 하위 ADC의 하위 비트 디지탈 데이타 출력을 상기 에러교정을 위한 디지탈 신호에 의해 결합하여 최종 디지탈 데이타 출력을 만들어 주는 디지탈 신호 결합부로 구성되어, 하나의 하위 ADC만으로 매 클럭 주기마다 디지탈 출력을 얻는 투스텝 ADC를 제작할 수 있으므로 전체 칩 면적을 줄일 수 있고, 입력 오프셋에 의한 ADC특성 열화를 최소화할 수 있다.The two-step parallel A / D converter of the present invention compares an analog input signal with a first reference voltage set and outputs an upper ADC that outputs digital data corresponding to the upper bits, and an analog input signal. Compared to the second reference voltage set, the lower ADC outputs the digital data corresponding to the lower bits and the digital signal for error correction, and provides the first reference voltage set to the upper ADC to provide the digital data output of the upper ADC. Accordingly, the reference voltage unit providing the second reference voltage set to the lower ADC, the upper bit digital data output of the upper ADC and the lower bit digital data output of the lower ADC are combined by the digital signal for error correction. It consists of a digital signal combiner that produces the final digital data output. So to create a two-step ADC to obtain a digital output and to reduce the overall chip area, it is possible to minimize the ADC characteristic deterioration due to the input offset.

Description

투 스텝 병렬 아날로그/디지탈 변환기Two-Step Parallel Analog-to-Digital Converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 이 발명에 따른 투스텝 병렬 아날로그/디지탈 변환기이다.3 is a two-step parallel analog / digital converter according to this invention.

Claims (4)

아날로그 입력신호를 제1기준전압세트와 비교하여 상위 비트에 해당하는 디지탈 데이타를 출력하는 상위 ADC와, 아날로그 입력신호를 제2기준전압세트와 비교하여 하위 비트에 해당하는 디지탈 데이타 및 에러 교정을 위한 디지탈 신호를 출력하는 하위ADC와, 상기 상위 ADC에 제1기준전압세트를 제공하여 주고 상기 상위 ADC의 디지탈 데이타 출력에 따라 상기 하위 ADC에 제2기준전압세트를 제공하여 주는 기준전압부와, 상기 상위 ADC의 상위 비트 디지탈 데이타 출력과 상기 하위 ADC의 하위 비트 디지탈 데이타 출력을 상기 에러교정을 위한 디지탈 신호에 의해 결합하여 최종 디지탈 데이타 출력을 만들어 주는 디지탈 신호 결합부로 구성된 것을 특징으로 하는 투스텝 병렬 아날로그/디지탈 변환기.The upper ADC outputs the digital data corresponding to the upper bits by comparing the analog input signal with the first reference voltage set, and the digital data and error correction corresponding to the lower bits by comparing the analog input signal with the second reference voltage set. A lower ADC that outputs a digital signal, a reference voltage unit providing a first reference voltage set to the upper ADC and a second reference voltage set to the lower ADC according to the digital data output of the upper ADC; A two-step parallel analog / coupling unit comprising a digital signal combiner that combines the upper bit digital data output of the upper ADC and the lower bit digital data output of the lower ADC by the digital signal for error correction to produce the final digital data output. Digital converter. 제1항에 있어서, 상기 상위 ADC는, 아날로그 입력신호 및 제1기준전압세트가 인가되는 다수개의 코스 샘플링 증폭기와, 상기 다수개의 코스샘플링 증폭기와 각각 직렬연결된 다수개의상위 래칭비교기와, 상기 다수개의 상위 래칭비교기와 연결된 상위 엔코더로 구성된 것을 특징으로 하는 투스텝 병렬 아날로그/디지탈 변환기.The apparatus of claim 1, wherein the upper ADC comprises: a plurality of coarse sampling amplifiers to which an analog input signal and a first reference voltage set are applied; a plurality of upper latching comparators connected in series with the plurality of cos sampling amplifiers; A two-step parallel analog / digital converter comprising an upper encoder connected to an upper latching comparator. 제1항에 있어서, 상기 하위 ADC는, 아날로그 입력신호 및 제2기준전압세트가 각각 인가되는 다수개의 제1 및 제2파인 샘플링 증폭기와, 각각 직렬 연결된 다수개의 아날로그 멀티플렉서와, 상기 아날로그 멀티플렉서와 각각 직렬연결된 다수개의 하위 래칭비교기와, 상기 다수개의 하위 래칭 비교기와 연결된 엔코더로 구성된 것을 특징으로 하는 투스텝 병렬 아날로그/디지탈 변환기.The method of claim 1, wherein the lower ADC includes a plurality of first and second wave sampling amplifiers to which an analog input signal and a second reference voltage set are respectively applied, a plurality of analog multiplexers connected in series, and the analog multiplexer, respectively. 2. A two-step parallel analog / digital converter comprising a plurality of lower latching comparators in series and an encoder connected to the plurality of lower latching comparators. 제1항에 있어서, 상기 상위 ADC가 N보다 작은 정수 n비트의 해상도를 갖고, 상기 하위 ADC가 N-n+α(α는 0보다 큰 임의의 수)의 해상도를 가지며, n비트의 상위 ADC출력과(N-n+α)비트의 하위 ADC출력을 조합하여 N비트의 디지탈 출력을 얻도록 구성된 것을 특징으로 하는 투스텝 병렬 아날로그/디지탈 변환기.2. The upper ADC of claim 1, wherein the upper ADC has a resolution of integer n bits less than N, the lower ADC has a resolution of N-n + α (α is any number greater than 0) and the upper ADC of n bits. A two-step parallel analog / digital converter, characterized in that it combines the output and the lower ADC output of (N-n + α) bits to obtain N bits of digital output. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920022276A 1992-11-25 1992-11-25 Two step analog/digital converter KR950004642B1 (en)

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Application Number Priority Date Filing Date Title
KR1019920022276A KR950004642B1 (en) 1992-11-25 1992-11-25 Two step analog/digital converter

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Application Number Priority Date Filing Date Title
KR1019920022276A KR950004642B1 (en) 1992-11-25 1992-11-25 Two step analog/digital converter

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KR940012857A true KR940012857A (en) 1994-06-24
KR950004642B1 KR950004642B1 (en) 1995-05-03

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KR20150020849A (en) 2013-08-19 2015-02-27 에스케이하이닉스 주식회사 Non-volatile memory apparatus, semiconductor system and computer device using the same

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