KR940011279B1 - Random data oscillating circuit using random noise - Google Patents

Abstract

The random data generating circuit converts original data into random data using random noise. As a sender transmits data encoded random data and a receiver decodes random data to extract original data, the circuit protects destruction or effluence of data. The circuit is composed of a random noise generator (10) that create random noise signal using breakdown phenomenon of a Zener diode and operation of a transistor, an amplifier (20), a sampling block (30), a serial/parallel converter (40) and a buffer (50).

Description

Random data generation circuit using random noise

1 is a circuit diagram according to the present invention.

2 to 4 are waveform diagrams according to the present invention.

5 is a waveform diagram according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: random noise generating means 20: amplification means

30: sampling means, 40: serial and parallel conversion means

50: buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to circuits for coding data in data transmission and communication systems, and more particularly to a random data generation circuit that changes one data into random data using random noise.

In general, data communication is performed by wireless or wired communication, and information is exchanged with each other. As a result, in the case of mutual data communication, other people have the opportunity to leak their communication contents, and they are actually mobilizing various equipment.

The layer for performing the data communication may also be various, and if necessary, it may be possible to communicate the contents that are enormously lost when someone leaks the contents of the communication. In this case, both communicators change their data using ciphers or notes, and with the changes of the times, they have introduced coding methods that do not have to be done manually.

However, the rapid development of electronic equipment has made it possible to decode by others, and accordingly, a coding method that is harder to be decoded by others has been required.

Accordingly, in the present invention, the data to be transmitted is wrapped in random data, and the receiving side removes the random data and extracts one data, thereby providing a circuit which can prevent unspecified data destruction or data leakage. I am doing it.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, which includes random noise generating means (10) for generating and outputting a random random noise signal using a breakdown phenomenon of a zener diode and an operation of a transistor, and the random noise generating means (10). Amplifying means 20 for receiving and amplifying the output, and sampling means 30 for sampling and converting the digital data provided by the data transmission and communication system into a random noise signal amplified by the amplifying means 20 when the output is input. And serial-to-parallel conversion means (40) for converting the output of the sampling means (30) into parallel data in synchronization with the inverted output of the amplification means (20), and outputting the output of the serial-to-parallel conversion means (40). And a buffer 50 which is latched by the latch signal RH provided from the control unit of the transmission and communication system and output to the control unit.

The random noise generating means 10 includes a variable resistor R1 connected to a supply power source B +, a capacitor C1 connected to a variable resistor R1 on one side and grounded on the other side, and a variable resistor R1. The capacitor C1 is composed of a transistor Q1 connected in parallel through a resistor R2 and an emitter is grounded, and a zener diode D1 connected between the base of the transistor Q1 and the variable resistor R1. do. An output line between the transistor Q1 and the resistor R2 is connected to the amplifying means 20.

In addition, the sampling means 30 is a four-type orphan connected to the D-type flip-flop 31 and the output terminal of the output terminal (Q1, Q2, Q3, Q4, Q5) of the D-type flip-flop 31 It consists of gates 32-35.

The output terminal Q1 of the D-type flip-flop 31 is connected to the input terminal D2, the output terminal Q2 of the D-type flip-flop 31 is connected to the input terminal D3, and the output terminal of the D-type flip-flop 31 is Q3 is connected to the input terminal D4. In addition, the output terminal Q4 of the D-type flip-flop 31 is connected to the input terminal D5. Meanwhile, the first exclusive orifice 33 is connected to the output terminals Q1 and Q2 of the D-type flip-flop 31, and the second exclusive o-gate 32 is the D-type flip-flop 31. Is connected to the output terminals (Q3) and (Q4) of the third exclusive oragate 34 is connected to the output terminal of the first exclusive oragate 33 and the second exclusive oragate (32) have. The fourth exclusive orifice 35 is connected to the output of the third exclusive orifice 34 and the output terminal Q5 of the D-type flip-flop 35.

The present invention in the above-described configuration will be described in detail one embodiment.

First, when power is supplied to each part, the variable resistor R1 of the random noise generating means 10 is adjusted so that about 10V is applied to the cathode of the zener diode D1. At this time, the zener diode D1 of the random noise generating means 10 has a breakdown phenomenon and the transistor Q1 is turned on so that the collector becomes a low potential, and thus the power supply B + is grounded through the resistor R2. Will flow into. At this time, the cathode potential of the control diode D1 is lowered again so that no breakdown occurs, and the transistor Q1 is turned off in the turned-on state, and the collector potential becomes high again. At this time, the zener diode D1 breaks again, and the random noise generating means 10 repeats such an operation.

Through this operation, random noise of the zener diode D1 appears in the base of the transistor Q1 in the form of a second degree. The transistor Q1 of FIG. 1 operates when the signal is shifted from the ground level to a signal higher than the predetermined level (0.7 V) in the waveform shown in FIG. The signal output through the collector of the transistor Q1 is a random random noise signal and is supplied to the amplifying means 20. The amplification means 20 is the random noise signal and is supplied to the amplification means 20. The amplifying means 20 amplifies the random noise signal and outputs an amplified random noise signal having the same shape as that of the third degree. The random noise signal is applied to the clock stage CLK of the D-type flip-flop 31 in the sampling means 30. At this time, the input data CK of the data transmission and communication system is applied to the input terminal D1 of the D-type flip-flop 31.

The input / output waveform diagram of the sampling means 30 is shown in detail in FIG.

Referring to FIG. 5, when the data CK to be converted is input to the input terminal D1 of the D-type flip-flop 31, the D-type frill flop 31 is amplified from the amplifying means 21. In response to the rising edge of the random noise signal, the data CK is sampled and output to the output terminal Q1. The signal output to the output stage Q1 is again input to the input terminal D2 of the D-type flip-flop 31, and the signal of the input terminal D2 is output to the output terminal Q2 in response to the rising edge of the next amplified random noise signal. Is passed). In the D-type flip-flop 31, the sampled signals output from the output terminal are sequentially input to the input terminals D3, D4, and D5, and output to the output terminals Q3, Q4, and Q5. At this time, it can be seen that the signals output from the output terminals Q1 to Q5 become sampling signals whose pulse width and period are not constant as shown in FIG. 5. However, the signals output from the D-type flip-flop 31 may have a constant pattern as shown in FIG. 5, the width of the pulse may be limited, and the number of high and low sections may be limited.

The exclusive orifices 32 to 35 of the sampling means 30 eliminate random patterns, increase the number of highs and lows, and also control the length of the pulse width. Generate a signal.

The first exclusive orifice 33 exclusively ORs the sampling signals of the output terminals Q1 and Q2 and the second exclusive orifice 32 exclusively the sampling signals of the output terminals Q3 and Q4. Logical OR. The third exclusive orifice 34 exclusively ORs the output of the first exclusive oragate 33 and the output of the third exclusive oragate 32 and outputs the fourth exclusive oragate. Reference numeral 35 exclusively ORs the outputs of the third exclusive orifice 34 and the output terminal Q5 of the D flip-flop 31. Signals output from the exclusive orifices 32 to 35 can be seen in FIG.

As a result, the data CK to be converted is output by the random noise signal of the random noise generating means 10 as shown in FIG. 4 and the output signal of the fourth exclusive ogate 35 shown in FIG. It is converted and printed as follows. This output signal is supplied to the serial-to-parallel conversion means 40.

The serial-parallel conversion means 40 receives the random noise signal of the random noise generating means 10 and inverts it to the inverter 41, and then shifts the output of the sampling means 30 several times by using it as a clock to parallel data. Convert. This signal is finally supplied to the buffer 50. The signal input to the buffer 50 is selected by the input latch signal RH applied from the control unit of the data transmission and communication system and is read into the control unit as parallel data DT by the read signal. The data DT read to the controller may be used differently depending on the application, and may be used and discarded once in the controller, or may be backed up in memory and used continuously.

As described above, the present invention has the advantage that it is possible to convert the input data so that others do not leak by random noise without using a lot of circuit elements and without being cumbersome as in software.

Claims (4)

A circuit for converting information data so that no data is leaked by a person other than a communicator during communication using a data communication system, comprising: random noise generating means for generating a random noise signal by an oscillation element to which a predetermined power supply is applied; Sampling means for sampling the information data in response to the random noise signal and converting the data into random data; and serial-to-parallel conversion means for converting and outputting the random data into parallel data in response to the random noise signal; And latch means for latching the parallel data to the controller by a latch signal applied from the controller to the data communication system. The method of claim 1, wherein the random noise generating means is connected between a variable resistor (R1) and a capacitor (C1) between the power supply (B +) and the ground, and one side of the zener diode (D1) to the variable resistor (R1) The other side of the zener diode D1 is connected to the base of the transistor, and the resistor R2 and the collector and emitter of the transistor are connected in series between the variable resistor R1 and the ground. Random data generation circuit using random noise. 2. The apparatus of claim 1, wherein the sampling means comprises: random information data generating means for sampling the information data by the random noise signal and outputting first random information data, and performing a logical operation on the first random information data to perform a second operation. A random data generation circuit using random noise, characterized by comprising logical operation means for outputting random information data. The random using random noise according to any one of claims 1 to 3, further comprising an amplifying means positioned between the random noise generating means and the sampling means and amplifying the random noise signal. Data generation circuit.

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