KR940010835B1 - Integrated circuit - Google Patents

Abstract

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Description

Integrated circuit

1 is a block diagram of a RAM to which the present invention is applied;

2 is a circuit diagram showing the circuit configuration of the main part of a word line driving circuit according to an embodiment of the present invention;

3 is a circuit diagram showing an example of a reference potential generating circuit in the circuit shown in FIG.

4 is a circuit diagram showing a charge pump circuit for generating a control signal supplied to a charging transistor in the booster circuit shown in FIG.

5 is a timing chart showing a pulse sequence for operation of the embodiment shown in FIGS.

FIG. 6 is a graph showing the potential of the power supply voltage Vcc for a word line versus some voltages in the circuit shown in FIG.

7 and 8 are circuit diagrams showing another example of the configuration of the word line boost voltage generation circuit in the circuit shown in FIG.

9 is a graph showing the power supply voltage Vcc versus the potential of some voltages in the circuits shown in FIGS. 7 and 8;

10 is a circuit diagram showing the circuit configuration of the main part of the word line driving circuit according to another embodiment of the present invention;

11A to 11F show a circuit diagram showing some suitable circuit configurations that can be provided as the reference voltage generation circuit shown in FIG.

12 is a graph showing the potential of the threshold voltage with respect to the thickness of the gate insulating film in the embodiments shown in FIGS. 10 and 11;

13A to 13D show a circuit diagram showing some suitable circuit examples which can be provided as other reference voltage generating circuits in FIG.

14 is a graph showing the output voltage of the power supply voltage Vcc versus the voltage generating circuit in the above embodiment;

15 is a graph showing the power supply voltage Vcc vs. the first reference voltage Vr1 in the above embodiment;

FIG. 16 is a three-dimensional graph showing characteristic curves of FIG. 15 against variations in gate insulating film thickness and threshold voltage resulting from variations in the DRAM manufacturing process; FIG.

17 is a graph showing a power supply voltage Vcc vs. a word line voltage Vwd according to the embodiment;

18 is a block diagram showing a leakage compensation circuit according to a third embodiment of the present invention in accordance with one of the first and second embodiments of the present invention;

19 is a circuit diagram showing the internal circuit configuration of the comparison circuit shown in FIG. 18;

20 is a circuit diagram showing the internal circuit configuration of the ring oscillation circuit shown in FIG.

FIG. 21 is a circuit diagram showing an example of the circuit configuration of the comparison circuit in FIG.

* Explanation of symbols for main parts of the drawings

12: memory cell array unit 14: row decoder

16: hanger address buffer 18: thermal decoder

20: open dress buffer 24: RA control circuit

26: booster 28: CA control circuit

62: comparator 64: ring oscillation circuit

66: charge pump circuit

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated semiconductor memory device, and more particularly, to a DRAM having a circuit arrangement for generating a boost voltage for word line driving.

[Traditional Technology and Problems]

In recent years, as the need for high-performance and high-reliability digital computer systems increases, there is a strong demand for the development of semiconductor memories having large capacities. On the other hand, DRAM designs have also been developed in accordance with the above-described trends. Currently, useful DRAMs have memory cell arrays arranged in row and column directions, and each memory cell is composed of only insulated gate transistors such as capacitors and MOSFETs. . Here, the capacitor functions as a data storage element, and the transistor functions as a data transfer gate associated with the capacitor.

The parallel data transmission line is connected to the current transfer music of the cell transistors of the memory cell row, and the parallel control line is coupled with the control electrode of the memory cell row. When an integral control line is activated and an arbitrary data transmission line is selected, The transistor in one memory cell is brought into a conductive state, and digital information from the corresponding data transfer line is transferred to the cell capacitor and stored in the selected memory cell. Here, the data transmission line is usually called a bit line, and the control line is called a word line.

The voltage "H" supplied to the control electrode of the transfer gate transistor through the word line should be addressed so as to be higher than the "H" information voltage at the bit line at its potential level. This difference voltage is the transfer gate of the memory cell. This is because it is necessary to ensure the potential drop of the word line driving voltage due to the threshold value of the transistor. This "H" voltage is generated by using a specific capacitor installed in a drive circuit connected to a word line, which is a "booting" or bootstrap capacitor that generates a drive voltage higher than the DRAM supply voltage. Acts as.

Usually, one end of the bootstrap capacitor is precharged with the power supply voltage, and then the readout potential is generated by driving the other end with the power supply voltage from the ground voltage. In such a boosting method, the dependence on the power supply voltage between the bit line "H" level voltage and the word line "H" level voltage is different. That is, the rate of change of the word line "H" level voltage at the time of power supply voltage change is larger than the rate of change of the bit line "H" level voltage. For example, the power supply voltage Vcc is the minimum operation guarantee voltage Vccmin and the maximum operation guarantee voltage Vccmax. When the voltage fluctuates within the allowable fluctuation range defined by), the word line "H" level voltage increases more rapidly than the increase of the bit line "H" level voltage. As a result, the difference between these voltages cannot be maintained at a constant value.

If the difference value with respect to the minimum allowable potential Vccmin of the power supply voltage is designed to the desired value, the word line "H" level voltage exceeds the limit when the power supply voltage is increased to be Vccmax. This causes more stress than necessary to the gate insulating film of the cell transistor, and in the worst case, the cell transistor is dielectrically broken. Such malfunctions are commonly referred to as time dependent dielectric breakdown (TDDB). On the other hand, to avoid this, on the contrary, if the difference value with respect to the maximum allowable potential of the power supply voltage (VccMAX) is designed to the desired value, the word line "H" level voltage is the bit line "H when the power supply voltage is reduced to Vccmin. "It is impossible to hold a potential higher than necessary for the level voltage. This becomes insufficient or impossible to guarantee the lowering of the threshold value in the memory cell serving as the transfer gate of the word line driving voltage. As a result, the write performance of the "H" level data in the DRAM is reduced.

In the conventional DRAM, since the memory density is relatively low, the above-described TDDB problem has not been considered as a large problem. That is, when the integration degree of the memory cells is low, the size of each memory cell can be designed relatively large, so that the thickness of the gate insulating film can be designed thick. When the thickness of the gate insulating film is increased, the insulation breakdown voltage of the cell transistor becomes high enough to absorb an excessive increase in the word line driving voltage when the power supply voltage Vcc is changed to the maximum allowable value Vccmax.

However, with the recent increase in the degree of integration of DRAM, the above-mentioned matters are not accepted. That is, as the number of bits in the DRAM increases, the cell size decreases, so that the thickness of the gate oxide film is reduced and the magnitude of the voltage at which the breakdown of the transfer gate transistor in each cell occurs is essentially reduced. Therefore, it becomes very difficult to maintain higher operation reliability while preventing the occurrence rate of TDDB in the cell transistor over the entire allowable variation range of the power supply voltage Vcc. And this is a serious problem for semiconductor manufacturers because it is a serious obstacle in developing more integrated DRAM.

[Purpose of invention]

Accordingly, the present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device having excellent operation performance and reliability in which the above problems are improved.

[Configuration of Invention]

The present invention for realizing the above object is an integrated circuit used in a semiconductor memory device having an array of rows and columns of memory cells associated with bit lines and word lines, wherein the " H " level of digital information is selected in the selected word lines of the word lines. First voltage generating means for generating a word line driving voltage Vwd high enough to enable writing; A second voltage generating means connected to the first voltage generating means, receiving a power supply voltage, generating a fixed voltage which is essentially unaffected by a change in the power supply voltage, and applying this to the first voltage generating means. And the first voltage generating means is configured to generate the driving voltage by performing capacitive charge accumulation using the fixed voltage.

[Action]

According to the present invention having the above-described configuration, the word line driving voltage is independent of the fluctuation of the power supply voltage during the operation of the memory. Thus, it is possible to sufficiently perform " H " level writing for the selected memory cell within the allowable range of the power supply voltage without increasing the voltage at which breakdown occurs.

EXAMPLE

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a DRAM according to an embodiment of the present invention, which is indicated by reference numeral 10 in FIG.

The DRAM 10 has a memory cell array unit 12 on its chip substrate, which is a rewritable memory cell array arranged in a first number of rows and a second number of columns. Consists of In addition, these memory cells are coupled to parallel data transmission lines and parallel control lines that cross each other insulated, so that one memory cell is disposed at each intersection of these intersection lines. Here, the data transmission line is called an in-phase bit line, and the control line is called a word line.

The row decoder 14 is connected to a word line, selects one of the row lines (word lines) according to the row address or the row address included in the buffer 16, and the column decoder 18 opens the address buffer 20. Select one of the heating wires (bit lines) according to the opening dress included in. These addresses have address bits A0, A1, ..., An, and are supplied to the buffers 16 and 20 by the address lines 22 of a predetermined number of bits n based on the time-distribution principle. The number n becomes 8 or 16.

The control circuit 24 has a row address strobe signal input thereto. In response to this, the row address buffer 16 is driven. Hereinafter, the control circuit 24 is referred to as an RA control circuit. The output of this RA control circuit 24 is applied to the row decoder 14 via the voltage booster circuit 26 arranged on the substrate of the DRAM 10. The voltage booster circuit 26 generates a high potential voltage used for the word line drive signal. On the other hand, another control circuit 28 is provided as an open-dress buffer control circuit or a CA control circuit for controlling the buffer operation of the open-dress buffer 20 in response to the open-dress strobe signal CAS. The input data buffer (or latch) 30 and the output data buffer 28 are connected to a well-known sense amplifier circuit 32 connected to the bit line, and the AND gate 31 is connected to the buffers 28 and 30. An output is connected, a write enable signal WE is supplied to a first input of the AND gate 31, Is supplied to the second input of the AND gate 31 and the CA control circuit 28.

As shown in FIG. 2, one word line WLi is connected to a plurality of memory cells M1, M2, ... in parallel, and each memory cell M has a so-called one transistor structure, that is, one capacitor. 40 is composed of an insulated gate transistor 42 which is provided to the data storage element and functions as a transfer gate between the corresponding data transfer line WLi and the capacitor 40. The cell transistor 42 may be composed of a MOSFET. The cell transistor 42 has a current carrying electrode (usually a drain electrode) connected to a corresponding one of the bit lines BL1, BL2, ..., and the other memory cells have the same configuration. Further, transistors provided in one row of memory cells have control gate electrodes connected in common to corresponding word lines WLi. In FIG. 2, the capacitor C1 represents a parasitic capacitance present in the word line WLi, which is hereinafter referred to as a word line capacitance.

The word line driver circuit having the booster circuit 26 is connected to the memory cell array 12 via the line WDRV. Hereinafter, the line WDRV is called a word line driving line. The booster circuit 26 is comprised of three MOS transistors Q1, Q2 and Q3 and a capacitor C2, where the capacitor C2 acts as a boot or bootstrap capacitor, the boosted "H". Will generate a voltage. In addition, the gate electrode of the transistor Q1 has a control signal input ( 1), and the drain electrode is connected to one electrode of the bootstrap capacitor C2 through the node N1, and this transistor Q1 is used with an enhancement type N-channel MOSFET. In addition, the capacitor C2 performs a precharge function. The transistors Q2 and Q3 are connected in series, and the gate electrodes thereof are commonly used as control signal inputs ( 2), and the common node N2 of these transistors Q2 and Q3 is connected to the other electrode of the capacitor C2, and these transistors Q2 and Q3 control the potential of the node N2. The capacitor potential control unit is configured. The transistor Q2 is an E-type P-channel MOSFET and the transistor Q3 is an E-type N-channel MOSFET.

As shown in FIG. 2, the transistor Q1 has its source electrode connected to the first reference voltage generating circuit 44, and the transistor Q2 has its source electrode connected to the second reference voltage generating circuit 46. As shown in FIG. It is. The first reference voltage generation circuit 44 receives the power supply voltage Vcc of the DRAM 10 to generate a predetermined dc voltage as the first reference voltage Vr1, and the second reference voltage generation circuit 46 is previously described. A fixed potential of the determined second reference voltage Vr2 is generated. These voltages Vr1 and Vr2 are independent power supplies that are substantially unaffected from variations in the chip source voltage Vcc. These voltages are applied to the source electrodes of the transistors Q1 and Q2, respectively.

Input control signal When transistor Q1 is turned on in response to 1), node N1 is precharged to voltage Vr1. Then, before the address is determined, the clock signal ( 2) is at the "H" level, the node N2 is maintained at the "L" level. On the other hand, after the address is determined, the control signal ( 2) drops to the " L " level, whereby the transistor Q2 is brought into a conductive state, and the transistor Q3 is kept in a non-conducting state. Accordingly, the node N2 becomes the reference voltage Vr2, and the bootstrap voltage at which the potential is increased is displayed at the node N1 due to the capacitance coupled between the node N1 and the node N2. The resultant voltage is supplied to the selected word line WLi by the word line driving line WDRV through the MOS transistors Q4 and Q5 constituting a part of the row decoder 14. Here, the capacitor C3 represents the total capacitance associated with the circuit portion disposed between the circuits 12 and 26, which includes the parasitic capacitance in the word line driving line WDRV and the equivalent capacitance of the transistors 24 and 25. It is.

The reference voltage generating circuits 44 and 46 are control signals ( One, In addition to the circuit arrangement for generating 2), it is possible to install in the RA control circuit 24, where the reference voltage generating circuit 44 is typically configured as shown in FIG.

In FIG. 3, three diode-connected N-channel MOS transistors Q11, Q12, Q13 are connected in series with the load resistor R1, and the other end of the resistor R1 is connected to the power supply voltage input Vcc. It is. The connection node N3 between the MOSFETs Q11, Q12, Q13 and the resistor R1 functions as a reference voltage generation point, and this node N3 is connected to the inverting input of the operational amplifier OP. The operational amplifier OP is connected to the gate of the P-channel MOSFET 14, and the MOSFET Q14 is connected in series between the voltage divider Ra and Rb, the power supply voltage Vcc, and the ground voltage. The common connection point N4 of the resistors Ra and Rb is connected to the non-inverting input of the operational amplifier OP.

Since the potential of the node N3 is determined by the threshold voltages of the three diode-connected MOSFETs Q11, Q12, and Q13, a voltage having a fixed potential that is not affected by the fluctuation of the power supply voltage Vcc is generated. The operational amplifier OP amplifies the difference between the voltage Vc and the potential of the voltage division point N4 of the resistors Ra and Rb to generate the reference voltage Vr1. Is displayed as:

Vr1 = Vc · (Ra + Rb) / Rb... … … … … … … … … … … … … … … … … … (One)

On the other hand, the reference voltage generating circuit 46 for generating the second reference voltage Vr2 is similar to the reference voltage generating circuit 44 in its circuit configuration. That is, the number of transistors connected to the diode and the circuit constants (for example, the design value of the resistor, the gain of the operational amplifier, etc.) in the diodes are deformed according to the required fixed potential value of the reference voltage Vr2. However, when the first and second reference voltages Vr1 and Vr2 have the same fixed potential, the circuit 46 of FIG. 3 may also use the first and second reference voltage generation circuits.

Control signal ( 1) if the reference voltage Vr1 is lower than the power supply voltage Vcc, the power supply voltage Vcc is simply a value obtained by subtracting the threshold value of the transistor Q1 from the power supply voltage Vcc, In other words, when it is higher than Vcc-Vt _Q1 , the charge pump circuit 48 shown in FIG. It is used to generate as 1).

The charge pump circuit 48 includes charge accumulation capacitors C11 and C12, an N-channel MOSFET Q15 for charging and driving the capacitor C11 at a suitable time, and a diode-connected N-channel MOSFET Q16 for charge transfer. Q17). At one end of the capacitors C11 and C12, a complementary clock signal obtained by, for example, a ring oscillator, _R , ) Is supplied.

And, the control signal ( By inputting 1) to the gate electrode of the charging MOSFET Q1 of FIG. 2, the above-mentioned reference voltage Vr1 drops to the node N1 in a state where there is no drop in the threshold voltage at the transistor Q1. Is precharged.

The word line boost driving operation of this embodiment is performed as follows.

As shown in FIG. 5, at the time t0 before the address is confirmed, the second control signal ( 2) becomes "H" level. Therefore, the potential Vn2 at the node N2 of the capacitor C2 is maintained at the "L" level. And the first control signal ( When the charging MOS transistor Q1 is turned on in response to 1), the node N1 is charged to the reference voltage Vr1. At this time, the second control signal (1) is charged at the time t1 when the address is determined. When 2) falls from the "H" level to the "L" level, the P-channel MOS transistor Q2 is turned on and the N-channel MOS transistor Q3 is kept turned off so that the second reference voltage Vr2 is a transistor. Since the voltage is applied to the node N2 through Q2, the boosted voltage is applied to the node N1 by the total capacitance of the capacitor C2. In addition, the boosted voltage includes a word line driver line (DWRV) and a clock signal ( 3, 4 is transferred to the selected word line WLi through transistors Q4 and Q5 that are selectively turned on in response to 4), and the voltage Vwd on the word line WLi (hereinafter referred to as word line boost voltage) is " H ""I will rise to the level. Therefore, the memory cells M1, M2, ... associated with this word line WLi use the "H" level voltage to transfer the data charge between the corresponding bit lines BL1, BL2, ... according to a known method. Data carrier).

In the circuit arrangement of FIG. 2, the word line boost voltage Vwd is defined as follows.

If the first and second reference voltages Vr1 and Vr2 are equal to each other, the word line boost voltage Vwd is

Is simplified.

As can be seen from the above equation, the word line boost voltage Vwd is the first and second reference voltages Vr1 and Vr2 independent of the power supply voltage Vcc supplied externally to the DRAM 10 chip. Is arbitrarily determined by. In other words, the word line boost voltage Vwd is maintained at a desired constant potential level without depending on any variation in the power supply voltage Vcc. This supports the fact that the voltage Vwd does not change in the allowable fluctuation range defined by the minimum allowable voltage Vccmin and the maximum allowable voltage Vccmax of the power supply voltage Vcc of the DRAM 10 in the graph of FIG. . The word line step-up voltage Vwd at a constant potential level is higher than (1) the bit line "H" level voltage at the lowest permissible power supply voltage (Vccmin), which increases substantially in proportion to the increase in the power supply voltage (Vcc). (2) At the maximum allowable power supply voltage Vccmax, it is appropriately suppressed so as not to exceed the insulation breakdown voltage of the memory cell transistor 42.

This enables sufficient " H " level recording at the lowest permissible power supply voltage Vccmin, while preventing the application of more stress than necessary to the gate insulating film of the cell transistor.

Accordingly, the time-destructive destruction (TDDB) of the cell transistor can be successfully removed, thereby further improving the operation reliability of the DRAM 10.

On the other hand, in Fig. 2, it is not necessary to use both the first and second reference voltage generating circuits 44 and 46. In other applications, at least one of them may be provided for the boost circuit 26. There may be cases. For example, the circuit configuration shown in FIG. 7 shows a case in which the reference voltage Vr2 in FIG. 2 is replaced with a power supply voltage Vcc. The circuit configuration shown in FIG. 8 shows a reference voltage in FIG. The case where Vr1) is replaced with the power supply voltage Vcc is shown. In the case of FIG. 7, the word line boost voltage Vwd

And the word line step-up voltage Vwd in the case of FIG.

Is displayed. In any of the circuit configurations of FIG. 7 and FIG. 8, although disadvantageous in view of the dependency of the word line step-up voltage Vwd on the power supply voltage Vcc, the present invention may have sufficient advantages in practice. The characteristic graph of the word line boost voltage Vwd versus the power supply voltage Vcc in each case is shown in FIG.

FIG. 10 illustrates a main configuration of a word line driving circuit according to another embodiment of the present invention. In FIG. 10, a special circuit section for compensating word line boost voltage Vwd between DRAM chips against accidental variations in manufacturing process conditions is shown in FIG. Is generally indicated by the reference numeral "50".

The circuit section 50 corresponds to the reference voltage generating circuits 44 and 46 of the embodiment circuit shown in FIG. In other words, the circuit part 40 is a circuit which generates the reference voltage Vr which compensates or absorbs the accidental fluctuation of the DRAM manufacturing process conditions.

As shown in FIG. 10, the circuit section 50 includes two voltage generating circuits 52a and 52b. One voltage generating circuit 52a is faithful to the actually manufactured thickness (actual breakdown voltage on a chip) of the gate insulating film of the memory cell transistor so as not to depend on the power supply voltage Vcc at a predetermined potential level of the power supply voltage Vcc. The first voltage Vc1 is proportionally generated, and this voltage is referred to as "Tox-voltage" and the circuit 52a is referred to as "Tox-voltage generation circuit".

In addition, the other voltage generating circuit 52b generates a second voltage Vc2 representing the power supply voltage Vcc and the actual threshold voltage of the memory cell transistor (the threshold value after the change if any change is made by the manufacturing process). . This voltage is called "Vth-voltage" and the circuit 52b is called Vth-voltage generating circuit.

The output voltage of the Tox-voltage generator circuit 52a is connected to the amplifier circuit 54a. The amplifier circuit 54a includes an operational amplifier OP1 and a gate electrode connected to the output of the operational amplifier OP1. The P-channel MOS transistor Q211 and the divided resistors Ra1 and Rb1 are formed in series circuits. In addition, the transistor Q211 and the divided resistors Ra1 and Rb1 are connected in series between the power supply voltage Vcc and the ground potential, and the common connection node of the resistors Ra1 and Ra1 is inverted of the operational amplifier OP1. Returned to the input, the voltage Vc1 is led to the inverting input of the operational amplifier OP1, and the amplified voltage appears at the output of the operational amplifier OP1. The drain electrode of the transistor Q211 serves as the output of the amplifying circuit 54a.

On the other hand, the Vth voltage generator circuit 52a is connected to the amplifier circuit 54b, which is connected to the operational amplifier OP2 and the output of the operational amplifier in the same manner as the amplifier circuit 54a. The P-channel MOS transistor Q212 having the gate electrode and the divided voltage resistors Ra2 and Rb2, and the common connection node of the resistors Ra2 and Rb2 are fed back to the non-inverting input of the operational amplifier OP2. have. When the voltage Vc2 is input to the inverting input of the operational amplifier OP2, the amplified output voltage of the operational amplifier OP2 is applied to the gate electrode of the transistor Q2l2. The drain electrode of this transistor Q212 serves as the output of the amplifying circuit 54b, and the outputs of the amplifying circuits 54a and 54b are interconnected at the node 56. Accordingly, the node 56 shows the potential higher of the amplified output voltages Va1 and Va2 of the amplifying circuits 54a and 54b.

The internal configuration of the Tox-voltage generating circuit 52a can be realized by employing any of the ones illustrated in Figs. 11A to 11F.

In the circuit configuration of FIG. 11A, three diode-connected N-channel MOSFETs Q31, Q32, and Q33 are used, one end of which is connected to the power supply voltage Vcc through a load resistor 32, and the other end thereof is a contact potential. Is connected to. These transistors Q31, Q32, and Q33 have N-conducting silicon gate electrodes, and these channel regions are provided with MOSFETs in which no ions are implanted or channel regions in which ions are implanted, so that the threshold value is the thickness of the gate oxide film. The N-channel MOSFET is substantially proportional to. The resistance value of the load resistor R2 is sufficiently large in proportion to the resistance values of the transistors Q31, Q32, and Q33. At the output terminal of this circuit, when the power supply voltage Vcc is higher than the sum of the threshold voltages of the three diode-connected transistors Q31, Q32, and Q33, the sum of the thresholds indicates the actual thickness of the gate insulating film. Appear as Tox-voltage Vc1.

The generation of the voltage Vc1 will be described in detail below.

In general, the threshold value Vth of an N-channel MOSFET having an insulated gate electrode and a gate electrode made of an N conductive semiconductor material without implantation of channel ions is summarized as follows.

Vth = -Vfb + 2 f + γ ( f + Vsub) [1/2] Tox... … … … … … … … … (6)

Where Vfb is the flat band voltage, f is the pad mi level, γ is the proportional constant, Vsub is the chip substrate bias voltage, and Tox is the thickness of the gate oxide film.

In the above-described N-channel MOSFET, in general,

│-Vfb + 2 f│ 《γ ( + Vsub) [1/2] Tox... … … … … … … … … (7)

to be. Therefore, the threshold voltage Vth is almost proportional to the thickness Tox of the gate oxide film (this can be understood from the straight line Vth (Tox) in the graph of FIG. 12 described later). Therefore, in the circuit configuration generating the reference voltage shown in FIG. 11A, when the power supply voltage [Vcc] is equal to or higher than a predetermined potential level, the voltage Vc1 is proportional to Tox regardless of the actual value of the power supply voltage Vcc as follows. do.

Vc1 = K Tox... … … … … … … … … … … … … … … … … … … … … (8)

Where K is the proportional factor.

In the reference voltage generating circuit of FIG. 11B, the substrate bias conditions of the MOS transistors Q31, Q32, and Q33 diode-connected with the circuit of FIG. 11A are different. That is, these transistors are commonly connected to the ground potential. Therefore, the Tox-voltage (Vc1) obtained here is expressed by γ ( + Vsub) [1/2] is defined as the same as (6), except that the value is different. The expression (8) also holds for this voltage Vc1.

As can be seen from Equation (8), the generated voltage Vc1 is independent of the number of diode-connected transistors used. This fact shows that the circuit configurations of 11a and 11b are shown in Fig. 11c. Likewise it is possible to modify to use only one MOSFET Q31. In the circuit configuration of FIGS. 11A to 11C, since the N-channel MOS transistor has a channel region in which no ions are implanted, variations in process conditions other than the thickness of the gate oxide film (eg, ion implantation conditions, temperature thereof, etc.) are extremely small. With or without. Therefore, the voltage Vc1 becomes electrically stable.

On the other hand, in the circuits of Figs. 11A to 11C, when the MOSFETs Q31, Q32 and Q33 have channel regions implanted with ions, the variation? Fb in the flat band voltage Vfb due to ion implantation is next. If the ion implantation state is arranged to satisfy the equation,

-Vfb + △ fb + 2 f to 0... … … … … … … … … … … … … … … … … … … (9)

Even if a MOSFET having a channel region implanted with ions is used, a Tox-voltage proportional to the thickness of the gate insulating film implanted with the ions of the MOSFET is generated. In addition, if the diode-connected N-channel MOSFETs Q31, Q32, Q33 have a gate electrode made of a P-type semiconductor, the threshold voltage is expressed as follows.

Vth = Vfb + 2 f + γ ( f + Vsub) [1/2] Tox... … … … … … … … … … 10

The ion implantation state in this case is similar to that described above.

The circuit of FIG. 11d differs from the circuit of FIG. 11c in that a P-channel MOSFET Q34 having a P-type gate electrode and a undoped channel region is used. The threshold voltage Vth of this transistor Q34 is as follows. Is given.

Vth = -Vfb + 2 f-γ ( f + Vsub) [1/2] Tox... … … … … … … … … … (11)

Here, if Tox is large enough, the following relationship is established.

│-Vfb + 2 f│ 《γ ( f + Vsub) [1/2] Tox... … … … … … … … … … … … (12)

As a result, the voltage Vc1 becomes proportional to the thickness of the gate insulating film of the transistor Q34. In addition to the P-channel MOS transistor Q34 having the P-type gate electrode, the N-channel MOS transistor having the N-type gate electrode has less variation in manufacturing parameters than the parameter for the thickness of the gate insulating film. As a result, the voltage Vc1 becomes less dependent on the power supply voltage Vcc, and thus becomes largely stable.

If no impurities are doped by ion implantation into the channel region of the P-type MOSFET with the N-type gate electrode, the threshold voltage is defined as follows.

Vth = Vfb + 2 f-γ ( f + Vsub) [1/2] Tox... … … … … … … … … … (13)

This indicates that the Vth voltage is not proportional to the thickness of the gate insulating film, which is shown as "-Vth2" in the graph of FIG. In this case, even when a predetermined impurity such as bronze is doped in the channel region of the transistor, the flat band variation ΔVfb is generated to satisfy the following condition.

│-Vfb + 2 f- DELTA Vfb | … … … … … … … … … … … … … … … … … … (14)

Thus, a suitable voltage to be used as the voltage Vc1 can be generated. Similarly, a series circuit of a plurality of diode-connected MOSFETs in the case of using a P-channel MOSFET with a P-type gate electrode can be used in the configuration of the reference voltage generating circuit 54a as in the case of the N-channel MOSFET.

The circuit shown in FIGS. 11E and 11F is a modification of the circuit shown in FIG. 11C and uses an N-channel MOSFET Q35 or a P-channel MOSFET Q36 instead of the load resistor R2. Here, the transistors Q35 and Q36 are set in accordance with the following conditions to obtain a load resistance.

Wch / Lch <1... … … … … … … … … … … … … … … … … … … … (15)

Here, "Wch" is the channel width and "Lch" is the channel length. Also in the above arrangement, as in the case of FIG. 11C described above, an appropriate voltage Vc1 proportional to the thickness of the gate insulating film can be generated.

The circuit arrangement of FIGS. 13A to 13D is for the second Vth-voltage generating circuit 52a of FIG.

According to the circuit configuration of FIG. 13A, the N-channel MOS transistor Q41 is formed to have the same shape under the same manufacturing process conditions as the memory cell transistors M1, M2, ... of FIG. The transistor Q41 is sufficiently larger than the resistance values of the resistors R3 and R4 between the power supply voltage Vcc and the ground potential. The output voltage, which is the Vth voltage Vc2 that appears in the current carrying current of the MOSFET Q41, is assuming that the threshold voltage of the MOSFET Q41 is Vtc.

Is displayed. It can be understood from the equation (16) that the voltage Vc2 depends on the power supply voltage Vcc and fluctuates in accordance with the variation of the gate threshold voltage Vtc of the MOS transistor Q41.

The circuit configuration of FIG. 13B is a different substrate bias condition of the MOS transistor Q41 of the circuit configuration of FIG. 13A. In this case, except that the threshold voltage of the transistor Q41 is different, the relationship defined by the expression (14) does not change.

In the circuit configuration of FIG. 13C, the connection position of the transistor Q41 and the resistor R4 is reversed in the circuit configuration of FIG. 13A. Therefore, the voltage Vc2 obtained in this case does not change at all.

The circuit arrangement of FIG. 13d is characterized in that a plurality of parallel connected MOSFETs are used instead of the MOSFET in the circuit arrangement of FIG. 13a. These transistors are substantially the same as the memory cell transistors 42 formed in the extremely fine size of the highly integrated DRAM 10 in its manufacturing process conditions. Even in this case, the voltage Vc2 is generated to be represented by the expression (14).

On the other hand, going back to the tenth degree, the circuit 50 operates as follows.

Tox-voltage Vc1 and Vth-voltage Vc2 are amplified by operational amplifiers OP1 and OP2, respectively. The amplified output voltage Va1 of this operational amplifier OP1 is

And the amplified output voltage Va2 of the operational amplifier 54b is given as follows.

The relationship between the voltages Va1 and Va2 and the power source voltage Vcc is as shown in the graph shown in FIG. As can be seen from FIG. 14, the voltage Va1 can be kept constant when the power supply voltage Vcc is greater than a specific potential level, and the voltage Va2 increases as the power supply voltage Vcc increases. This voltage Va2 is proportional to the power supply voltage Vcc and the threshold voltage of the MOS transistor. As described above, the voltage at the wired output node 56 serving as the first reference voltage Vr1 is converted as shown in the graph of FIG. 15 in proportion to the larger of the voltages Va1 and Va2. .

The reference voltage Vr1 generated by the circuit of FIG. 10 is applied to the MOS transistor Q1 of the boost circuit 26 shown in FIG. In this case, the word line boost voltage Vwd is as follows. When the voltage Va1 is charged to the boosting capacitor C2 (FIG. 2) alone, and the charge pump voltage of the capacitor C2 is applied to the word line WLi, the word line boost voltage Vwd is Is defined as

However, since capacitor C3 in FIG. 2 is small, it is ignored. Considering only the voltage Va2 defined by the expression (18), it becomes as follows.

The larger of the values of the formulas (16) and (17) is supplied to the word line WLi designated as the word line voltage Vwd. Referring to FIG. 16, it is more preferable that the characteristic graph of FIG. 15 is changed to compensate for variations in the gate insulating film thickness Tox and the threshold voltage Vth of the memory cell transistor caused by the error in the DRAM manufacturing process. It can be well understood. For example, when Tox and Vth increase, the potential level in the plan region of the reference voltage Vr1 (that is, the potential region corresponding to the constant potential of the potential Va1 in FIG. 14) is equal to the diagonal portion. Increase as indicated by (58).

According to the embodiment having the boost circuit 26 employing the configuration of the reference voltage generator of FIG. 10, the power supply voltage dependency characteristic of the boost voltage Vwd applied to the word line WLi is large in the graph of FIG. As shown by lines L1, L2, and L3. The voltage Vwd is maximized when the reference voltage Vr1 is potentially equal to the power supply voltage Vcc and C1 >> C2. This is indicated by the line L1, which indicates that the voltage Vwd increases in proportion to the power supply voltage Vcc without depending on the voltage Va1. In Fig. 17, the line L2 keeping 5V constant corresponds only to the flat portion of the voltage Va1 of Fig. 14, i.e., the region depending only on the gate insulating film thickness Tox of the MOS transistor. As the power supply voltage Vcc further increases, the word line boost voltage Vwd is increased depending on both the power supply voltage Vcc and the threshold voltage in accordance with the reference voltage Va2 as indicated by the line L3.

Features of this embodiment are as follows. If the maximum electric field of TDDB is Emax,

Is displayed as: If you combine (20) and (21),

Is obtained. This equation means that the word line boost voltage Vwd is completely defined by the product of the maximum TDDB electric field Emax and the thickness Tox of the control gate insulating film. That is, in the graph of FIG. 17, the flat part 22 of the voltage Vwd change is not limited to the fluctuation of the power supply voltage Vcc but becomes constant at the TDDB limit. Moreover, the word line boost voltage Vwd changes in proportion to the variation of the Tox value. Therefore, according to the present embodiment, in addition to the drop in the previous embodiment, the word line boost voltage Vwd changes in the thickness Tox of the gate insulating film of the memory cell transistor 42 due to the variation of the DRAM manufacturing process parameters. Can be effectively compensated.

Further, if C1 is sufficiently larger than C2 (C1 >> C2), and the power supply voltage Vcc is smaller than (Emax * Tox) / 2, the voltage Vwd is set to the limit value of the boost circuit 26, that is, 2Vcc. To increase. In view of the above, even when the thickness of the gate insulating film Tox is undesirably changed, the word line-up voltage Vwd

(1) When 2Vcc> Emax Tox, Vwd increases to 2Vcc,

(2) When 2 Vcc ≤ Emax Tox, Vwd = Emax Tox 2 Vcc (constant value) is maintained.

The "absorption" feature of the automatic Tox variation of the gate insulating film eliminates the deterioration of the operation reliability caused by the TDDB of the DRAM 10, and thus, the allowable fluctuation range of the power supply voltage Vcc of the DRAM 10 is eliminated. Sufficient " H " level write margin for any memory cell can be guaranteed. Accordingly, the word read voltage Vwd is sufficiently high potential to improve the data read speed. It is also possible to compensate for unwanted fluctuations in Tox of the memory cell transistor 42 caused at the time of drafting the DRAM 10.

In formula (20),

In the case of (20)

Is simplified. It can be seen from the formula (23) that the condition of the formula (23) can be set as desired by changing (Ra2 + Rb2) / Rb2 even if the value of R3 / R4 is deformed. In the DRAM 10, the word line voltage Vwd required when actually performing " H " level writing to an arbitrary memory cell is

It becomes Here, Vt1 represents the threshold voltage of the cell transistor 42.

In the boosting circuit 26 employing the circuit configuration of FIG. 13A, the MOS transistor Q41 and the cell transistor 42 are equivalent to each other in manufacturing process conditions, size, shape, etc., and they differ only in substrate bias potential. The substrate bias potential (Vsub1) of the memory cell array is

It becomes Where Vbb is the well potential. The substrate bias potential Vsub2 of the MOS transistor Q41 is

to be. From the equations (24) and (25), it can be seen that Vsub1 &gt; Vsub2, so the relationship of Vtc &lt; Vt1 is found. In this way, the threshold difference is compensated by modifying R3 / R4.

,

It is possible to obtain the word line voltage Vwd prescribed by.

13B and 13C are also the same except for the difference in their substrate bias potential. However, in the arrangement, the " H " level writing efficiency to the memory cells is guaranteed so that the Tox variation of the cell transistor 42 can also be automatically compensated. This also has an advantage in accelerated testing of the DRAM 10. The reliability test of the DRAM 10 forcibly raising the power supply voltage Vcc can be conducted using the driving circuit configuration of the above embodiment and using the region of the rising characteristic curve L3 in FIG. In the graph of FIG. 17, the triangular region surrounded by the large curved lines L1, L2, L3 and the line Vcc-Vt1 indicating the minimum required voltage only for the "H" level recording has a sufficient operating margin. This is the area that can be obtained. This is broader in comparison with the above case and therefore supports an improvement in operating margin.

FIG. 18 shows a leakage compensating circuit according to a third embodiment of the present invention, which is additionally installed inside the DRAM 10 so as to work together with any of the first and second embodiments described above. . The leakage compensating circuit 60 actively suppresses the variation of the word line boost voltage Vwd due to current leakage in the word line (for example, the drain electrode of the memory cell transistor 42) which is essentially generated inside the DRAM 10. FIG. To compensate.

As shown in FIG. 18, the word line boost voltage Vwd generated by the boost circuit 26 in FIG. 2 is led to the first input of the voltage comparator 62, and the comparator 62 is a word line. A second input is provided which is supplied with a reference voltage Vref representing the preferred standard potential of the boost circuit Vwd. In addition, the comparator 62 generates a voltage signal Vro indicating a comparison result of the voltage Vwd and the voltage Vref at its output, which is input to the ring oscillation circuit 64. In addition, the ring oscillation circuit 64 is connected to the charge pump circuit 66, so that the operation of the charge pump circuit 66 is controlled in response to the output of the ring oscillation circuit 64.

As shown in FIG. 19, the comparator 62 has N-channel MOS transistors Q51 and Q52 whose gate electrodes are commonly connected to the ON / OFF control input Vsw. These transistors have control voltage signals. It is selectively turned on and off in response to Vsw. The transistor Q51 is connected at one end to a series circuit of resistors R11 and R12 connected to the word line voltage input Vwd, and the transistor Q52 is connected at one end to a series of reference voltage inputs Vref. It is connected to the resistors R13 and R14 of the connection. In the N-channel MOS transistors Q53 and Q54, the gate electrodes thereof are respectively connected to the common noses Nr1 and Nr2 of the resistor, the source electrodes are connected together, and the P-channel MOS transistors Q55 and Q56 are connected. It is connected to the transistors Q53 and Q54, respectively, to selectively supply the current required for the transistors Q53 and Q54. The series circuit of the N-channel switching MOS transistors Q57 and Q78 is connected to the source electrodes of the transistors Q53 and Q54. The transistor Q57 is supplied with a control signal Vsw to the gate electrode thereof, and the transistor ( Q58 is applied another control voltage signal Vm to its gate electrode. The transistors Q53, Q54, Q55, Q56, Q57, and Q58 constitute a current meter type differential amplifier circuit.

The gate electrode of transistor Q53 serves as the first input of comparator 62. The supplied word line voltage Vwd is divided by the resistors R11 and R12, and the reference voltage Vref is divided by the resistors R13 and R14 and provided as a second input of the comparator 62 as a transistor Q54. Is supplied to the gate electrode. The output of the CMOS differential amplifier is output from the node Nq so that the ring oscillation circuit control signal Vro is transmitted to the ring oscillation circuit 64 through the P-channel MOS transistor Q59 and the output buffer 68. The transistor Q59 has its drain electrode connected to the power supply voltage vcc, and the source electrode connected to the ground potential via the N-channel MOS transistor Q61. The gate electrodes of the transistors Q58 and Q61 are interconnected so that the control signal Vm is supplied to both transistors Q58 and Q61. The P-channel MOS transistor Q60 is connected between the gate and the drain of the transistor Q59, and the gate electrode thereof is connected to the signal Vsw.

As the word line voltage Vwd input to the comparator 62, the actual potential on the word line WLi actually selected inside the DRAM 10, or a pseudo word line additionally provided inside the DRAM 10 (of course this is actually Potential is obtained from the same load condition as that of the word line. As the reference voltage Vref, for example, the output voltage Vr1 of the circuit 44 of FIG. 2 is used. The resistance values of the divided resistors R11, R12, R13, and R14 are designed so that the control signal Vvo of the ring oscillation circuit becomes " H " when the word line boost voltage Vwd drops below a predetermined potential.

The ring oscillation circuit 64 is configured as shown in FIG. 20. In FIG. 20, a plurality of series-connected CMOS inverters 70 have N gate electrodes connected to gate electrodes of transistors Q74. The channel MOS transistor Q73 and the MOS transistors Q71, Q72, and Q74 are coupled to a series circuit, and the control signal Vro is supplied to the gate electrode of the transistor Q74 through the CMOS inverter Q72, and the transistor ( The gate electrodes of Q71 and Q72 are commonly connected to the output of the inverter at the final stage.

The current leakage compensation circuit 60 performs a compensation function as follows. The comparator 62 is kept in an inactive state while the switching control signals Vsw and Vm are at the "L" level. At this time, the output transistor Q60 is brought into a conductive state, and the gate electrode thereof is turned on by the transistor Q60. And the transistor Q59 to which the drain electrode is connected together are turned off. The transistor Q61 also remains in a non-conductive state. In addition, the transistors Q73 and Q74 in the ring oscillation circuit 64 are also turned off so that the oscillation circuit 64 is prohibited from oscillation operation.

On the other hand, when the signals Vsw and Vm become " H &quot;, the comparator 62 is activated. In this case, when the word line voltage Vwd is higher than the preselected potential level, the output of the differential amplifier in the comparator 62 This level becomes "H". Accordingly, as the transistor Q59 is turned off, the transistor Q61 is turned on so that the voltage Vro is constantly fixed at the "L" level. When the voltage Vwd is smaller than a preselected level, the output voltage of the differential amplifier is “L”, and the transistor Q59 is turned off. At this time, the turn-on resistances of the transistors Q59 and Q61 are suitably designed to satisfy a predetermined relationship. As the transistors Q59 and Q61 are turned on, the voltage Vro becomes " H &quot;. The oscillation circuit 64 is activated according to the potential level change in the voltage Vro. Therefore, the oscillation circuit 64 oscillates to obtain an appropriate clock signal. Since the charge pump circuit 66 is driven in response to the oscillation, the word line voltage generation circuit 26 (see FIG. 2) is activated to reduce the voltage on the selected word line WLi. To a predetermined standard level corresponding to Vref).

According to the third embodiment, it is possible to fix the actual voltage on the word line WLi to a predetermined potential level by compensating for the sudden voltage drop caused by the leakage current present in the word line. Furthermore, such selective activation of the ring oscillation circuit can enhance the operation reliability of the DRAM 10 while minimizing power consumption.

The comparator 62 may be modified as shown in FIG. In FIG. 21 to FIG. 19, the voltage dividing resistor R12 is constituted by a pair of resistors R12a and R12b, and one of the sources and the drain electrode is connected to the common node Nr3 of the resistors R12a and R12b. While connected, an N-channel MOS transistor Q62 whose gate electrode is connected to the voltage Vro is added. The transistor Q62 is selectively turned on and off in response to the voltage Vro to connect the node Nr3 to the ground potential at turn-on.

In the circuit shown in FIG. 21, a portion is formed which is not influenced by the leakage compensation operation. In particular, while the word line boost voltage is higher than the predetermined potential level and the voltage Vro is kept at the "L" level, the transistor Q62 is brought into a non-conductive state. The partial pressure ratio on the word line side is R11 / (R12a + R12b). The voltage (Vin) input to the differential amplifier circuit is

Is given by When the voltage Vin drops from the predetermined potential level, the comparator 62 starts operation so that the control signal Vro becomes " H ", and the ring oscillation circuit 64 starts oscillation. When the voltage Vro is at the "H" level, the transistor Q62 is turned on, and the divided voltage ratio at this time is R11 / R12a. Therefore, the input voltage Vin

Is displayed. Therefore, the ring oscillation circuit 64 is prohibited from immediately returning the input voltage Vin of the differential amplifier to the " H " level even when the voltage on the selected word line WLi is restored to some extent, thereby continuing the oscillation operation for a while. This clearly indicates that there is a part which is not affected by the leakage compensating operation. This makes it possible to prevent the unwanted occurrence of the word line WLi from being oscillated secondarily with leakage compensation.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

[Effects of the Invention]

As described above, according to the present invention, since the " H " level writing to the memory cell can be performed sufficiently without increasing the voltage at which the dielectric breakdown occurs, the semiconductor memory device having excellent operation performance and reliability can be provided. Will be.

Claims (10)

An integrated circuit for use in a semiconductor memory device having a row and column array of memory cells (M) associated with a bit line (BL) and a word line (WL), wherein the digital information is stored in a selected word line of the word line (WL). Connected to the first voltage generation means 26 for generating word line driving voltage Vwd high enough to enable " H " level recording, and to the first voltage generation means 26, and receiving a power supply voltage Vcc. Second voltage generating means (44,46) for generating fixed voltages (Vr1, Vr2) which are essentially unaffected by variations in the power supply voltage (Vcc) and applying them to the first voltage generating means (26). And 50, wherein the first voltage generating means generates the word line driving voltage Vwd by performing capacitive charge accumulation using the fixed voltages Vr1 and Vr2. Circuit. 2. An integrated circuit according to claim 1, wherein said first voltage generating means (26) comprises capacitor means (C2) for accumulating charge when said fixed voltages (Vr1, Vr2) are applied. 3. The first reference voltage generating circuit (44) according to claim 2, wherein said second voltage generating means (26) is connected to said power supply voltage (Vcc) to generate a first DC reference voltage (Vr1). And a second reference voltage generating circuit 46 connected to Vcc to generate a second DC reference voltage Vr2, wherein the capacitor C2 receives the first DC reference voltage Vr1. And a second electrode receiving the first electrode and the second DC reference voltage (Vr2). 4. An integrated circuit according to claim 3, wherein at least one of said first and second reference voltage generating circuits (44, 46) comprises at least one diode-connected MOS transistor (Q11, Q12 or Q13). . 4. An integrated circuit according to claim 3, wherein at least one of the first and second reference voltage generators (44, 46) comprises a series circuit of diode-connected MOS transistors (Q11, Q12, Q13). . 6. The amplifier (OP) according to claim 5, wherein said at least one of said first and second reference voltage generating circuits (44, 46) has an amplifier (OP) connected to a series circuit of said diode-connected MOS transistors (Q11, Q12, Q13). Integrated circuit comprising a. 4. The power supply voltage Vcc according to claim 3, wherein one of the first and second reference voltage generating circuits 44 and 46 has a constant potential irrelevant to a change in the power supply voltage Vcc when the power supply voltage Vcc is below a predetermined potential. A voltage is generated, and when the power supply voltage Vcc is equal to or higher than a predetermined potential, a strain voltage is generated which is substantially proportional to the gate insulation breakdown voltage of the cell transistor included in the memory cell associated with the currently selected word line WLi, And compensation means (50) for supplying these voltages to said first voltage generating means (26) to compensate for the error in dielectric breakdown voltage between said memory cells. 8. The integrated circuit of claim 7, wherein the strain voltage is potentially proportional to the thickness of the gate insulating film of the cell transistor. The method of claim 1, further comprising an additional circuit means (60) for detecting a current leakage component present in the selected word line (WLi) and selectively generating a voltage for compensating the detected current leakage component. Integrated circuit, characterized in that configured. 10. The reference circuit according to claim 9, wherein the additional circuit means (60) is applied with an actual potential (Vwd) on the selected word line (WLi) and represents a reference potential representing an appropriate potential on the selected word line supplied externally. Vref) is applied to the comparison means 62 for comparing them, the oscillation means 64 for selectively performing the oscillation operation in response to the output of the comparison means 62, and the output of the oscillation means 64. And charging means (66) operating accordingly to produce a compensated word line voltage.