KR940010769A

KR940010769A - Letter box type video display system

Info

Publication number: KR940010769A
Application number: KR1019920019135A
Authority: KR
Inventors: 길동선
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1992-10-17
Filing date: 1992-10-17
Publication date: 1994-05-26
Also published as: KR950005605B1

Abstract

본 발명은 가로대 세로의 비율이 16 : 9인 스크린에 4 : 3 스크린을 디스프레이하는 기술에 관한 것으로, 종래의 시스템에 있어서는 가로대 세로비가 16 : 9인 스크린 전체에 래터박스형 영상이 다 차지않아 디스플레이되지 않는 부분이 남게 되므로 사용자가 표준모드와 와이드 모드를 일일이 선택해야되는 번거로움이 있었는 바, 이를 해결하기 위하여 신호 검출부(30)에서 래터박스형 신호를 검출하고 이에 따라 스위칭부(60)의 스위칭을 제어하여 보간부(50)에서 보간된 신호나 필드메모리(20)의 출력신호를 선택적으로 출력할 수 있게 한 것이다.The present invention relates to a technique of displaying a 4: 3 screen on a screen having a 16: 9 aspect ratio, and in a conventional system, an entirety of a screen having a 16: 9 aspect ratio does not occupy and is not displayed. Since there is a part that does not remain, the user has to select the standard mode and the wide mode one by one. In order to solve this problem, the signal detection unit 30 detects the ratter box-type signal and controls the switching of the switching unit 60 accordingly. The interpolation unit 50 can selectively output the interpolated signal or the output signal of the field memory 20.

Description

Letter box type video display system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 영상처리기의 영상 디스플레이 블록도,1 is an image display block diagram of a general image processor;

제2도의 (가)는 래터박스형 영상신호의 화면 구성도이고, (나)는 제1도에 의한 래터박스형 영상신호의 화면 구성도,(A) of FIG. 2 is a screen configuration diagram of the letterbox type video signal, (B) is a screen configuration diagram of the letterbox type video signal according to FIG.

제3도는 본 발명의 래터박스형 영상 디스플레이 블록도,3 is a ratbox type image display block diagram of the present invention;

제4도는 제3도에서 신호 검출부의 상세 블록도,4 is a detailed block diagram of a signal detector of FIG. 3;

제5도의 (가)는 래터박스형 영상신호의 화면 구성도이고, (나) 제3도에 의한 래터박스형 영상신호의 화면 구성도,(A) of FIG. 5 is a screen configuration diagram of the letterbox type video signal, (B) a screen configuration diagram of the letterbox type video signal according to FIG.

제6도는 제4도에서 레벨 검출부의 진리표,6 is a truth table of the level detector of FIG.

제7도의 (가) 내지 (다)는 제4도 각부의 파형도.7A to 7C are waveform diagrams of respective parts of FIG.

Claims

Analog (A) / digital to convert analog luminance signal (Y) and chrominance signal (BY), (RY) into digital luminance signal (DY) and digital chrominance signal (D (BY)), (D (BY)) (D) The converter 10, the input luminance signal (Y) and the horizontal synchronization signal (H. Sync) is supplied to check whether the screen is composed of the absence of the signal portion and the presence of the control signal accordingly The digital luminance signal DY and the color difference signal D (BY) output from the A / D converter 10 by using the signal detection unit 30 to output, the read and write signals f _r and f _w . ) And (D (RY)) the memory controller 40 which writes or reads the field memory 20 and outputs a switching control signal according to the signal input from the signal detector 30, and the field memory. A digital luminance signal (DY) and a color difference signal (D (BY)) and (D (BY)) of the current line outputted from (20) and mixed with the corresponding signal delayed by one line are outputted. A switching unit 60 for selecting an output signal of the field memory 20 or an output signal of the interpolation unit 50 according to the executive unit 50 and the switching control signal of the memory control unit 40, and the switching. A D / A converter 70 for converting the digital luminance signal DY and the color difference signals D (BY) and (D (BY)) output from the unit 60 into an analog signal, and the D / A converter ( 70 extracts the red signal (R), green signal (G), and blue signal (B) from the analog luminance signal (AY), and the color difference signal (A (BY)) and (A (RY)). Later box-type image display system, characterized in that consisting of an image processing unit 80 for outputting to a color picture tube (CPTll).

The first and second counters of claim 1, wherein the signal detection unit 30 receives an input luminance signal Y and a horizontal synchronization signal H. Sync, and outputs a high potential at a portion where no signal exists. A second counter 32 that is enabled by the low potential output from the first counter 31 and outputs a high potential, and disables the first counter 31 at the high potential, and the first and second counters 31. And a level detector (33) for outputting a detection signal according to whether or not the high potential is output from at least one of (32) and (32).

※ Note: The disclosure is based on the initial application.