KR940008767B1 - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
- Publication number
- KR940008767B1 KR940008767B1 KR1019910022781A KR910022781A KR940008767B1 KR 940008767 B1 KR940008767 B1 KR 940008767B1 KR 1019910022781 A KR1019910022781 A KR 1019910022781A KR 910022781 A KR910022781 A KR 910022781A KR 940008767 B1 KR940008767 B1 KR 940008767B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- etching
- photoresist
- metal
- interlayer insulating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1도는 종래의 제조방법에 따른 금속라인부의 단면도,1 is a cross-sectional view of a metal line part according to a conventional manufacturing method,
제2도는 (a)에서 제2도 (d)까지는 본 발명의 일실시예에 따른 제조 공정도,2 is a manufacturing process diagram according to an embodiment of the present invention from (a) to 2 (d),
제3도는 본 발명의 일실시예에 따른 금속라인부의 단면도,3 is a cross-sectional view of a metal line part according to an embodiment of the present invention;
제4도의 (a)에서 (d)까지는 본 발명의 반도체 소자를 구비한 DRAM의 제조공정도.4A to 4D are manufacturing process diagrams of a DRAM including the semiconductor element of the present invention.
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 미세하게 형성된 패턴 사이의 공백(void)이 제거된 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which voids between finely formed patterns are removed.
다이나믹 랜덤 액세스 메모리(DRAM)는 지난 몇해동안 고집적도 기술에 있어서 눈부신 향상을 하였으며, 이미 주류는 64K에서 256K에로 변천하여 1M비트에 이르기까지 생산되는 상태에 이르렀다. 이러한 고집적도의 DRAM에서는 셀면적을 점점 줄이면서도 일정한 셀 스토리지 커패시터 용량을 유지할 수 있어야 한다. 예를 들면 64M비트의 DRAM에서는 셀면적은 약 0.8μm2로 작아지게 된다. 반도체 제조 공정상 마지막 단계로 금속막 상부에 층간절연막을 형성하는데, 상기와 같이 반도체 소자의 제조기술이 발달하고 소자의 집적도가 증가됨에 따라서 소자의 크기는 감소하게 되므로 금속라인 사이의 공간 또한 좁아지게 된다.Dynamic Random Access Memory (DRAM) has made significant strides in high-density technology over the past few years, and the mainstream has already moved from 64K to 256K, producing up to 1Mbits. In such high-density DRAMs, the cell area must be reduced while maintaining constant cell storage capacitor capacity. For example, in a 64-Mbit DRAM, the cell area is reduced to about 0.8 μm 2 . As a final step in the semiconductor manufacturing process, an interlayer insulating film is formed over the metal film. As the manufacturing technology of the semiconductor device is developed and the degree of integration of the device is increased, the size of the device decreases, so that the space between the metal lines is also narrowed. do.
제1도는 종래의 제조방법에 따른 금속라인부의 단면도이다.1 is a cross-sectional view of a metal line part according to a conventional manufacturing method.
반도체 기판(2) 상에 층간절연막(3)을 형성한 후 상기 층간절연막(3) 상부에 금속막을 형성하고 상기 금속막을 식각하여 금속라인(4,5)을 형성한 후 1차, 2차 층간절연막을 연속적으로 형성시킨다.After the interlayer insulating film 3 is formed on the semiconductor substrate 2, a metal film is formed on the interlayer insulating film 3, and the metal film is etched to form metal lines 4 and 5. An insulating film is formed continuously.
이때 1M DRAM 이하에서는 문제가 되지 않으나 4M DRAM 이상에서는 금속라인 사이의 간격이 1μm 이하가 되므로 금속라인 사이에 공백이 발생하는 문제가 있었다. 더구나 최근 개발되고 있는 64M 비트 이상의 DRAM에서는 셀 자체의 면적도 1μm2에 미치지 못하므로 상기의 공백에 관한 문제는 더욱 심각하다.At this time, it is not a problem below 1M DRAM, but above 4M DRAM, there is a problem that a gap is generated between metal lines since the gap between metal lines is 1 μm or less. In addition, in the recent development of 64Mbit or larger DRAM, the area of the cell itself is less than 1μm 2 , and thus the above-mentioned space problem is more serious.
즉 통상의 반응성이온 식각을 행한 금속라인 상에 1차 층간절연막 형성시 화학기상증착(CVD) 특성에 의해 금속라인 상부영역에서는 층간절연막이 두껍게 형성되고 금속라인 하부영역에서는 층간절연막이 얇게 형성된다. 따라서 금속라인 하부영역에서는 층간절연막 사이의 간격이 매우 좁아서 2차 층간절연막 형성시 막의 형성을 제한하기 때문에 금속라인 하부 근처에서 공백이 생기게 된다. 이렇게 발생된 공백은 습기의 소오스(source)로 작용하여 소자의 신뢰성을 저감시킬 뿐만 아니라 스트레스(stress) 등으로 인하여 소자의 특성을 저하시킨다.In other words, when the primary interlayer insulating film is formed on a metal line subjected to conventional reactive ion etching, the interlayer insulating film is thickly formed in the upper region of the metal line and thinly formed in the lower region of the metal line by chemical vapor deposition (CVD). Therefore, in the lower area of the metal line, the gap between the interlayer insulating films is very narrow, thereby limiting the formation of the film when forming the secondary interlayer insulating film, so that a space is formed near the bottom of the metal line. The voids thus generated act as a source of moisture to reduce the reliability of the device and to degrade the device characteristics due to stress.
따라서 본 발명의 목적은 미세하게 형성된 패턴 사이의 공백(void)이 제거된 반도체 소자의 제조방법을 제공하고자 한다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which voids between finely formed patterns are removed.
상기와 같은 목적을 달성하기 위하여 본 발명은 반도체 기판 상부에 층간절연막과 금속막을 형성한 후 소정의 금속라인 패턴대로 포토레지스터를 형성하는 단계와, 금속막을 수직방향으로 식각하고 포토레지스터의 측벽을 식각하는 단계와, 상기의 식각공정을 소정의 금속라인이 명확히 분리될 때까지 수회 반복 실행하는 단계와, 상기의 반도체 기판 전면에 층간절연막을 형성하는 단계로 구성되는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming an interlayer insulating film and a metal film on the semiconductor substrate and then forming a photoresist according to a predetermined metal line pattern, etching the metal film in a vertical direction and etching sidewalls of the photoresist And a step of repeatedly performing the etching process until a predetermined metal line is clearly separated, and forming an interlayer insulating film on the entire surface of the semiconductor substrate.
이하 본 발명을 도면을 참조로 하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the drawings.
제2도 (a)에서 제2도 (d)까지는 본 발명의 일실시예에 따른 제조공정도이다.2 (a) to 2 (d) is a manufacturing process diagram according to an embodiment of the present invention.
제2도 (a)에 도시된 바와 같이 반도체 기판(20) 상부에 층간절연막(21)을 형성하고 그 다음 상기 층간절연막(21) 상부에 금속막(22)를 형성한다. 그 다음 상기 금속막(22) 상부에 포토레지스터(P,R)를 식각하여 패턴을 만든다.As shown in FIG. 2A, an interlayer insulating film 21 is formed over the semiconductor substrate 20, and then a metal film 22 is formed over the interlayer insulating film 21. Next, photoresists P and R are etched on the metal layer 22 to form a pattern.
그후 제2도 (나)에 도시된 바와 같이 상기의 포토레지스터(P, R) 패턴을 이용하여 상기 금속막(22)을 수직방향으로 약 1000Å 이하의 두께로 이방성식각후 포토레지스터(P, R)의 측벽을 약 250Å 이하로 식각한다. 이때 이 이방성식각은 145SCCM(Standard Cubic Centi Meter)의 BCl3가스, 35SCCM의 Cl2가스 그리고 10SCCM의 CHF3가스를 25mT의 압력하에서 200Volt의 파워를 사용하여 분당 1000Å의 식각률로 건식식각하였다. 그리고 포토레지스터(P,R)의 측벽은 70SCCM의 O2가스, 30SCCM의 CH3가스를 52mTorr의 압력하에서 1300Watt의 파워로 식각하였다.Thereafter, as shown in FIG. 2B, after the anisotropic etching of the metal film 22 in the vertical direction using the photoresist P and R patterns, the photoresist P and R The sidewalls of the etch are etched to about 250 mm 3 or less. At this time, the anisotropic etching was carried out dry etching of 145SCCM (Standard Cubic Centi Meter) BCl 3 gas, 35SCCM Cl 2 gas and 10SCCM CHF 3 gas at an etching rate of 1000Å per minute using a power of 200Volt at 25mT pressure. The sidewalls of the photoresists P and R were etched with O 2 gas of 70 SCCM and CH 3 gas of 30 SCCM at a power of 1300 Watt under a pressure of 52 mTorr.
제2도의 (c)에 도시된 바와 같이, 상기의 (b)공정, 즉 금속막의 수직방향 식각과 포토레지스터의 측벽식각공정을 수회 반복 실행한다. 이 공정은 상기의 (b)공정과 같은 조건하에서 소장 패턴의 금속라인이 명확히 형성될때까지 반복 실행한다.As shown in FIG. 2C, the above-described step (b), that is, the vertical etching of the metal film and the sidewall etching of the photoresist are repeatedly performed several times. This process is repeated until the metal line of the small pattern is clearly formed under the same conditions as the above step (b).
그후 제2도의 (d)에 도시된 바와 같이 최종적으로 그 상부에 층간절연막(26)을 형성한다.Thereafter, as shown in FIG. 2D, an interlayer insulating film 26 is finally formed thereon.
1회 식각량을 감소시키고 반복 실행의 회수를 증가시키게 되면 단차를 감소시킬 수 있게 되어 제3도에 도시된 바와 같이 완만한 곡선을 형성할 수 있게 된다. 또한 금속막의 이방성식각량과 포토레지스터의 측벽식각량을 적당히 조절함으로써 원하는 경사각을 임의로 조절가능하게 된다.Reducing the amount of one-time etching and increasing the number of repetitive executions can reduce the step and form a gentle curve as shown in FIG. Further, by appropriately adjusting the anisotropic etching amount of the metal film and the sidewall etching amount of the photoresist, the desired tilt angle can be arbitrarily adjusted.
이하에 또하나의 실시예로서 본 발명의 반도체 소자를 구비한 DRAM(Dynamic Random Access Memory)에 관하여 도면을 참조로 하여 상세히 설명하겠다.Hereinafter, as another embodiment, a DRAM (Dynamic Random Access Memory) having a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
제4도의 (a)에서 (d)까지는 본 발명의 반도체 소자를 구비한 DRAM의 제조공정도이다.4A to 4D are manufacturing process diagrams of a DRAM including the semiconductor element of the present invention.
제4도의 (a)에 도시된 바와 같이, P형 반도체 기판(41)상에 필드산화막(42)을 형성하고, 게이트전극(44)을 형성한 후 이온주입 공정을 통하여 소오스 드레인 불순물 영역(43,43＇)을 형성한다.As shown in FIG. 4A, the field oxide film 42 is formed on the P-type semiconductor substrate 41, the gate electrode 44 is formed, and then the source drain impurity region 43 is formed through an ion implantation process. 43 ＇).
그후 제4도의 (b)에 도시된 바와 같이 반도체 기판(41) 전면에 층간절연막(45)을 형성하고 개구부(46)를 형성한 후 금속막(47)을 형성하고, 상기 금속막(47) 상부에 포토레지스터(P, R)를 식각하여 패턴을 만든다.Thereafter, as shown in FIG. 4B, an interlayer insulating film 45 is formed on the entire surface of the semiconductor substrate 41, an opening 46 is formed, and then a metal film 47 is formed, and the metal film 47 is formed. The photoresist P and R are etched to form a pattern.
그후, 제4도 (c)에 도시된 바와 같이 상기의 포토레지스터(P, R) 패턴을 이용하여 상기 금속막(47)을 수직방향으로 약 1000Å 이하의 두께로 이방성식각한 후 포토레지스터(P,R)의 측벽을 약 250Å 이하로 식각한다. 이때 이 이방성 식각은 145SCCM(Standard Cubic Centi Meter)의 BCl3가스, 35SCCM의 Cl2가스 그리고 10SCCM의 CHF3가스를 25mT의 압력하에서 200Volt의 파워를 사용하여 분당 1000Å의 식각률로 건식식각하였다. 그리고 포토레지스터(P,R)의 측벽은 70SCCM의 O2가스 그리고 300SCCM의 CHF3가스를 52mT의 압력하에서 1300Watt로 식각하였다. 연속하여 상기의 금속막의 수직방향식각과 포토레지스터의 측벽 식각 공정을 소정 패턴의 금속라인이 명확히 형성될 때까지 수회 반복 실행한다.Thereafter, as shown in FIG. 4 (c), the metal film 47 is anisotropically etched to a thickness of about 1000 mm or less in the vertical direction by using the photoresist patterns P and R, and then the photoresist P , Sidewalls of R) are etched to about 250 mm 3 or less. At this time, the anisotropic etching was carried out dry etching of 145SCCM (Standard Cubic Centi Meter) BCl 3 gas, 35SCCM Cl 2 gas and 10SCCM CHF 3 gas at an etching rate of 1000Å per minute using a power of 200Volt at 25mT pressure. The sidewalls of the photoresist P and R were etched at 1300 Watts under a pressure of 52 mT, with O 2 gas of 70 SCCM and CHF 3 gas of 300 SCCM. Subsequently, the vertical etching of the metal film and the sidewall etching process of the photoresist are repeatedly performed several times until the metal line of the predetermined pattern is clearly formed.
그후 제4도의 (d)에 도시된 바와 같이 최종적으로 그 상부에 층간절연막(48)을 형성한다.Thereafter, as shown in FIG. 4 (d), an interlayer insulating film 48 is finally formed thereon.
종래의 반응성 이온에칭에 의한 것과 비교해 볼 때 이방성식각만으로 금속라인의 모서리 부분을 경사식각함으로써 금속라인 사이의 공백의 발생없이 보호막을 형성시킬 수 있다.Compared with the conventional reactive ion etching, a protective film can be formed without generating spaces between the metal lines by inclining the corner portions of the metal lines only by anisotropic etching.
상술한 바와 같이 본 발명은 금속라인 상부 모서리 부분을 경사식각함으로써 금속라인 사이에서 발생되는 불필요한 공백을 제거하여 반도체 장치의 전기적 성질을 향상시킬수 있게 되었으며, 뿐만 아니라 이방성식각만으로 금속라인을 형성하게 되므로 그 공정도 용이해졌다.As described above, the present invention can improve the electrical properties of the semiconductor device by eliminating unnecessary spaces generated between the metal lines by inclining the upper edge portions of the metal lines, as well as forming the metal lines only by anisotropic etching. The process also became easy.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910022781A KR940008767B1 (en) | 1991-12-12 | 1991-12-12 | Fabricating method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910022781A KR940008767B1 (en) | 1991-12-12 | 1991-12-12 | Fabricating method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930014996A KR930014996A (en) | 1993-07-23 |
| KR940008767B1 true KR940008767B1 (en) | 1994-09-26 |
Family
ID=19324659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910022781A KR940008767B1 (en) | 1991-12-12 | 1991-12-12 | Fabricating method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940008767B1 (en) |
-
1991
- 1991-12-12 KR KR1019910022781A patent/KR940008767B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930014996A (en) | 1993-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4690729A (en) | Tapered trench process | |
| US5126916A (en) | Stacked capacitor dram cell and method of fabricating | |
| US7268402B2 (en) | Memory cell with trench-isolated transistor including first and second isolation trenches | |
| US5668038A (en) | One step smooth cylinder surface formation process in stacked cylindrical DRAM products | |
| US5552334A (en) | Method for fabricating a Y-shaped capacitor in a DRAM cell | |
| US5010378A (en) | Tapered trench structure and process | |
| US4916511A (en) | Trench structure and process | |
| US6255682B1 (en) | Trench DRAM cells with self-aligned field plate | |
| US6825081B2 (en) | Cell nitride nucleation on insulative layers and reduced corner leakage of container capacitors | |
| US5567640A (en) | Method for fabricating T-shaped capacitors in DRAM cells | |
| US5631480A (en) | DRAM stack capacitor with ladder storage node | |
| US6977227B2 (en) | Method of etching bottle trench and fabricating capacitor with same | |
| JPH08236512A (en) | Polysilicon/polyside etching method for submicron gate stack | |
| US5798280A (en) | Process for doping hemispherical grain silicon | |
| US5837615A (en) | Integrated circuit device fabrication by plasma etching | |
| US5550077A (en) | DRAM cell with a comb-type capacitor | |
| US5909621A (en) | Single-side corrugated cylindrical capacitor structure of high density DRAMs | |
| US6541809B1 (en) | Method of making straight wall containers and the resultant containers | |
| KR940008767B1 (en) | Fabricating method of semiconductor device | |
| US6177695B1 (en) | DRAM using oxide plug in bitline contacts during fabrication | |
| US5696036A (en) | DRAM no capacitor dielectric process | |
| US6103571A (en) | Method for forming a DRAM capacitor having improved capacitance and device formed | |
| US6087217A (en) | Method for improving capacitance in DRAM capacitors and devices formed | |
| KR940009631B1 (en) | Manufacturing method of dram with trench capacitor | |
| JP2877354B2 (en) | Surface treatment method and semiconductor device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050802 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |