KR940008205B1 - Data protection circuit of nonvolatile memory - Google Patents

Abstract

a data protecting signal generating circuit for generating a data protecting signal by sensing a power voltage dropping to a first voltage level; and a clock pass cutoff circuit connected between a bias terminal of a clock generator and an output terminal of the data protecting signal generating circuit, for cutting off a clock output of the clock generator in response to the data protecting signal, thereby stably protecting data of the memory.

Description

Data protection circuit of nonvolatile memory

1 is a conventional nonvolatile memory control circuit diagram.

2 is an operating waveform diagram of FIG.

3 is a nonvolatile memory control circuit diagram according to the present invention.

4 is a detailed circuit diagram of the voltage divider and the constant voltage circuit shown in FIG.

5 is an operating waveform diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit for controlling a non-volatile memory, and in particular, to prevent abnormal write operations that occur when a power supply is cut off, thereby protecting the contents of the nonvolatile memory. It is about.

Examples of general memory control circuits include non-volatile memory, for example, a read-only memory (EPROM) that can be electrically erased and programmed using a memory control means such as a CPU (Central Processing Unit) or an MPU (Microprcessor). The configuration of a system for controlling data write and read is shown in FIG.

1 is a conventional memory control circuit diagram for controlling access to a nonvolatile memory using an MPU. The MPU 11 controls all operations of a system, and a nonvolatile memory that maintains and stores stored data even when a power is turned off. A memory 12, a generator 18 for generating an operation reference clock of the MPU 11, and a program memory 13 for storing and providing work to be processed in the MPU 11;

The clock generator 18 shown in FIG. 1 is composed of two capacitors 16 and 17 and a crystal oscillator 14, and is connected to the oscillation stages OSC1 and OSC2 of the MPU 1. Such a configuration is one embodiment of a circuit having a clock oscillation circuit inside the MPU 11, and when the MPU 11 does not have a built-in clock oscillation circuit, the clock generator 18 is independently as is widely known. The operation clock of the MPU 11 should be generated.

In the first diagram, DATA B is a data bus, ADD 8 is an address bus, and CTL B is a control signal bus.

2 is an operational waveform diagram of FIG. 1, (a) is a waveform diagram of the power supply voltage VDS, and (b) is a waveform diagram of the clock generator 18 related to the level of the power supply voltage VDS.

When the power supply voltage VDS input to the circuit configured as shown in FIG. 1 now reaches a normal voltage as shown in " VDS " in FIG. 2A, the MPU 11 is built-in or externally connected to the program memory 13 The system is controlled in accordance with the contents of " At this time, the clock generator 18 oscillates at a natural oscillation frequency and is input to the clock input terminal OSC2 of the MPU 11 to serve as a reference for system operation.

However, the control circuit of the conventional nonvolatile memory 12 configured as shown in FIG. 1 operates well when the power supply is "on" and the power supply voltage VDS is normal, but the power supply "as shown in FIG. An abnormal operation occurs when the time interval t1-t2 of the state of changing from about 0.8 times to about 0.3 times the normal power supply voltage VDS in the "off" state t0 is several milliseconds [ms] or more.

That is, the power supply voltage VDS is " off " at the point t0 in FIG. 2 (a) so that the level 34 of the input power supply voltage VDS falls with the same period as t1 and t2 in FIG. In this case, the clock period output from the clock generator 18 is converted as shown in FIG. Therefore, the MPU 11 operates in an abnormal state by changing the reference clock amplitude input to the MPU 11.

An abnormal write operation occurs in the nonvolatile memory 12 due to an abnormal operation of the MPU 11, resulting in the destruction of data contents stored in the memory 12. In order to prevent such an abnormal operation, the value of the capacitor 15 between the power terminal and the ground terminal of the MPU 11 may be made sufficiently small so that the time interval t2-t1 in FIG. 2 is 1 ms or less, but this is in terms of power stabilization. By performing poor operation, it is almost impossible in the circuit which is actually applied.

Accordingly, an object of the present invention is to provide a circuit that detects a power supply voltage level input to a system and protects data of a nonvolatile memory by blocking a clock input to a memory controller when the voltage is below a first predetermined state.

Another object of the present invention is to provide a circuit for protecting the contents of the nonvolatile memory by stopping the operation of the MPU by controlling the operation of the clock by detecting that the input voltage falls below a predetermined voltage when the power is turned off.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram according to the present invention. The MPU 20 controls the system, the nonvolatile memory 21 which protects the stored contents without breaking data even when the power is turned off, and the MPU 20 is capable of processing. A program memory 22 for storing and providing work; a clock generator 33 for generating an operation reference clock of the MPU 20; and a voltage divider for dividing a power supply voltage VDS at a constant ratio and outputting a divided voltage ( 24 and a constant voltage circuit 25 for receiving the power supply voltage VDS and outputting a constant voltage at a predetermined level, and comparing the voltages output from the voltage divider 24 and the constant voltage circuit 25 to output a comparison signal. Comparator 26, a resistor 27 for pulling up the output of the comparator 28, and a diode 28 and a resistor 29 for transmitting the output of the comparator 26 to one terminal of the clock generator 33 do.

The operations of the MPU 20, the nonvolatile memory 21, the program memory 22, and the clock generator 33 in the configuration of FIG. 3 are the same as those in FIG.

4 is a detailed view of the voltage divider 24 and the constant voltage circuit 25 shown in FIG. 3, (a) is a detail view of the voltage divider circuit 24, (b) is a detail view of the constant voltage circuit 25, (c) is a detailed circuit diagram of still another embodiment of the constant voltage circuit 25.

The voltage dividing circuit 24 of FIG. 4 (a) is configured in series connection of the voltage dividing resistor 42 and the resistor 43 between the power supply voltage VDS and the ground GND. Outputs a level voltage (VDS x 0.6) of about%. At this time, the resistance ratio of the resistor 42 and the resistor 43 is set at a ratio of 4: 6 so as to have a level of about 60% of the power supply voltage VDS to which the divided output voltage is input.

The constant voltage circuit 25 of FIG. 4 (b) has a constant voltage element for outputting a current limiting resistor 44 and a constant voltage VDS × 0.5 in a first predetermined state between a power supply voltage VDS and a ground GND. 45) are connected in series, clamped to the constant voltage of the first predetermined state of the power supply voltage VDS, and are sustained. The constant voltage element 45 of FIG. 4 (b) has a breakdown voltage which is stable with respect to Zener Diods or a temperature and time having a level (VDS × 0.5) of about 1/2 of the input power voltage VDS. A micropower voltage reference diode can be used to obtain the output.

FIG. 4 (c) is another configuration example of the constant voltage circuit 25 shown in FIG. 3, which is a commercially available linear regulator 46, and stabilizes the power supply voltage VDS to 1/2 to input voltage VDS. The voltage VDS x (1/2) having the 1/2 level of? 47, 48, 49, and 50 in FIG. 4 (c) are capacitors.

5 is an operational waveform diagram of FIG. In FIG. 5, (a) shows the change curve 35 of the input power supply voltage VDS, the output curve 36 of the voltage divider 24 and the output curve 37 of the constant voltage circuit 25. As shown in FIG. It is shown. And (b) shows the output curve 38 of the comparator 26 and the change state curve 39 of the input power supply voltage VDS, (c) is the output waveform diagram of the clock generator 33. As shown in FIG.

An operation example of FIG. 3 according to the present invention will now be described with reference to FIGS. 4 and 5.

In the circuit according to FIG. 3, in the power supply "on" state and in the normal power supply voltage state, the same operation as that of the circuit of FIG. 1 is omitted. Therefore, the input power supply voltage VDS is as shown in FIG. The operation after the " off " state will be described in detail using FIG. 3 and FIG.

If the normal power supply voltage VDS is supplied to the circuit as shown in FIG. 3 now, the MPU 20, the nonvolatile memory 21, the program memory 22, and the clock generator 33, as described above in FIG. It works normally. At this time, the voltage divider 24 configured as shown in FIG. 4 (a) divides the input power supply voltage VDS by the internal resistor 42 and the resistor 43, thereby reducing the input voltage as shown in 36 of FIG. A voltage VDS x 0.6 having a 60% level of VDS is output and input to the non-inverting terminal (+) of the comparator 26. In the constant voltage circuit 25 configured as shown in FIG. 4B, the constant voltage VDS + having the input voltage VDS is 50% of the power supply voltage VDS by the constant voltage device 45. ) Is outputted to the inverting terminal (-) of the comparator 26 as shown in (37) of FIG.

The output of the voltage divider 24 and the output of the constant voltage circuit 25 are input to the non-inverting terminal (+) and the inverting terminal (-) of the comparator 26. The comparator 26 compares the two inputs and outputs a clock control signal input to the clock terminal OSC2 of the MPU 20. That is, the comparator 26 reduces the first predetermined state (power supply voltage state) by the pull-up resistor 27 when the voltage level input to the non-inverting (+) is higher than the voltage level input to the inverting terminal (-). In this case, the second predetermined state (ground voltage) is output to the cathode of the diode 28.

Therefore, if the power supply voltage VDS input to FIG. 3 is in a steady state as shown in (35) of FIG. The logic signal is outputted as a logic signal of the first scheduled state. At this time, the clock side terminal OSC2 of the crystal oscillator 34 in the clock generator 33 receives a bias voltage provided by the MPU 20 when there is no externally applied condition. This bias voltage is usually the power supply voltage VDS input to the MPU 20. Has a level of

Therefore, when the output of the comparator 26 has the first scheduled state, the diode 28 is “off”, so that a normal bias is applied to one terminal OSC2 of the clock generator 33. If the output of the comparator 26 has the second predetermined state (logical "low") as shown in FIG. 5 (b) 39, the diode 28 is turned "on" so that the drop voltage of the diode 28 is reduced. Since the clock oscillator 33 does not operate normally and stops oscillation as shown in FIG. Here, the resistor 29 connected between the one end terminal OSC2 of the clock generator 33 and the output terminal of the comparator 26 prevents the rapid flow of current when the diode 29 is "on".

The waveform diagram of each terminal in the power-off state is as shown in FIG.

Therefore, the present invention shows that when the power supply voltage VDS becomes about 80% of the normal power supply voltage, the value of the non-inverting terminal (+) of the comparator 26 starts to be smaller than that of the inverting terminal (-). have. At this time, the output of the comparator 26 transitions from the first scheduled state to the second scheduled state within a few μS, and the bias voltage of one terminal OSC2 of the clock generator 33 also transitions to about 0.6V to stop clock generation. All operations of the MPU 20 are stopped at the same time as generation stops.

Therefore, since all operations are stopped from the moment when the voltage drops to about 80% of the normal power supply voltage, the control of the abnormal nonvolatile memory 21 can be prevented and the stored contents can be safely protected without being destroyed.

As described above, according to the present invention, when the level of the power supply voltage is lower than or equal to a predetermined voltage, the data of the memory can be protected at the same time as the power supply voltage fluctuation by quickly blocking the clock of the microprocessor controlling the data access of the nonvolatile memory.

Claims (5)

A nonvolatile memory, memory control means operated by an input of a clock to access data in the nonvolatile memory, and a clock generator for generating a predetermined clock and supplying the memory control means by inputting a power supply voltage VDS. A data protection circuit of a nonvolatile memory including: a constant voltage circuit (25) for maintaining and outputting the power supply voltage (VDS) at a voltage of a first level, and dividing the power supply voltage (VDS) to divide the constant voltage; A data protection signal generating means for detecting the power supply voltage VDS falling below the voltage of the first level in comparison with the output level of the circuit 25 and outputting a data protection signal; a bias terminal of the clock generator; It is connected between the output terminals of the data protection signal generating means and outputs the data protection signal from the data protection signal generating means. And a clock path blocking means for blocking a clock output of the clock generator in response to the clock generator to block the clock of the clock oscillator when the power supply voltage VDS falls below a predetermined voltage to protect data in the nonvolatile memory. A data protection circuit of a nonvolatile memory, characterized by operating forever. A nonvolatile memory, memory control means operated by an input of an operation clock to access data in the nonvolatile memory, and a predetermined clock is generated by input of a power supply voltage VDS to generate an operation clock to the memory control means. A data protection circuit of a nonvolatile memory having a clock generator provided, comprising: a constant voltage circuit 25 which maintains and outputs the power supply voltage VDS at a voltage of a first level, and the power supply voltage VDS at a predetermined ratio. The voltage divider 24 compares the voltage of the first level output from the constant voltage circuit 25 and the voltage divider 24 and the divided voltage to divide the voltage into the voltage of the first level. The comparator 26 which detects this at the time of transition and outputs the data protection signal, and between the bias terminal of the clock generator and the output terminal of the data protection signal generating means. It is, and the comparator 26 output signal data protection non-volatile memory of the data protection circuit characterized in that it consists of a clock path blocking means to block the output of the clock generator in response to the on the inside. 3. The circuit according to claim 2, wherein the clock path blocking means comprises a current connection resistor 29 and a diode 28 connected in series from the bias terminal of the clock generator toward the output terminal of the comparator 26. . 4. The voltage divider 24 has at least two resistors connected in series between an input terminal of the power supply voltage VDS and a ground terminal, and supplies the power supply voltage VDS to the power supply. And a voltage having a level of about 0.6 times the voltage VDS as a divided voltage. The constant voltage circuit (25) according to claim 4, wherein the constant voltage circuit (25) outputs a current limiting resistor (44) and a first level constant voltage (VDS x 0.5) between the power supply voltage (VDS) and ground. Is connected in series and clamped to the voltage of the first level of the power supply voltage (VDS) to maintain and output the data.