KR940007981B1 - Digital subscriber matching circuit - Google Patents

Abstract

The circuit easily detects an abnormal state by a test program in the subscriber matching device, and improves reliability for matching. The circuit includes an overvoltage protector (211) which suppresses an overvoltage, a test access unit (213) which transfers a telephone line, an U-transceiver (213) which connects to the output of test access unit (212), a multi U-interface means (21), an ISDN exchange power controller (IEPC:22), an extension PCM matching control measn (EPIC:23), a TSL matching means (28), an ISDN D channel exchange control means (IDEC:24), a memory map decoding means (25), a LC bus matching means (31), an interrupt processing means(26), and a MMC port (32).

Description

Digital subscriber matching circuit with line code 2BIQ using GCI mode

1 is a block diagram of an ISDN basic speed subscriber matching apparatus to which the present invention is applied;

2 is a detailed block diagram of the present invention.

* Explanation of symbols for main parts of the drawings

21: U-interface part 22: IEPC

23: EPIC 24: IDEC

25: memory map decoder 26: interrupt handler

27: CPU 28: time switch connection matching unit

29: memory unit 30: common memory (CM)

31: L-C bus matching unit 32: MMC port

33: address, data, control 34: GCI bus

The present invention relates to a subscriber matching circuit mounted in an ISDN basic speed subscriber matching device of an electronic switching system.

As the demand for communication technology increases, demand for ISDN functionality is added to existing electronic switchboards, and the development of digital subscriber matching devices to meet the needs is urgently needed.

Accordingly, the ISDN basic speed subscriber matching device uses a circuit code of 4B3T (4 Bitary 3 Ternary) or 2B1Q (2 Bianry 1 Quarternary) circuit depending on the transmission method in order to effectively transmit digital signal information through the subscriber line. The service can be arbitrarily mounted.

Accordingly, an object of the present invention is to provide a subscriber matching circuit implemented using a National Semiconductor's TP3410 device as a U-transceiver to effectively provide a service required for a digital subscriber matched to an all-electronic exchange.

In order to achieve the above object, the present invention provides an overvoltage protection device connected to an input of a subscriber line to suppress overvoltage flowing from a subscriber line, and a test access connected to an output of the overvoltage device and connected to a test apparatus to transfer a line. And a plurality of U-interface means having a U-transceiver connected to an output of the test access unit and one side of a subscriber line via an overvoltage protection element in the U-interface means, thereby shorting the power supply for the subscriber. Is connected to the subscriber circuit by connecting the ISDN Switching Power Controller (IEPC) to the power supply from the matching circuit and receiving the minimum service, and the Universal Circuit Matching Bus (GCI) bus to the U-transceiver in the U-interface means. An extended PCM matching control means (EPIC) for time-divisionally switching and outputting a channel inputted from TSL matching means connected to the control means for adjusting the data transmission and reception level to the TTL level, address, data, control bus connected to the U-transceiver, the extended PCM matching control means (EPIC) and the ISDN switched power controller (IEPC). And an ISDN D-channel switching control means (IDEC) for processing D-channel data connected to the address, data, and control bus, a memory unit connected to the address, data, and control bus to process layer 1 functions; Memory map decoding means connected to an address, data and control bus to classify the addresses of the respective functional circuits, common memory and IC bus matching means connected to the address, data and control bus and controlling bus access; CPU, which is connected via the data and control buses to perform central control functions, and manages the priority of interrupts by being connected through the address, data and control buses. Interrupt processing means, and the MMC port is connected via the address, address, control bus and configured to configure the RS-232C matching unit to perform the test and maintenance functions.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an ISDN basic speed subscriber matching device to which the present invention is applied, and a peripheral configuration thereof, in which 10 is an ISDN basic speed subscriber matching device according to the present invention, 1 is a subscriber matching circuit, 2 is an IDPA matching circuit, and 3 is a time switch. (TSW) matching circuit, 4 is FMXP matching circuit, 5 is ISAP matching circuit, 6 is alarm equipment matching circuit, 7 is test equipment matching circuit, 8 is subscriber line matching circuit.

The ISDN subscriber matching circuit (1) of the present invention is a part directly connected to the ISDN subscriber line matching circuit (8) and uses an echo cancellating method for full duplex communication, and the subscriber line matching circuit (8) It performs overvoltage protection function to be introduced to department, test function to test subscriber line side and exchange side, and supply power in case of power failure of terminal side.

In addition, the present invention matches the basic speed digital subscriber (2B + D) using the 2B1Q line code to the electronic switching system, and separates the signals of 2B + D into B and D channels, and uses a maintenance channel for the exchange. Increase the communication reliability between the terminal and the terminal. Channel B is a 2.048 MHz bidirectional subhighway cable connected to the time switch matching circuit (3) in units of two subscriber matching boards, and the 8 kHz FS signal and 4.096 MHz required for the subscriber matching board from the time switch matching circuit (3). Receives a clock signal. Data for controlling D-channel and subscriber matching board is transmitted / received to IDPA matching circuit 2 using common memory in subscriber matching board, and subscriber matching device to provide a path for testing subscriber line side and exchange side. Connect the test device matching circuit (7) as a unit.

In addition, when the power is turned on or manually reset, a safety test is performed to output normality to a CRT terminal, and an ISAP (ISDN Subscriber Access Processor) matching circuit (2) is provided through an IDPA (ISDN D-ch. Processing Board Assembly) matching circuit (2). Report). The MMC port mounted on the board can be used to perform a test program embedded in the warpware, and can also be controlled from the ISAP matching circuit (5) through the IDPA matching circuit (2) during system operation.

Meanwhile, the IDPA matching circuit 2 processes the D-channel received by the subscriber matching circuit 1 to provide signaling information for circuit switching, various fault information in the subscriber matching device, status information, and subscriber matching device. Control information for various maintenance is exchanged with the ISAP matching circuit 5 through the TD-bus, and the packet message information among the D channel information received from the subscriber matching circuit 1 of the present invention is D-channel link access processing. (LAPD) is separated and transmitted to the frame malutiplex processor (FMXP) matching circuit through DP-bus in subunit units, and the packet message information transmitted from the output of the PMXP matching circuit (4) is multiplexed onto one D channel. do.

In addition, the IDPA matching circuit 2 collects the failures generated in the subscriber matching circuit 1 in one basic block unit and notifies the alarm device 6 directly. The type of alarm includes function failure information. , Board stripping information, cable stripping information, etc. to facilitate maintenance.

In addition, the ISDN basic speed subscriber matching apparatus to which the present invention is applied may mount a DC / DC converter, IDPA, subscriber matching circuit board and cable on one back board, and accommodate up to 128 subscribers of ISDN basic speed subscriber.

2 is a detailed block diagram of the present invention, in which 21 is an U-interface part, 211 is an overvoltage protection device, 212 is a test access part, 213 is a U-transceiver, and 22 is an ISDN switched power controller (hereinafter referred to as IEPC). 23 is an extended PCM matching controller (hereinafter referred to as EPIC), 24 is an ISDN D-channel switching controller (hereinafter referred to as IDEC), 25 is a memory map decoder, 26 is an interrupt handler, 27 is a CPU and 28 is a time switch connection. Matching section (hereinafter referred to as TSL), 29 is a memory section, 30 is a common memory (CM), 31 is an LC bus matching section, 32 is an MMC port, 33 is an address, data, control bus, and 34 is general purpose circuit matching Represent each bus (GCI bus).

The subscriber matching circuit of the present invention is a circuit for performing a matching function between an exchanger and an NT1 (Network Terminator 1), and the ECH (Echo Cancellation with Hybrib) method and 2B + D basic speed for full-duplex communication with the NT1 and 2 wires. Use the 2B1Q line code to transmit. The 2B + D channel is separated from the data coming into the subscriber, and the 2B channel is transmitted to the TSL (Time Switch Link) block through the IDPA (2), and the D-channel data is transmitted through the IDEC (24) to the LC-bus (Line Controller Bus). Is transmitted to the IDPA (2).

Referring to the drawings and the configuration and operation according to an embodiment of the present invention in detail.

The U-transceiver 213 in the U-interface unit 21 is a TP 3410 IC chip manufactured by National Semiconductor Corporation. The U-transceiver 213 is designed to have a bus structure of a general circuit interface (GCI) mode among various modes. + D Put data on the assigned GCI channel. The D channel is transmitted to the IDEC 24 and the B channel is transmitted to the EPIC 22. In addition, the U-transceiver 213 includes many registers therein, and the CPU 27 can control the GCI bus 34 through the EPIC 23 in order to control these registers.

Each subscriber has a time slot of 256 Kbps designated per line, and transmits an activation request status from the subscriber to the EPIC 22 using the C / I channel, and the EPIC 22 requests an interrupt to the interrupt handler 26. The CPU can monitor the subscriber's C / I channel, and the subscriber's activation / deactivation request and various loop back request signals from the CPU 27 are switched to the C / T channel, and the monitor channel is It can also be used to determine the registration status and availability of the subscriber. The procedure for activation and deactivation is in accordance with CCTTT I.430 and is designed to mount 8 circuits of 2B1Q within the matching circuit board.

The EPIC 23 uses Siemens PEB 2055. In the EPIC 23, the 2B channel coming from the subscriber side is allocated to a 32 channel time slot and then connected to the TSL matching unit 28 for time division switching. The 2.048 Mbps data is switched to B1 and B2 of the GCI bus 34.

IDEC (24) is implemented using Siemens PEB 2075, can process D-channel data, and is implemented in the present invention, the two are implemented, subscribers 0-3 is the first IDEC, 4-7 subscribers The second IDEC processes the D channel data. The four D-channel controllers are designed in a single connection mode, which is multiplexed and connected to one GCI bus 34, and have a demultiplexed bus structure, and are designed to process both signals and packet data as D-channels.

The CPU 27 uses the Z-180 processor, 8-bit Zylog Corporation, and performs the initialization of the matching circuit, D-channel transmission and reception, and maintenance, and also uses the I / O port for LED control, IEPC control, Matched circuit board selection reads and board mounting positions for time slot designation are available. In addition, it separates the D channel from the 2B + D channel coming from the user side and transmits it to the IDPA (2) matching circuit, and transmits the D channel received from the IDPA (2) to the corresponding subscriber. It is configured to perform power supply and matching circuit reset.

The common memory 30 and the LC-bus matching unit 31 are each implemented with two 2Kbyte dual port RAMs and a gate array logic (GAL). It always has a high priority and if the IDPA 2 is accessing, the internal bus is put on standby by the BUSY signal and implemented to be accessible later.

The memory map decoder (7) circuit is implemented by GAL. In order to perform matching circuit control function, it performs functions such as initialization, control, and separation of 2B + D channels, so that each circuit can be accessed. The decoder circuits were used to classify the circuit addresses, respectively.

IEPC (22) is implemented by PEENS 2025 of Gence, so that when the commercial power supply of the subscriber is short-circuited to supply the power from the matching circuit to receive a simple service.

The memory unit 29 is composed of a ROM and a RAM to provide a 32 Kbyte area, respectively, and implemented to process the functions of Layer 1 by firmware (F / W).

The TSL matching unit 28 is designed to transmit and receive data at the TTL level by implementing the RS-422 driver / receiver.

The interrupt handler 26 is implemented with an AM 9519 IC. This device supports interrupt levels of seven levels. When an interrupt occurs, the interrupt handler 26 enters the service according to the priority and releases the signal by receiving an ACK signal from the CPU 27. It is designed to be.

The test access unit 212 of the U-interface unit 21 was constructed as a relay that can cut the line to the subscriber line side or the exchange side, and the overvoltage protection circuit 211 suppresses the overvoltage flowing from the subscriber line side and the other. The CCTTT K.20 is satisfied to protect the subscriber matching circuit.

The MMC port 32 constituted an RS-232C interface to perform a test and maintenance function using a CRT.

Therefore, the present invention configured and operated as described above uses a U-transceiver IC chip manufactured by National Semiconductor, which incorporates a clock compensation circuit in a 2B1Q scheme, thereby providing various services including voice and non-voice systems in an ISDN exchange. Therefore, it is easy to match with the basic speed digital terminal. In addition, by using the test program built in the subscriber matching device to which the present invention is mounted, it is possible to easily perform maintenance by detecting a transmission line failure state, thereby improving reliability in matching with a basic speed subscriber.

Claims (1)

An input voltage connected to the subscriber line to suppress the overvoltage flowing from the subscriber line side overvoltage protection device 211, the test access unit connected to the output of the overvoltage element 211 and connected to the test device 7 to transfer the line 213, a plurality of U-interface means 21 having a U-transceiver 213 connected to the output of the test access unit 212, and an overvoltage protection element in the U-interface means 21 An ISDN switched power controller (IEPC; 22) connected to one side of the subscriber line via 212 to supply power from the matching circuit when the subscriber's power supply is short-circuited, and the U- Expansion PCM matching control means 23 (EPIC) connected to the U-transceiver 213 in the interface means 21 as a universal circuit matching bus (GCI) bus for time-divisionally switching and outputting a channel input from the subscriber side; PCM TSL matching means 28 connected to the matching control means 23 for adjusting the data transmission / reception level to the TTL level, the U-transceiver 213 and the extended PCM matching control means 23 (EPIC), and the ISDN switched power supply. An address, data and control bus 33 connected to the controller (IEPC) 22, an ISDN D channel exchange control means (IDEC) 24 connected to the address and data control bus 33 to process D channel data, A memory unit 29 connected to the address and data control bus 33 to process the functions of layer 1, and a memory map decoding connected to the address, data and control bus 33 to classify the addresses of the respective functional circuit units. Means 25 and the common memory 30 and LC bus matching means 31 which are connected via the address, data and control bus 33 and which control bus access, and are connected via the address, data and control bus. CPU 27 serving as a central control function, the address, data, Interrupt processing means 26 connected via the control bus to manage the priority of the interrupt, and MMC port connected to the address, address, control bus and configured RS-232C matching unit to perform the test and maintenance function ( 32. A subscriber matching circuit, comprising: 32).