KR940007980B1 - Isdn subscriber matching device - Google Patents

Abstract

The devcie effectively matches an exchanger to a basic speed (2B+D) subscriber, and efficiently gives service to digital subscriber. The device includes an ISDN basic speed subscriber matching circuit (1) which receives a 8KHz FS signal and 4.096 MHz clock signal, transmits/receives data for control of D channel and the subscriber matching board, and gives a path between the subscriber line and the exchanger, and an ISDN D-channel processing board (IDPA) (2) which exchanges control information through an ISAP matching circuit (5) and TD-bus, and multiplexes packet message information into a D channel. The device includes an U-interface unit (81) which has PEB 20901,20902; IEC-t (812), a EPIC (82) which has PEB 2075, an interrupt processor (87) which is AM 9519, a CPU (86) which is Z-180, a common memory and LC-bus matching units (90,91) which have dual port RAM, a memory map decoder (84) which is 74LS138, a IEPC which is PEB 2025, a memory unit (89) which has ROM/ RAM(32Kbytes), a TSL matching unit (88) which is RS-422, and a clock compensation circuit (92) which is NE 564, 74LS93,and 74LS393.

Description

ISDN basic speed subscriber matching device

1 is a block diagram of the configuration of the present invention and the peripheral circuit.

2 is a detailed configuration diagram of an IDPA matching circuit.

3 through 6 illustrate embodiments of a subscriber circuit.

* Explanation of symbols for main parts of the drawings

10: ISDN basic speed subscriber matching device 1: subscriber matching circuit

2: IDPA matching circuit 3: Time switch (TSW) matching circuit

4: FMXP matching circuit 5: ISAP matching circuit

6: alarm device matching circuit 7: test device matching circuit

8: subscriber line matching circuit

The present invention relates to a subscriber matching device for receiving a basic access digital subscriber of an electronic switching system including an ISDN function.

In general, the ISDN digital subscriber matching device is for accommodating basic access digital subscribers in an electronic switching system and performs subscriber matching, D-channel protocol processing, and maintenance functions.

An object of the present invention is to provide an ISDN basic speed subscriber matching device that efficiently matches a basic speed (2B + D) subscriber with an exchange, and effectively provides a service required for a digital subscriber matched to an electronic switch.

In order to achieve the above object, the present invention is connected to the subscriber line matching device, the time switch matching circuit and the test device matching circuit to convert the basic speed digital subscriber (2B + D) using the 2B1Q line code and the 4B3T line code. 2B + D signals are separated into B and D channels, and the B channel is provided to the time switch matching circuit through a 2.048 MHz bidirectional subhighway cable in units of two subscriber matching boards. Receives 8Khz FS signal and 4.096MHz clock signal from subscriber matching board, transmits / receives data for D channel and subscriber matching board control, and checks subscriber line side and exchange side through test equipment matching circuit. ISDN basic speed subscriber matching circuit means for providing a path for testing, the ISDN basic speed subscriber matching circuit means, and frame multiplexing pro It is connected to the FMXP matching circuit and the alarm matching circuit, and processes the D-channel received by the ISDN subscriber matching circuit means to provide signaling information for circuit switching, various fault information in the subscriber matching device, status information, and the like. Control information for various maintenance of subscriber matching device is exchanged with ISAP matching circuit through TD-bus, and packet message information is separated from received D channel information after D-channel link access processing (LAPD). And an ISDN D-channel processing board (IDPA) matching circuit means for transmitting the packet message information transmitted from the FMXP matching circuit output to sub-unit units and multiplexing the packet message information transmitted from the output of the FMXP matching circuit. do.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

First, the configuration and operation of the present invention will be described as follows.

In order to implement the digital subscriber matching function, IDPA (ISDN D-ch. 1) for the interaction between other blocks such as subscriber matching board for processing Layer 1 including subscriber line and digital communication, and Layer 2 processing for D channel protocol. Processing Board Assembly) It consists of a power supply unit to supply the necessary power to these boards and a back board that can be easily mounted / separated.

The subscriber matching board is designed to accommodate two boards in the same back board to use echo cancellation between user terminals and line coding of 2B1Q or 4B3T, and each subscriber matching board accommodates 8 subscribers. 8 subscriber matching boards each have a common memory to communicate with the IDPA via a parallel bus. Two IDPA cards can be mounted on the same back board to accommodate 8 subscriber matching boards, and the LC bus can be independently used in the back board to increase reliability.

Subscriber matching boards include ISB Basic Access 2B1Q Board Assembly (IBQA) for 2B1Q line code and ISDN Basic Access 4B3T Board Assembly (1BTA) for 4B3T line code, depending on the line code. The D channel is separated and the D channel is sent to IDPA for LAPD processing. The D-channel information, which has completed layer 2 processing in IDPA, is separated by SAPI, and the signal information is transmitted to the ISAP (ISDN Subscnber Access Processor) block through the TD-bus. ISAP is redundant, and the TD-bus (Telephony Device-bus) has a bus select signal so that if one of the two ISAPs fails, the normal ISAP block takes over the control of the DSI hardware block. The packet message information is transmitted to a Frame Malutiplex Processor (FMXP) block through a D-ch Packer-bus (DP-bus), which is a basic bus in units of basic DSI blocks. The 2B data from the subscriber is connected to four subhighways to send and receive data, and the clock required for this is provided from a time switch link (TSL). In addition, when an error occurs, an alarm signal is generated and an alarm message is sent to the FIA.In the ISDN network, SAP points are formed between upper and lower layers to perform voice and non-voice matching functions of digital subscribers. (Layer) The D-channel protocol of CCTTT Recommendation Q.831 is used for communication with Layer B and Processor Communication (IPC) and for communication with lower layers.

The inventors of the present invention, i.e., ISDN basic rate subscriber matching device, will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of an ISDN basic speed subscriber matching device of the present invention and a peripheral configuration thereof, in which 10 is an ISDN basic speed subscriber matching device of the present invention, 1 is a subscriber matching circuit, 2 is an IDPA matching circuit, and 3 is a time switch (TSW). Matching circuit, 4 is FMXP matching circuit, 5 is ISAP matching circuit, 6 is alarm equipment matching circuit, 7 is test equipment matching circuit, 8 is subscriber line matching circuit.

The ISDN subscriber matching circuit 1 is a part directly connected to the ISDN subscriber line matching circuit 8 and uses an echo cancellation scheme for full duplex communication, and the subscriber line matching circuit 8 It performs overvoltage protection function from), test function to test subscriber line side and exchange side, and supply power in case of power failure of terminal side.

In addition, the basic speed digital subscriber (2B + D) using the 2B1Q line code and the 4B3T line code is matched to the electronic switching system, and the 2B + D signal is separated into the B and D channels, and the maintenance channel is used. Increase the communication reliability between the exchange and the terminal. The B channel is connected to the time switch matching circuit (3) via 2.048 MHz bidirectional subhighway cable in units of two subscriber matching boards, and the 8Khz FS signal and 4.096 required for the subscriber matching board from the time switch matching circuit (3). Receive a clock signal of MHz. Data for controlling D-channel and subscriber matching board is transmitted / received to IDPA matching circuit 2 using common memory in subscriber matching board, and subscriber matching device to provide a path for testing subscriber line side and exchange side. Connect with matching circuit (7).

In addition, by performing a safety test on power-on or manual reset, it outputs the normal status to the CRT terminal and the ISDN Subscriber Access Processor (ISAP) matching circuit (2) through the IDPA (ISDN D-ch. Processing Board Assembly) matching circuit (2). Report). The test program embedded in the firmware can be executed using the MMC port mounted on the board, and it can be controlled from the ISAP matching circuit (5) through the IDPA matching circuit (2) during system operation.

Meanwhile, the IDPA matching circuit 2 processes the D-channel received by the subscriber matching circuit 1 to provide signaling information for circuit switching, various fault information in the subscriber matching device, status information, and subscriber matching device. Control information for various maintenance is exchanged with the ISAP matching circuit 5 through the TD-bus, and the packet message information among the D channel information received from the subscriber matching circuit 1 of the present invention is D-channel link access processing. (LAPD) is separated and transmitted to the Frame Malutiplex Processor (FMXP) matching circuit through the DP-bus in subunit units, and the packet message information transmitted from the output of the FMXP matching circuit (4) is multiplexed onto one D channel. do.

In addition, the IDPA matching circuit 2 collects the failures generated in the subscriber matching circuit 1 in one basic block unit and notifies the alarm device 6 directly. The type of alarm includes function failure information. , Cord sheath information, and cable sheath information to facilitate maintenance.

In addition, the ISDN basic speed subscriber matching apparatus to which the present invention is applied may mount a DC / DC converter, an IDPA, a subscriber matching circuit board, and a cable on one back board to accommodate up to 128 subscribers of the ISDN basic speed subscriber.

2 is a detailed configuration diagram of the ISDN matching circuit 2, in which 11 is a CPU, 12 is a memory unit, 13 is a DP bus, 14 is a common memory, 15 is a TD bus, and 16 is an LC bus matching unit. And 17 denote RS-232C matching units, respectively.

Central processing unit (CPU) 11 used a Motorola 32-bit microprocessor to perform D-channel link access processing (LAPD) for layer 2 protocol processing.

The memory unit 12 used ROM 128 Kbytes and RAM 256 Kbytes.

The DP-bus matching unit 13 communicates with the FMXP for transmitting and receiving packet data among the D channel data.

The TD-bus matching unit 15 separates the signal data and the packet data of the D-channel data, and transmits and receives the signal data to the ISAP through the TD-bus.

The common memory (CM) 14 is for transmitting and receiving various data including signal data with the ISAP 5 via the TD-bus.

RS-232C matching unit 17 provides one port for monitoring programs and quick program de-bugging early in development, enabling the testing of IDPA and buffers in subscriber matching boards using CRT monitors, and LC-bus matching The unit 16 uses a common memory in the primary group speed subscriber matching circuit 1. It separates D channel among (30B + D) / (23B + D) channels from user side and transmits it to IDPA, and transmits D channel received from IDPA to the user.

3 is a detailed block diagram of the subscriber matching circuit 1 according to an embodiment of the present invention, in which 21 is a U-interface part, 211 is an overvoltage protection device, 212 is a test access part, 213 is a U-transceiver, and 22 is an ISDN. Switched power controller (hereinafter referred to as IEPC), 23 is an extended PCM matching controller (hereinafter referred to as EPIC), 24 is an ISDN D-channel switching controller (hereinafter referred to as IDEC), 25 is a memory map decoder, 26 is an interrupt handler , 27 is the CPU, 28 is the time switch connection matching section (hereinafter referred to as TSL), 29 is the memory section, 30 is the common memory (CM), 31 is the LC bus matching section, 32 is the MMC port, 33 is the address and data Control bus 34 denotes a general-purpose circuit matching bus (GCI bus).

The U-transceiver 213 in the U-interface unit 21 is a TP 3410 IC chip manufactured by National Semiconductor, and is designed to have a bus structure of a general circuit interface (GCI) mode among various modes. Put D data on the assigned GCI channel. The D channel is transmitted to the IDEC 24 and the B channel is transmitted to the EPIC 22. In addition, the U-transceiver 213 includes many registers therein, and the CPU 27 can control the GCI bus 34 through the EPIC 23 in order to control these registers.

Each subscriber has a time slot of 256 Kbps designated for each line, and transmits an activation request status from the subscriber to the EPIC 22 using the C / I channel, and the EPIC 22 requests an interrupt to the interrupt handler 26. The CPU is able to monitor the subscriber's C / I channel, and the subscriber's activation / deactivation request and various loop back request signals from the CPU 27 are switched to the C / T channel. The subscriber's registration status and availability can be determined. The procedure for activation and deactivation is in accordance with CCTTT I.430 and is designed to accommodate 8 circuits of 2BIQ on the matching circuit board.

The EPIC 23 uses Siemens PEB 2055. In the EPIC 23, the 2B channel coming from the subscriber side is allocated to a 32 channel time slot and then connected to the TSL matching unit 28 for time division switching. The 2.048 Mbps data is switched to B1 and B2 of the GCI bus 34.

IDEC 24 is implemented using Siemens PEB 2075, can process the D-channel data, and the two implemented in the present invention, subscribers 0-3 is the first IDEC, 4-7 subscribers The second IDEC processes the D channel data. The four D channel controllers are designed in a single connection mode that is multiplexed and connected to one GCI bus 34, have a demultiplexer bus structure, and are designed to process both signal and packet data as D channels.

The CPU 27 uses Z-Logi's 8-bit Z-180 processor, and performs matching circuit initialization, D-channel transmission and reception, and maintenance functions. Also, I / O port is used to control LED, IEPC, Matched circuit board selection reads and board mounting positions for time slot designation are available. In addition, it separates the D channel from the 2B + D channel coming from the user side and transmits it to the IDPA (2) matching circuit, and transmits the D channel received from the IDPA (2) to the corresponding subscriber. It is configured to perform power supply and matching circuit reset.

The common memory 30 and the LC-bus matching unit 31 are each implemented with two 2Kbyte dual port RAMs and a gate array logic (GAL). It always has a high priority, and if the IDPA 2 is being accessed, the internal bus is put on standby by the BUSY signal and is implemented to allow access later.

The memory map decoder 25 circuit is implemented by GAL, and performs functions such as initialization, control, and separation of 2B + D channels for each circuit in order to perform matching circuit control functions, and to access each circuit. Decoder circuits were used to classify the circuit addresses, respectively.

IEPC (22) is implemented by Siemens PEB 2055, when the power supply of the subscriber is short-circuited to supply power from the matching circuit to receive a simple service.

The memory unit 29 is composed of a ROM and a RAM to provide a 32 Kbyte area, respectively, and implemented to process the functions of Layer 1 by firmware (F / W).

The TSL matching unit 28 is designed to transmit and receive data at the TTL level by implementing the RS-422 driver / receiver.

The interrupt handler 26 is implemented with an AM 9519 IC, which supports seven levels of interrupt priority. When an interrupt occurs, it enters the service according to the priority and releases it by receiving an ACK signal from the CPU 27. It is designed to be.

The test access unit 212 of the U-interface unit 21 is implemented as a relay that can cut the line to the subscriber line side or the exchange side, and the overvoltage protection circuit 211 suppresses the overvoltage flowing from the subscriber line side and the other. The CCTTT K.20 is satisfied to protect the subscriber matching circuit.

The MMC port 23 constitutes an RS-232C interface to perform a test and maintenance function using a CRT.

4 is a detailed configuration diagram according to a second embodiment of the subscriber matching circuit 1, in which 41 is a U-interface part, 411 is an overvoltage protection device, 412 is a test access part, 413 is a U-transceiver, and 42 is an ISDN. Switched power controller (hereinafter referred to as IEPC), 43 is an extended PCM matching controller (hereinafter referred to as EPIC), 44 is an ISDN D channel switching controller (hereinafter referred to as IDEC), 45 is a memory map decoder, 46 is a CPU, 47 Is MMC port, 48 is time switch connection matching section (hereinafter referred to as TSL), 49 is memory section, 50 is common memory (CM), 51 is LC bus matching section, 52 is clock compensator, 53 is address, data And control buses respectively.

The U-transceiver 413 in the U-interface unit 41 is composed of Siemens PEB 2091 IC chip, and is designed to have a bus structure of IOM-2 (ISDN Oriented Modide 2) mode among various modes. It has a data rate of 2048Mbps and is assigned 256Kbps per line per line. The procedures for activation and deactivation are in accordance with CCTTT 1, 430 and are intended to accommodate 8 2B1Q subscribers within the matching circuit board.

The EPIC 43 uses Siemens PEB 2055. In the EPIC 43, the 2B channel coming from the subscriber side is allocated to a 32 channel time slot and then connected to the TSL matching unit 48 for time division switching. The 2.048Mbps data is switched to B1 and B2 on the IOM 2 bus. In addition, the CPU 46 allows the CPU 46 to monitor the activation request status from the subscriber using the C / T channel, and the activation / deactivation request and various loop back request signals of the subscriber requested from the CPU 46 are transmitted through the C / I channel. In this case, the subscriber's synchronization status and availability can be determined using the monitor channel.

IDEC 44 is implemented using Siemens PEB 2075, and the four channel controllers are designed in a single connection mode where multiple channels are connected to one IOM-2 bus. In the present invention, two are implemented, and subscribers 0-3 have the first IDEC and subscribers 4-7 have the demultiplexed bus structure by processing the D channel data, and both the signal and packet data have both. It is designed to process with D channel.

The CPU 46 uses the Z-180 processor, 8-bit Zylog Corporation, and performs the initialization of the matching circuit, D channel transmission and reception, and maintenance, and also uses the I / O port for LED control, IEPC control, and matching circuit. The board selection lead and board mounting position for the type slot designation can be made. Also, it separates D channel among 2B + D channels coming from the user side and transmits it to IDPA (2) matching circuit, and transmits D channel received from IDPA to the corresponding subscriber. And matching circuit reset and the like. Then, interrupt processing is performed in order of EPIC 43 and IDEC 44 using an internal interrupt handler.

The common memory 50 and the LC-bus matching unit 51 are each implemented with two 2Kbyte dual port RAMs and a gate array logic (GAL). IDPA, which is the upper of the two ports, is always high priority. If the IDPA is being accessed and the IDPA is being accessed, the internal bus is put on standby by the BUSY signal and is subsequently accessible.

The memory map decoder 44 circuit is implemented as a GAL, and each circuit can be accessed to perform functions such as initialization, control of each circuit, and separation of 2B + D channels to perform matching circuit control functions. The decoder circuits were used to classify the circuit addresses, respectively.

The IEPC 42 is implemented with Siemens PEB 2025, and when the power supply of the subscriber is short-circuited, the matching circuit is supplied with power to allow the service to be restored.

The memory unit 49 is composed of a ROM and a RAM to provide a 32 Kbyte area, respectively, and is implemented to process the functions of Layer 1 by firmware (F / W).

The TSL matching unit 48 is designed to transmit and receive data at the TTL level by implementing the RS-422 driver / receiver.

The clock compensating circuit 52 is composed of 74LS163 and 74LS624 and supplies 15.36MHz to the PEB 209 IC as a stable clock with reference to 4.096MHz supplied from the TSL block.

The MMC port 47 configures an RS-232C interface to perform a test and maintenance function using a CRT.

5 is a detailed configuration diagram according to a third embodiment of the subscriber matching circuit 1, in which 61 is a U-interface part, 611 is an overvoltage protection device, 612 is a test access part, 613 is a U-transceiver, and 614 is a power supply Circuit part, 62 is bus change circuit part, 63 is PCM matching controller (EPIC), 64 is ISDN D channel switching controller (IDEC), 65 is memory map decoder, 66 is interrupt handler, 67 is CPU, 68 is time switch connection matching Part (TSL), 69 is memory part, 70 is common memory (CM), 71 is LC bus matching part, 72 is MMC port, 73 is address, data, control bus, 74 is ISDN module matching bus (IOM bus) Denotes an internal chip digital connection bus (hereinafter referred to as IDL bus).

The U-transceiver 613 in the U-interface section 61 is a well-known general purpose IC chip (MC145472 IC of MOTOROLA Co., Ltd.), and the IDL bus 75 for 2B + D transmission and reception is transferred from the bus conversion circuit section 62. Converted to IDN (ISDN Onented Modular Interface) to transmit / receive to EPIC (63) and IDEC (64), and SCP (Serial Conned Port) for controlling U-transceiver 613 is in parallel with bus conversion circuit part 62. Implemented to interface with the processor by converting. This device accepts 20.48MHz output and has a built-in circuit that compensates for the clock and timing on the exchange side.The procedure for activation and deactivation is in accordance with CCTTT I.430. Eight circuits are mounted on the matching circuit board. It is designed to be.

The bus conversion circuit 62 converts the IDL bus 75 signal and the IOM bus 74 signal to each other, and implements the interface between the U-transceiver 613, the EPIC 63, and the IDEC 64, and the U-transceiver. (613) SCP for control is designed as a serial-to-parallel conversion circuit that can interface with a processor.

The EPIC 63 used Siemens PEB 2055. In the EPIC 63, a 2B channel coming from a subscriber side is allocated to a time slot, and then connected to a TSL matching unit 68 for time division switching. The Mbps data switches to B1 and B2 of the IOM bus 74. In addition, the CPU 67 can monitor the activation request status from the subscriber by using the C / I channel, and the activation / deactivation request and the various loopback request signals of the subscriber requested from the CPU 67 are C. It is switched to / I channel, and it is possible to determine the synchronization status and availability of the subscriber by using the monitor channel.

IDEC (64) is implemented using Siemens PEC 2075, can process D-channel data, and is implemented in the present invention, two are implemented, subscribers 0-3 is the first IDEC, 4-7 subscribers The second IDEC processes the D channel data. The four D-channel controllers are designed in a single connection mode that is multiplexed and connected to one iom bus 74, have a demultiplexer bus structure, and are designed to process both signal and packet data as D channels.

CPU 67 uses Z-log's 8-bit Z-80180 processor, and performs matching circuit initialization, D-channel transmission and reception, and maintenance functions. 614) Controls, matching circuit board selection reads, and board mounting positions for type slot designation are available. Also, it separates D channel among 2B + D channels coming from user side and transmits it to IDPA matching circuit, and transmits D channel received from IDPA to the corresponding subscriber, input / output test request from upper level, power supply and matching circuit Configured to perform a reset or the like.

The common memory 70 and the LC-bus matching unit 71 are each implemented with two 2 Kbyte dual port RAMs and a gate array logic (GAL), and IDPA, which is the upper of the two ports, always has high priority. If the IDPA is being accessed and the IDPA is being accessed, the internal bus is put on standby by the BUSY signal and is subsequently accessible.

The memory map decoder 65 circuit is implemented by GAL, and performs initialization, control, and separation of 2B + D channels of each circuit to perform matching circuit restraint, and to access each circuit. Decoder circuits were used to classify the circuit addresses, respectively.

The power feeding circuit 714 is designed as a hybrid IC, and when an abnormality occurs in the commercial power source on the subscriber side, the emergency power can be supplied, and the feeding current is programmable by an external resistor.

The memory unit 69 is composed of a ROM and a RAM to provide a 32 Kbyte area, respectively, and is implemented to process the functions of Layer 1 by firmware (F / W).

The TSL matching unit 68 is designed to transmit and receive data at the TTL level by implementing the RS-322 driver / receiver.

The interrupt handler 66 is implemented with an AM 9519 IC, which supports seven levels of interrupt priority, and when an interrupt occurs, the CPU 67 sends an ACK signal, at which time data coming from the interrupt handler 66 is received. According to the interrupt service.

The test access unit 612 of the U-interface unit 61 is implemented as a relay capable of cutting the line to the subscriber line side or the exchange side, and the overvoltage protection circuit 611 suppresses the overvoltage flowing from the subscriber line side and the other. The CCTTT K.20 is satisfied to protect the subscriber matching circuit.

The MMC port 72 configures an RS-232C interface to perform a test and maintenance function using a CRT.

6 is a detailed configuration diagram of the present invention, in which 81 is an U-interface part, 811 is an overvoltage protection device, 812 is an ISDN echo cancellation circuit (hereinafter referred to as IEC-T), and 82 is an ISDN switched power controller (IEPC). ) 83 is an extended PCM matching controller (EPIC), 84 is an ISDN D-channel switching controller (hereinafter referred to as IDEC), 85 is a memory map decoder, 86 is a CPU, 87 is an interrupt handler, 88 is a time switch connection matching unit ( TSL), 89 denotes a memory unit, 90 denotes a common memory (CM), 91 denotes an LC bus matching unit, 92 denotes a clock compensating unit, and 93 denotes an address, data and control bus.

The IEC-T 812 in the U-interface unit 81 is composed of Siemens PEB 20901 and 20902 IC chips, and the IOM is used to exchange digital information through the network termination circuit (NT1) and the subscriber line during the ISDN exchange. Designed in -1 mode, it has a 256Kbps TS (Time Slot) designated for each subscriber's line, and the procedure for activation and deactivation follows CCTTT 1,430. In the present invention, eight circuits are designed to be mounted.

EPIC 82 used Siemens PEB 2055, the 2B channel of the IEC-T input data is processed by the EPIC 83, D-channel data provides a path for the IDEC (84) to process. In addition, the CPU 86 enables the CPU 86 to monitor the activation request status from the subscriber by using the C / I channel, and the activation / deactivation request and various loopback request signals of the subscriber requested from the CPU are switched to the C / I channel. In addition, the monitor channel can be used to determine the subscriber's synchronization status and availability.

IDEC 84 is implemented using Siemens PEB 2075, can process the D-channel data input to the IEC-T (212), and set the two in the present invention, 0-3 subscribers 0 IDEC of 4, Subscriber 4-7, 1 IDEC processes D-channel data, 4 D-channel controllers are designed in a single access mode that is multiplexed and connected to one IOM-1 bus. The signal and packet data are all designed to be processed by D channel.

The interrupt handler 87 is implemented with AM 9519. This device supports 7 levels of interrupt priority. When an interrupt occurs, the device enters the service according to the priority and is designed to be released by receiving an ACK signal from the CPU. have.

The CPU 86 uses Z-180, 8-bit Zylolog, performs initialization of matching circuit, D-channel transmission / reception and maintenance, and also uses LED input / output port to control LED, IEPC 82, Matching circuit mode selection lead and board mounting position for time slot designation can be done. It controls the data coming from the subscriber side and the signal from layer 2, and it is configured to perform input / output test request, power supply and matching circuit reset from upper level.

The common memory 90 and the LC-bus matching unit 91 implement two 2Kbyte dual port RAMs and a gate array logic (GAL) to store messages for layer 1, respectively. In this case, the IDPA, which is a higher level of the two ports, always has a high priority and provides access to the common memory 90.

The memory map decoder 84 is implemented by 74LS138, and the decoder can access each circuit to perform functions such as initialization, control of each circuit, and separation of 2B + D channels to perform matching circuit control functions. The circuits were used to classify the addresses of each circuit.

The IEPC 82 is implemented with Siemens PEB 2025, and when the subscriber's power supply is shorted, the IEPC 82 is supplied with power from the matching circuit so as to receive a simple service.

The memory unit 89 is composed of a ROM and a RAM to provide a 32 Kbyte area, respectively, and is implemented to process the functions of Layer 1 by firmware (F / W).

The TSL matching unit 88 is designed to transmit and receive data at the TTL level by implementing the RS-422 driver / receiver.

The clock compensation circuit 92 is composed of NE 564, 74LS93, and 74LS393, and supplies 15.360MHz to the IEC-T 812 as a stable clock with reference to 4.096MHz supplied from the TSL block.

In addition, an MMC port was provided in the CPU 86 to configure an RS-232C interface and to perform a test and maintenance function using a CRT.

Accordingly, the present invention configured and operated as described above is composed of a subscriber matching board performing a layer 1 function and an IDPA performing a LAPD function, and has a high degree of integration, and an effect of easily matching with a functional block of an existing electronic switchboard. have.

Claims (6)

In the ISDN basic speed subscriber matching device, a basic speed digital subscriber (2B) connected to a subscriber line matching device (8), a time switch matching circuit (3), and a test device matching circuit (7) using a 2B1Q line code and a 4B3T line code. + D) is matched to the electronic switching system, and the 2B + D signal is separated into the B channel and the D channel, and the B channel is the time switch matching circuit through a 2.048 MHz bidirectional subhighway cable in units of two subscriber matching boards. (3), receives the 8Khz FS signal and 4.096MHz clock signal from the time switch matching circuit (3) required for the subscriber matching board, and transmits / receives data for D channel and subscriber matching board control. An ISDN basic speed subscriber matching circuit means 1 which provides a path for testing the subscriber line side and the exchange side through the test apparatus matching circuit 7, and the ISDN basic speed subscriber matching circuit means 1; Connected to a frame multiplexing processor (FMXP) matching circuit 4 and an alarm device matching circuit 6 to process the D channel received by the ISDN subscriber matching circuit means 1 for signaling information for circuit switching, Various failure information, status information, and control information for various maintenance of the subscriber matching device are exchanged with the ISAP matching circuit 5 through the TD-bus, and the packet message information among the received D channel information After the D-channel link access processing (LAPD) is separated and transmitted to the FMXP matching circuit 4 in subunit units, the packet message information transmitted from the FMXP matching circuit 4 output is multiplexed into one D channel. ISDN basic speed subscriber matching device comprising an ISDN D-channel processing board (IDPA) matching circuit means (2). The overvoltage protection device 211 according to claim 1, wherein the ISDN basic speed subscriber matching circuit means 1 includes an overvoltage protection device 211 and an overvoltage protection device 211 which are connected to a subscriber line to suppress an overvoltage flowing from the subscriber line. A plurality of U- having a test access unit 213 connected to the output and connected to the test device 7 to transfer the track, and a U-transceiver 213 connected to the output of the test access unit 212. Connected to the interface means 21 and one side of the subscriber line via the overvoltage protection element in the U-interface means 21, when the power supply of the subscriber is short-circuited, the matching circuit can be supplied with power to receive the service of reduced service. An ISDN switched power controller (IEPC) 22 and a UCI transceiver 213 in the U-interface means 21 as a general-purpose circuit matching bus (GCI) to time-divisionally switch channels input from the subscriber side. An extended PCM matching control means (EPIC) 23 for outputting, a TSL matching means 28 connected to the extended PCM matching control means 23 for adjusting a data transmission / reception level to a TTL level, and the U-transceiver 213 And an address, data and control bus 33 connected to the extended PCM matching control means 23 (EPIC) and the ISDN switched power controller (IEPC) 22, and connected to the address, data and control bus 33. ISDN D-channel switching control means 24 (IDEC) for processing channel data, a memory unit 29 connected to the address, data and control bus 33 to process the functions of layer 1, and the address, data, A memory map decoding means 25 connected to the control bus 33 to classify the addresses of the respective functional circuits, a common memory 30 connected to the address, data, and control bus 33 and controlling bus access; LC bus matching means 31 connected via the address, data and control bus CPU 27, which is in charge of the central control function, is connected via the address, data, and control bus to interrupt processing means 26 for managing the priority of interrupts, and is connected via the address, address and control bus. ISDN basic speed subscriber matching device comprising a M-232 port for performing a test and maintenance function by configuring a -232C matching unit. The overvoltage protection device 411 and the overvoltage device 411 of claim 1, wherein the ISDN basic speed subscriber matching circuit means 1 has an input connected to the subscriber line to suppress an overvoltage flowing from the subscriber line. A plurality of U- having inside the test access unit 413 connected to the output and connected to the test device 7 to transfer the track, and the U-transceiver 413 connected to the output of the test access unit 412. Connected to one side of the subscriber line via the interface means 41 and the overvoltage protection element 412 in the U-interface means 41, when the power supply of the subscriber is short-circuited, the service is restored by supplying power from the matching circuit. ISDN switch power supply controller (IEPC) 42 for receiving a signal and connected to the U-transceiver 413 in the U-interface means 41 by an IOM-2 bus to time-divisionally switch the channel input from the subscriber side doing Long PCM matching control means 43 (EPIC), TSL matching means 48 connected to the extended PCM matching control means 43 to adjust the data transmission and reception level to the TTL level, and input to the TSL matching means 48. Is connected and an output is connected to the U-transceiver 413 in the U-interface means 41, so that 15.360 MHz is set as a stable clock with reference to 4.096 MHz supplied from the TSL matching means 48. Address, data, and control connected to the clock compensating means 42 for supplying to the 413, the U-transceiver 413, the extended PCM matching control means 43 (EPIC), and the ISDN switched power controller (IEPC) 42; ISDN D-channel switching control means 44 (IDEC) connected to the bus 53, the address, data and control bus 53 to process D-channel data, and to the address, data and control bus 53. Memory 49 for processing the functions of layer 1, and the address, data, and control bus 53 Memory map decoding means 45 for classifying the addresses of the respective functional circuit portions, the common memory 50 and the LC bus matching means 51 which are connected via the address, data and control bus 53 and control bus access; And a CPU 47 connected through the address, data, and control bus 53 to perform a central control function, and an RS-232C interface connected to the CPU 47 to test and maintain using a CRT. ISDN basic speed subscriber matching device having an MMC port 47 for performing a function. The overvoltage protection device 611 and the overvoltage device 611 of claim 1, wherein the ISDN basic speed subscriber matching circuit means 1 is connected to a subscriber line to suppress an overvoltage flowing from the subscriber line. A test access unit 613 connected to the output and connected to the test apparatus 7 to transfer the line, a U-transceiver 613 connected to the output of the test access unit 612, and the test access unit 612 A plurality of U-interface means 61 and a U-transceiver 613 in the U-interface means 61 having a power supply circuit 614 therein, which is connected to one end of the output and supplies emergency power to the subscriber. A bus converting means 62 connected to the ISDN module matching bus 74 (IOM bus) and an internal chip digital connection bus 75 (IDL bus) signal, and the IOM bus to the bus converting means 62; Connected via 74 and input from subscribers An extended PCM matching control means (EPIC) 63 for time division switching and outputting the TSL matching means 68 connected to the extended PCM matching control means 63 to adjust a data transmission / reception level to a TTL level; ISDN D channel switching control means 64 (IDEC) connected to the circuit means 62 via the IOM bus 74 to process D channel data, the extended PCM matching control means 63 (EPIC) and the ISDN D; A memory unit 69 connected to the channel switching control means 64 (IDEC) and the bus converting means 62 via an address, data, and control bus 73 to process the functions of layer 1, and the address, data, and control; A memory map decoding means 75 connected via a bus 73 to classify an address of each functional circuit unit, a common memory 70 connected through the address, data, and control bus 73 and controlling bus access; LC bus matching means 71 and the address, data and control bus 73 CPU 67, which is connected via the central control function and the address, data, and control bus 73 are connected to each other, and interrupt processing means 66 for managing the priority of the interrupt. ISDN basic speed subscriber matching device, characterized in that it has an MMC port 72 connected via a bus (73) to configure the RS-232C matching unit to perform the test and maintenance functions. The overvoltage protection device 811 and the overvoltage device 811 of claim 1, wherein the ISDN basic speed subscriber matching circuit means 1 has an input connected to the subscriber line to suppress an overvoltage flowing from the subscriber line. A plurality of U-interface means 81 connected to the output and having an echo cancellation circuit section (IEC-T) 212 which sets a mode for exchanging digital information via the network termination circuit NT1 and the subscriber line in the ISDN exchange period. And, connected to one side of the subscriber line via the overvoltage protection element 812 in the U-interface means 81 to supply the power from the matching circuit when the power supply of the subscriber is short-circuited to receive the service of a simple Connected to an ISDN switched power controller (IEPC) 82 and an echo cancellation circuit section (IEC-T) in the U-interface means 81 by an IOM-1 bus to time-divisionally switch channels input from the subscriber side. An extended PCM matching control means (EPIC) 83 to be output, a TSL matching means 88 connected to the extended PCM matching control means 83 to adjust a data transmission / reception level to a TTL level, and the TSL matching means 88 15.360 MHz as a stable clock with reference to 4.096 MHz supplied from the TSL matching means 88 connected to an input thereof and to an output of an echo cancellation circuit portion (IEC-T) 812 in the U-interface means 81. Clock compensation means 92 for supplying the signal to the U-transceiver 813, the echo cancellation circuit unit (IEC-T) 812, the extended PCM matching control means 83 (EPIC), and the ISDN switched power controller (IEPC). 82, an address, data and control bus 93 connected to the ISDN, and an ISDN D-channel switching control means 84 (IDEC) connected to the address, data and control bus 93 to process D-channel data; A memory unit 89 connected to the data, control bus 93 to process the functions of layer 1, A memory map decoding means 85 connected to the address, data and control bus 93 to classify the addresses of the respective functional circuits, and a common to connect the bus through the address, data and control bus 93 and control bus access. A memory 87 and an LC bus matching means 91, a CPU 87 connected through the address, data and control bus 93 and serving as a central control function; and the address, data and control bus 93 ISDN basic speed subscriber matching device, characterized in that it is provided via interrupt processing means 87 to support the interrupt priority of 7 channels, and to receive the service according to the priority when an interrupt occurs. The IDPA matching circuit means (2) includes a CPU (11) for performing a D-channel link access processing (LAPD) function for Layer 2 protocol processing and a ROM connected to the CPU (11). (ROM) 128 Kbytes, RAM (RAM) memory unit 12 consisting of 256Kbytes, and the CPU 11 and the frame multiplexing processor (FMXP) matching circuit (4) connected to the packet data transmission and reception of the D-channel data DP-bus matching unit 13 which communicates with FMXP, common memory (CM; 14) for transmitting and receiving various data including signal data with ISAP 5 via TD-bus, and the common memory ( A TD-bus matching unit 15 connected to the CM 14) and the ISAP matching circuit 5 to separate the signal data and the packet data of the D-channel data and transmit and receive the signal data to the ISAP through the TD-bus; Connected to the CPU 11, the primary group speed subscriber matching means 1, and the alarm device matching circuit 6 Using the common memory in the speed subscriber matching means (1), the D channel is separated from the (30B + D) / (23B + D) channels coming from the user side and transmitted to IDPA, and the D channel received from IDPA is transmitted to the user. And an LC-bus matching unit (14) for transmitting to the ISDN basic speed subscriber matching device.