KR940006491U - 디램 모듈 - Google Patents

디램 모듈

Info

Publication number
KR940006491U
KR940006491U KR2019920016030U KR920016030U KR940006491U KR 940006491 U KR940006491 U KR 940006491U KR 2019920016030 U KR2019920016030 U KR 2019920016030U KR 920016030 U KR920016030 U KR 920016030U KR 940006491 U KR940006491 U KR 940006491U
Authority
KR
South Korea
Prior art keywords
dram module
dram
module
Prior art date
Application number
KR2019920016030U
Other languages
English (en)
Other versions
KR950004211Y1 (ko
Inventor
김영선
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR92016030U priority Critical patent/KR950004211Y1/ko
Publication of KR940006491U publication Critical patent/KR940006491U/ko
Application granted granted Critical
Publication of KR950004211Y1 publication Critical patent/KR950004211Y1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
KR92016030U 1992-08-25 1992-08-25 디램 모듈 KR950004211Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92016030U KR950004211Y1 (ko) 1992-08-25 1992-08-25 디램 모듈

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92016030U KR950004211Y1 (ko) 1992-08-25 1992-08-25 디램 모듈

Publications (2)

Publication Number Publication Date
KR940006491U true KR940006491U (ko) 1994-03-25
KR950004211Y1 KR950004211Y1 (ko) 1995-05-22

Family

ID=19339012

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92016030U KR950004211Y1 (ko) 1992-08-25 1992-08-25 디램 모듈

Country Status (1)

Country Link
KR (1) KR950004211Y1 (ko)

Also Published As

Publication number Publication date
KR950004211Y1 (ko) 1995-05-22

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Legal Events

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A201 Request for examination
E701 Decision to grant or registration of patent right
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FPAY Annual fee payment

Payment date: 20050422

Year of fee payment: 11

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