KR940006216A - Dry etching method and dry etching device - Google Patents

Dry etching method and dry etching device Download PDF

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KR940006216A
KR940006216A KR1019930011383A KR930011383A KR940006216A KR 940006216 A KR940006216 A KR 940006216A KR 1019930011383 A KR1019930011383 A KR 1019930011383A KR 930011383 A KR930011383 A KR 930011383A KR 940006216 A KR940006216 A KR 940006216A
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gas
chamber
dry etching
high frequency
semiconductor substrate
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KR1019930011383A
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KR0126249B1 (en
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신이찌 이마이
노리히코 타마키
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모리시타 요이찌
마쯔시다덴기산교 가부시기가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체기판의 일부를 가스를 사용해서 제거하도록 한 드라이에칭법 및 그 장치의 개량에 관한 것으로서, 플라즈마에칭을 이용하면서, 플라즈마중합에 의한 부착막의 형성을 제어할 수 있는 반도체기판의 드라이에칭법, 드라이에칭장치를 제공하는 것을 목적으로 한 것이며, 그 구성에 있어서, 고주파전원(13)에 접속되는 1쌍의 전극(12a), (12b)을 채임버(11)내에 설치하고, 실리콘기판(X1)은, 하부전극(12b)위에 설치되어 있으며, CHF3 가스공급장치(16)로부터 불화탄소가스인 CHF3가수를 공급하고, CIF3가스공급장치(17)로부터 할로겐간화합물 가스인 CIF3 가수를 공급한 후, 고주파전원(13)을 온한다. 이에 의해, 채임버(11)의 내벽을 CIF3가스로부터 발생하는 할로겐래디컬로 덮어서, CHF3가스의 플라즈마중합에 의한 폴리머의 생성을 억제하고, 부착막의 생성을 적당한 정도로 제어한다. 즉, 개구부의 형상을 적절한 형상으로 제어하므로서 치수이동이 작게 된다. 또 채임버(11)의 내벽에 부착하는 폴리머에 의한 먼지도 저감하게 한 것을 특징으로 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method in which a portion of a semiconductor substrate is removed by using a gas, and to an improvement in the apparatus thereof. It is an object of the present invention to provide a dry etching apparatus, and in this configuration, a pair of electrodes 12a and 12b connected to the high frequency power source 13 are provided in the chamber 11, and the silicon substrate is provided. (X1) is provided on the lower electrode 12b, and supplies CHF3 water, which is a fluorocarbon gas, from the CHF3 gas supply device 16, and supplies CIF3 valence, which is an inter-halogen compound gas, from the CIF3 gas supply device 17. After that, the high frequency power supply 13 is turned on. As a result, the inner wall of the chamber 11 is covered with halogen radicals generated from the CIF3 gas, thereby suppressing the production of the polymer by plasma polymerization of the CHF3 gas, and controlling the production of the adhesion film to an appropriate level. That is, the dimension movement becomes small by controlling the shape of the opening portion to an appropriate shape. Moreover, the dust by the polymer adhering to the inner wall of the chamber 11 is also reduced.

Description

드라이에칭법 및 드라이에칭장치Dry etching method and dry etching device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

재1도는 실시예에 있어서의 에칭장치의 구성을 개략적으로 표시한 단면도,1 is a cross-sectional view schematically showing the configuration of the etching apparatus in the embodiment;

제2도는 제1실시예의 방법에 의한 LOCOS의 형성공정에 있어서의 실리콘기판의 상태를 표시한 단면도.2 is a cross-sectional view showing the state of the silicon substrate in the process of forming the LOCOS by the method of the first embodiment.

제3도는 플라즈마중합에 의한 부착막의 형성과 할로겐원자에 의한 기화성물질의 생성기구를 설명하는 도면.3 is a view for explaining the formation mechanism of the adhesion film by plasma polymerization and the generation mechanism of vaporizable material by halogen atom.

Claims (15)

고주파전원에 접속되는 적어도 1쌍의 전극을 채임버내에 배설해서 이루어진 에칭장치내에서, 반도체기판의 일부를 반응성가스와의 반응에 의해 제거하도록 한 드라이에칭법에 있어서, 반도체기판을 채임버내에 설치하고, 상기 채임버내에, 적어도 할로겐간 화합물가스와 불화탄소가스를 도입하고, 다음에 상기 고주파전원으로부터 상기 전극에 고주파전압을 인가하는 것을 특징으로 하는 드라이에칭법.In an etching apparatus formed by disposing at least one pair of electrodes connected to a high frequency power source in a chamber, a semiconductor substrate is provided in the chamber in a dry etching method in which a part of the semiconductor substrate is removed by reaction with a reactive gas. And at least an interhalogen compound gas and a fluorocarbon gas are introduced into the chamber, and then a high frequency voltage is applied to the electrode from the high frequency power supply. 제1항에 있어서, 상기 반도체기판의 피에칭부를, 규소를 함유한 물질로 구성되어 있는 것을 특징으로 하는 드라이 에칭법.The dry etching method according to claim 1, wherein the etching target portion of the semiconductor substrate is made of a material containing silicon. 제1항에 있어서, 상기 반도체기판의 피에칭부는, 절연막인 것을 특징으로 하는 드라이에칭법.The dry etching method according to claim 1, wherein the etching target portion of the semiconductor substrate is an insulating film. 제1항, 제2항 또는 제3항에 있어서, 상기 반도체기판의 피에칭부는 절연막의 일부를 제거해서 절연막 아래 쪽의 도전부표면을 노출시키는 콘택트구멍인 것을 특징으로 하는 드라이에칭법.4. The dry etching method according to claim 1, 2 or 3, wherein the etching target portion of the semiconductor substrate is a contact hole for removing a portion of the insulating film to expose the conductive portion surface under the insulating film. 제3항에 있어서, 상기 반도체기판의 피에칭부는, LOCOS형성을 위한 마스크가 되는 실리콘 질화막인 것을 특징으로 하는 드라이에칭법.4. The dry etching method of claim 3, wherein the etching target portion of the semiconductor substrate is a silicon nitride film serving as a mask for forming LOCOS. 제1항 또는 제5항에 있어서, 상기 피에칭부의 제거가 종료하기 직전에, 할로겐간화합물가스의 공급을 정지하고, 그후, 고주파전원이 인가된 불화탄소가스에 의한 처리를 행하는 것을 특징으로 하는 드라이에칭법.6. The supply of the inter-halogen compound gas is stopped immediately before the removal of the etched portion is completed, and thereafter, the treatment is performed by a fluorocarbon gas to which a high frequency power supply is applied. Dry etching method. 제1항 또는 제5항에 있어서, 상기 피에칭부의 제거가 종료에 가까와지면, 할로겐화합물의 공급량을 저감해 가는 것을 특징으로 하는 드리이에칭법.The dry etching method according to claim 1 or 5, wherein the supply amount of the halogen compound is reduced when the removal of the etched portion is near the end. 제1항 또는 제4항에 있어서, 상기 피에칭부의 제거가 종료한 후, 고주파전압의 인가를 정지하고, 적어도 할로겐간화합물가스를 채임버내에 잔류시키는 것을 특징으로 하는 드라이에칭법.The dry etching method according to claim 1 or 4, wherein after the removal of the etched portion is completed, application of a high frequency voltage is stopped and at least an interhalogen compound gas is left in the chamber. 제1항에 있어서, 상기 할로겐간화합물가스로서 CIF3가스를 사용하는 것을 특징으로 하는 드라이에칭법.The dry etching method as claimed in claim 1, wherein CIF3 gas is used as the halogen-containing compound gas. 제1항 또는 제9항에 있어서, 상기 불화탄소가스로서, CHF3가스 및 CH2F2가스중 적어도 한쪽을 사용하는 것을 특징으로 하는 드라이에칭법.The dry etching method according to claim 1 or 9, wherein at least one of CHF 3 gas and CH 2 F 2 gas is used as the carbon fluoride gas. 제1항, 제9항 또는 제10항에 있어서, 상기 불화탄소가스 및 할로겐간화합물가스에 더하여, 불활성가스를 혼입한 것을 특징으로 하는 드라이에칭법.The dry etching method according to claim 1, 9 or 10, wherein an inert gas is mixed in addition to the carbon fluoride gas and the halogen compound gas. 반도체기판의 일부를 반응성가스와의 반응에 의해 제거하기 위한 드라이에칭장치로서, 반도체기판을 설치하고, 가스에 의한 에칭을 행하기 위한 채임버와, 이 채임버에 반응성가스를 공급하는 가스공급장치와, 상기 채임버내에 배설된 적어도 1쌍의 전극과, 이 전극간에 고주파전압을 인가하기 위한 고주파 전원과, 상기 가스공급장치에 가스배관을 개재해서 접속되고, 채임버의 상부로부터 가스를 분출하기 위한 다수의 가는 구멍을 가진 제1 가스분출구와, 상기 가스공급장치에 가스배관을 개재해서 접속되어, 채임버의 옆부분으로부터 가스를 분출하기 위한 다수의 가는 구멍을 가진 제2가스분출구와, 상기 채임버로부터 가스를 배출하기 위한 배출구를 구비한 것을 특징으로 하는 드라이에칭장치.A dry etching apparatus for removing a part of a semiconductor substrate by reaction with a reactive gas, comprising: a chamber for installing a semiconductor substrate and etching by gas; and a gas supply apparatus for supplying a reactive gas to the chamber. And at least one pair of electrodes disposed in the chamber, a high frequency power source for applying a high frequency voltage between the electrodes, and a gas pipe connected to the gas supply device to blow gas from the upper portion of the chamber. A first gas outlet having a plurality of fine holes for the first gas outlet, a second gas outlet having a plurality of fine holes for ejecting gas from the side of the chamber, connected to the gas supply device via a gas pipe; Dry etching apparatus comprising a discharge port for discharging the gas from the chamber. 제12항에 있어서, 상기 채임버는, 내면이 원통형상으로 형성되어 있고, 상기 제2가스분출구는, 챔버의 옆 부분에 원통형상으로 배치되고, 각 가는 구멍은, 원통면 전체에 걸쳐서 배설되어 있는 것을 특징으로 하는 드라이에칭장치.The said chamber is formed in the cylindrical shape, the said 2nd gas ejection opening is arrange | positioned at the side of a chamber, and each thin hole is excreted over the whole cylindrical surface. Dry etching apparatus characterized in that. 반도체기판의 일부를 가스와의 반응에 의해 제거하기 위한 드라이에칭장치로서, 적어도 내면이 구형상으로 형성되고, 반도체기판을 설치해서 반응성가스에 의한 에칭을 행하기 위한 채임버와, 이 채임버에 반응성가스를 공급하는 가스공급장치와, 상기 채임버내에 배설된 적어도 1쌍의 전극과, 이 전극간에 고주파전압을 인가하기 위한 고주파전원과, 상기 가스공급장치에 가스배관을 개재해서 접속되고. 채임버의 상부로부터 가스를 분출하기 위한 다수의 가는 구멍을 가진 구형상의 가스분출구를 구비한 것을 특징으로 하는 드라이에칭장치.A dry etching apparatus for removing a part of a semiconductor substrate by reaction with a gas, wherein at least an inner surface thereof is formed in a spherical shape, and a chamber for installing a semiconductor substrate for etching with a reactive gas and the chamber. A gas supply device for supplying a reactive gas, at least one pair of electrodes disposed in the chamber, a high frequency power supply for applying a high frequency voltage between the electrodes, and a gas piping to the gas supply device. And a spherical gas ejection opening having a plurality of fine holes for ejecting gas from the top of the chamber. 제12항, 제13 또는 제14항에 있어서, 상기 각 가는 구멍은, 체임버의 내벽을 따라서 서로 등간격으로 배치되어 있는 것을 특징으로 하는 드라이에칭장치.The dry etching apparatus according to claim 12, 13 or 14, wherein the thin holes are arranged at equal intervals along the inner wall of the chamber. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930011383A 1992-06-22 1993-06-22 Dry etching method and apparatus thereof KR0126249B1 (en)

Applications Claiming Priority (2)

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JP92-161551 1992-06-22
JP16155192 1992-06-22

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100331053B1 (en) * 1994-05-17 2002-06-20 가나이 쓰도무 Plasma processing appartus and plasma processing method
KR100433098B1 (en) * 2000-05-30 2004-05-28 샤프 가부시키가이샤 Method of anisotropic plasma etching using non-chlorofluorocarbon, fluorine-based chemistry

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102493574B1 (en) * 2015-10-13 2023-01-31 세메스 주식회사 Apparatus for treating substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100331053B1 (en) * 1994-05-17 2002-06-20 가나이 쓰도무 Plasma processing appartus and plasma processing method
KR100433098B1 (en) * 2000-05-30 2004-05-28 샤프 가부시키가이샤 Method of anisotropic plasma etching using non-chlorofluorocarbon, fluorine-based chemistry

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