KR940005431B1 - Power control circuit for pc - Google Patents
Power control circuit for pc Download PDFInfo
- Publication number
- KR940005431B1 KR940005431B1 KR1019910024824A KR910024824A KR940005431B1 KR 940005431 B1 KR940005431 B1 KR 940005431B1 KR 1019910024824 A KR1019910024824 A KR 1019910024824A KR 910024824 A KR910024824 A KR 910024824A KR 940005431 B1 KR940005431 B1 KR 940005431B1
- Authority
- KR
- South Korea
- Prior art keywords
- power supply
- serial port
- control circuit
- uart
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000010586 diagram Methods 0.000 description 6
- 230000001276 controlling effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 발명에 의한 직렬 포트 전원 제어회로의 블럭도.1 is a block diagram of a serial port power supply control circuit according to the present invention.
제2도는 제1도의 디코더의 세부 회로도.2 is a detailed circuit diagram of the decoder of FIG.
제3도는 제1도의 스위칭부의 세부 회로도.3 is a detailed circuit diagram of the switching unit of FIG.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 디코더 12 : 스위칭부11 decoder 12 switching unit
13 : UART 14 : RS-232C 드라이버13: UART 14: RS-232C Driver
15 : RS-232C 콘넥터 21 : 포트지정부15: RS-232C connector 21: port designator
22 : D플립플롭 R1, R2 : 저항22: D flip-flop R1, R2: resistance
Q1 : npn 트랜지스터 Q2 : p채널 MOSFETQ1: npn transistor Q2: p-channel MOSFET
본 발명은 휴대용 컴퓨터의 직렬 포트 전원 제어회로에 관한 것이다.The present invention relates to a serial port power control circuit of a portable computer.
종래에는 휴대용 컴퓨터에 있어서, 사용하지 않는 직렬포트 회로에 지속적으로 전원을 공급하여 전력 손실이 커지므로써 밧데리의 수명이 단축되는 문제점이 있었다.Conventionally, in portable computers, there is a problem in that the life of the battery is shortened because power loss is increased by continuously supplying power to a serial port circuit which is not used.
상기 문제점을 개선하기 위해 안출된 본 발명은 예약된 어드레스를 지정하여 전원을 제어하므로써 전력손실을 줄여 밧데리의 수명을 연장시키기 위한 직렬 포트 전원 제어회로를 제공함에 그 목적이 있다.An object of the present invention is to provide a serial port power supply control circuit for reducing the power loss to extend the life of the battery by designating a reserved address to control the power supply.
상기 목적을 달성하기 위해 본 발명은 외부와의 통신을 위한 UART를 구비하는 시스템의 직렬포트 전원 제어회로에 있어서, 상기 UART의 입력단에 연결되어 상기 UART로의 전원 공급을 제어하는 스위칭 수단, 및 상기 스위칭 수단에 연결되어 상기 스위칭 수단의 입력을 조절하는 디코더 수단을 포함하여 구성되는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a serial port power control circuit of a system having a UART for communication with an external device, the switching means being connected to an input terminal of the UART to control a power supply to the UART, and the switching A decoder means connected to the means for regulating the input of the switching means.
이하, 첨부한 도면을 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
제1도는 본 발명에 의한 직렬 포트 전원 제어회로의 블럭도로, 10은 전원 제어회로, 11은 디코더, 12는 스위칭부, 13은 UART, 14는 RS-232C 드라이버, 15는 RS-232C 콘넥터를 각각 나타낸다.1 is a block diagram of a serial port power supply control circuit according to the present invention, 10 is a power supply control circuit, 11 is a decoder, 12 is a switching unit, 13 is a UART, 14 is an RS-232C driver, 15 is an RS-232C connector, respectively. Indicates.
본 발명에 의한 전원 제어회로는 제1도에 도시한 바와 같이 외부와의 통신을 위해 직렬포트인 RS-232C 콘넥터(15)에 연결된 UART(Universal Asynchronous Receiver Transmitter)(13)와 RS-232C 드라이버(14)에 스위칭부(12)를 연결하고, 상기 스위칭부(12)에 디코더(11)를 연결하여 구성한다.As shown in FIG. 1, the power control circuit according to the present invention includes a UART (Universal Asynchronous Receiver Transmitter) 13 and an RS-232C driver connected to an RS-232C connector 15 which is a serial port for communication with the outside. The switch 12 is connected to the 14 and the decoder 11 is connected to the switch 12.
상기 디코더(11)는 상기 스위칭부(12)의 입력을 조절하는 기능을 하며, 상기 스위칭부(12)는 직렬포트로 신호가 전송되는 경우에만 전원이 공급되도록 제어하는 기능을 한다.The decoder 11 functions to adjust the input of the switching unit 12, and the switching unit 12 controls to supply power only when a signal is transmitted to the serial port.
제2도는 제1도의 디코더(11)의 세부 회로도로, 21은 포트지정부, 22는 D플립플롭을 각각 나타낸다.2 is a detailed circuit diagram of the decoder 11 of FIG. 1, where 21 is a port designator and 22 is a D flip-flop.
상기 디코더(11)는 제2도에 도시한 바와 같이 포트 지정부(21)와 D플립플롭(22)으로 구성된다.The decoder 11 includes a port designation section 21 and a D flip flop 22 as shown in FIG.
상기 포트지정부(21)는 입출력 어드레스 맵 중에서 직렬 포트로 신호가 전송되는 예약된 임의의 포트를 지정하는 PAL(Programmable Array Logic)로 구성되며 바람직한 실시예로 PAL16L8을 사용한다.The port designator 21 is composed of a programmable array logic (PAL) that designates a reserved port in which a signal is transmitted to a serial port in an input / output address map and uses PAL16L8 as a preferred embodiment.
상기 D플립플롭(22)은 상기 포트지정부(21)의 출력을 클럭 입력으로 하고 상기 직렬포트로 출력되는 신호(SD)를 데이타 입력으로 하고 출력단자(Q)로는 상기 스위칭부(12)를 제어하기 위한 제어신호를 출력한다.The D flip-flop 22 uses the output of the port designator 21 as a clock input, the signal SD output from the serial port as a data input, and the switching unit 12 as an output terminal Q. Outputs a control signal for controlling.
제3도는 제1도의 스위칭부(12)의 세부 회로도로, R1, R2는 저항, Q1은 npn 트랜지스터, Q2는 p채널 MOSFET를 각각 나타낸다.3 is a detailed circuit diagram of the switching unit 12 of FIG. 1, in which R1 and R2 represent resistors, Q1 represents npn transistors, and Q2 represents p-channel MOSFETs, respectively.
상기 스위칭부(12)는 상기 디코더(11)의 출력을 베이스 입력으로 하고 전원(V)에 콜렉터가 연결되고 에미터는 접지된 npn 트랜지스터(Q1)와, 상기 npn 트랜지스터(Q1)의 콜렉터에 베이스가 연결되고 전원(VBB)에 소오스가 연결되고 에미터는 상기 UART(13) 및 RS-232C 드라이버(14)의 입력단에 연결된 p채널 MOSFET(Q2)로 구성된다.The switching unit 12 has an output of the decoder 11 as a base input, a collector is connected to a power supply V, and an emitter is grounded, and a base is connected to the collector of the npn transistor Q1. Connected to a source V BB , and the emitter consists of a p-channel MOSFET Q2 connected to the input of the UART 13 and RS-232C driver 14.
상기 디코더(11)의 출력에 따른 상기 스위칭부(12)의 동작을 설명하면 다음과 같다.The operation of the switching unit 12 according to the output of the decoder 11 will be described below.
상기 디코더(11)의 출력이 논리 '1'이면 상기 npn 트랜지스터(Q1)는 도통하고 상기 p채널 MOSFET(Q2)도 도통하여 출력(VO)은 'VBB'가 되고 상기 출력전압 'VBB'는 상기 UART(13)와 RS-232C 드라이버(14)에 공급된다.When the output of the decoder 11 is a logic '1', the npn transistor Q1 is turned on and the p-channel MOSFET Q2 is turned on so that the output V O becomes' V BB 'and the output voltage' V BB 'Is supplied to the UART 13 and RS-232C driver 14.
상기 디코더(11)의 출력이 논리 '0'이면 상기 npn 트랜지스터(Q1)와 p채널 MOSFET(Q2)가 차단되어 상기 UART(13)와 RS-232C 드라이버(14)로의 전원 공급은 차단된다.When the output of the decoder 11 is logic '0', the npn transistor Q1 and the p-channel MOSFET Q2 are cut off, and the power supply to the UART 13 and the RS-232C driver 14 is cut off.
상기와 같이 구성되어 동작하는 본 발명은 직렬포트 신호가 공급되는 경우에만 전원을 공급하므로써 전원의 지속적인 공급을 억제할 수 있어 밧데리 수명을 연장시킬 수 있는 적용효과가 있으며 데스트 탑 컴퓨터(Desk Top Computer)와 같이 밧데리를 사용하는 컴퓨터에 적용 가능하다.The present invention configured and operated as described above has an application effect that can prolong the life of the battery by supplying power only when the serial port signal is supplied, and extend the battery life. It can be applied to a computer using the battery as shown.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024824A KR940005431B1 (en) | 1991-12-28 | 1991-12-28 | Power control circuit for pc |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910024824A KR940005431B1 (en) | 1991-12-28 | 1991-12-28 | Power control circuit for pc |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930013944A KR930013944A (en) | 1993-07-22 |
| KR940005431B1 true KR940005431B1 (en) | 1994-06-18 |
Family
ID=19326381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910024824A Expired - Fee Related KR940005431B1 (en) | 1991-12-28 | 1991-12-28 | Power control circuit for pc |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940005431B1 (en) |
-
1991
- 1991-12-28 KR KR1019910024824A patent/KR940005431B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR930013944A (en) | 1993-07-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19911228 |
|
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19911228 Comment text: Request for Examination of Application |
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| PG1501 | Laying open of application | ||
| G160 | Decision to publish patent application | ||
| PG1605 | Publication of application before grant of patent |
Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19940527 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19940831 |
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| GRNT | Written decision to grant | ||
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