KR940005088A - Synchronous Signal Separation Circuit - Google Patents

Synchronous Signal Separation Circuit Download PDF

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Publication number
KR940005088A
KR940005088A KR1019920014256A KR920014256A KR940005088A KR 940005088 A KR940005088 A KR 940005088A KR 1019920014256 A KR1019920014256 A KR 1019920014256A KR 920014256 A KR920014256 A KR 920014256A KR 940005088 A KR940005088 A KR 940005088A
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South Korea
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signal
pulse
pulse width
detecting means
output
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KR1019920014256A
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Korean (ko)
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KR0160615B1 (en
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박재찬
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강진구
삼성전자 주식회사
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Priority to KR1019920014256A priority Critical patent/KR0160615B1/en
Publication of KR940005088A publication Critical patent/KR940005088A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

동기신호 분리회로는 고화질의 영상신호를 처리하는 장치에 있어서, 회로를 간소화하고 안정되게 하기 위한 것이다. 이를 위하여 인가되는 복합영상신호의 동기신호를 분리하기 위한 동기신호 분리회로에 있어서; 일정 기준레벨로 클램프한 복합영상신호의 동기신호의 부극성펄스를 검출하기 위한 부극성 펄스 검출수단; 부극성 펄스검출수단에서 검출된 부극성펄스의 폭을 조절하여 복합동기신호를 검출하기 위한 복합동기신호 검출수단; 복합동기신호 검출수단의 출력신호의 펄스폭을 조절하고복합동기신호 검출수단의 출력신호와 펄스폭이 조절된 신호의 소정의 논리연산에 의하여 수평동기신호를 검출하기 위한 수평동기 신호 검출수단의 출력신호와 수정의 논리연산에 의하여 수직동기신호르 검출하기 위한 수직동기신호 검출수단을 포함하도록 구성된다.The synchronization signal separation circuit is intended to simplify and stabilize the circuit in an apparatus for processing a high quality video signal. A synchronization signal separation circuit for separating a synchronization signal of a composite video signal applied for this purpose; Negative pulse detection means for detecting a negative pulse of the synchronization signal of the composite video signal clamped to a predetermined reference level; Compound synchronous signal detecting means for detecting a compound synchronous signal by adjusting the width of the negative pulse detected by the negative pulse detecting means; Output of horizontal synchronous signal detecting means for adjusting the pulse width of the output signal of the composite synchronous signal detecting means and detecting the horizontal synchronous signal by a predetermined logical operation of the output signal of the composite synchronous signal detecting means and the signal whose pulse width is adjusted. And vertical synchronizing signal detecting means for detecting the vertical synchronizing signal by logical operation of the signal and correction.

Description

동기신호 분리회로Synchronous Signal Separation Circuit

제2도는 3치동기신호에 대한 제1도의 출력파형도,2 is an output waveform diagram of FIG. 1 for a tri-level synchronous signal,

제3도는 3치동기신호의 수직블랭킹기간내의 등화펄스에 대한 파형도,3 is a waveform diagram of an equalization pulse within a vertical blanking period of a tri-level synchronous signal;

제4도는 본 발명에 따른 동기신호 분리회로도,4 is a synchronization signal separation circuit diagram according to the present invention;

제5도는 제4도에 도시된 회로도의 출력파형도,5 is an output waveform diagram of the circuit diagram shown in FIG.

Claims (4)

복합영상신호의 동기신호를 분리하기 위한 동기신호 분리회로에 있어서, 일정 기준레벨로 클램프한 상기 복합영상신호의 상기 동기신호의 부극성펄스를 검출하기 위한 부극성 펄스 검출수단(6); 상기 부극성 펄스 검출단(6)에서 검출된 부극성펄스의 폭을 조절하여 복합동기신호를 검출하기 위한 복합기동신호 검출수단(7); 상기 복합동기신호 검출수단(7)의 출력신호의 펄스폭을 조절하고 상기 복합동기신호 검출수단(7)의 출력신호와 상기 펄스폭이 조절된 신호의 소정의 논리연산에 의하여 수평동기신호를 검출하기 위한 수평동기신호 검출수단(8); 상기 수평동기신호 검출수단(8)의 출력신호의 펄스폭을 조절하여 상기 복합동기신호 검출수단(7)의 출력신호와 소정의 논리연산에 의하여 수직동기신호를 검출하기 위한 수직동기신호 검출수단(9)을 포함하는 것을 특징으로 하는 동기신호분리회로.A synchronization signal separation circuit for separating a synchronization signal of a composite video signal, comprising: negative pulse detection means (6) for detecting a negative pulse of said synchronization signal of said composite video signal clamped to a predetermined reference level; Compound starting signal detecting means (7) for detecting a compound synchronizing signal by adjusting the width of the negative pulse detected by said negative pulse detecting stage (6); The pulse width of the output signal of the compound synchronous signal detecting means 7 is adjusted, and the horizontal synchronous signal is detected by a predetermined logical operation of the output signal of the compound synchronous signal detecting means 7 and the signal whose pulse width is adjusted. Horizontal synchronous signal detecting means (8) for carrying out; Vertical synchronous signal detecting means for detecting the vertical synchronous signal by a predetermined logic operation with the output signal of the composite synchronous signal detecting means 7 by adjusting the pulse width of the output signal of the horizontal synchronous signal detecting means 8 ( 9) a synchronization signal separation circuit comprising: a. 제1항에 있어서, 부극성펄스 검출수단(6)은 상기 동기신호의 페디스탈레벨과 임계레벨중 어느 하나를 기준레벨로 하여 상기 동기신호와 비교하여 상기 부극성펄스를 검출하기 위한 비교기(COM3), 상기 기준레벨을 상기 페디스레벨과 임계레벨중 어느 하나를 선택적으로 스위칭하기 위한 제어용 스위치(SW1), 상기 비교기(COM3)의 출력신호에 의하여 상기 제어용 스위치(SW1) 스위칭을 제어하기 위한 논리소자(AND2),와 상기 비교기(CON3)의 기준레벨이 상기 페디스탈레벨로 설정된 후 다음 상기 임계레벨이 검출되기 전에 상기 기준레벨이 바뀌도록 상기 논리소자(AND2)의 입력레벨의 펄스폭을 조절하기 위한 펄스폭 조절수단(MM1)으로 이루어짐을 특징으로 하는 동기신호분리회로.2. The comparator according to claim 1, wherein the negative pulse detecting means (6) is configured to detect the negative pulse by comparing any one of the pedestal level and the threshold level of the synchronization signal with the reference signal. ), Logic for controlling switching of the control switch SW1 by an output signal of the comparator COM3 and a control switch SW1 for selectively switching either the reference level or any one of the pediment level and the threshold level. After the reference level of the device AND2 and the comparator CON3 are set to the pedestal level, the pulse width of the input level of the logic device AND2 is adjusted so that the reference level is changed before the next threshold level is detected. Synchronization signal separation circuit, characterized in that consisting of a pulse width adjusting means (MM1) for. 제1항에 있어서, 상기 복합동기신호 검출수단(7)은 상기 부극성 펄스 검출수단(6)에서 출력된 신호에서 수평동기펄스에 해당되는 부극성 펄스구간만을 검출할 수 있도록 상기 부극성 펄스 검출수단(6)에서 출력되는 펄스폭을 조절하는 제1펄스폭조절기(MM3)와, 상기 부극성 펄스 검출수단(6)에서 출력되는 신호에 의하여 상기 복합동기신호를 출력하기 위하여 상기 제1펄스폭조절기(MM3)에서 출력되는 신호의 펄스폭을 조절하기 위한 제2펄스폭조절기(MM4)로 이루어짐을 특징으로 하는 동기신호 분리회로.2. The negative polarity pulse detection according to claim 1, wherein the complex synchronous signal detecting means (7) detects only the negative pulse section corresponding to the horizontal synchronizing pulse from the signal output from the negative polarity pulse detecting means (6). A first pulse width regulator (MM3) for adjusting the pulse width output from the means (6) and the first pulse width for outputting the composite synchronous signal according to a signal output from the negative pulse detection means (6). And a second pulse width controller (MM4) for adjusting the pulse width of the signal output from the controller (MM3). 제1항에 있어서, 상기 수직동기신호 검출수단(9)은 상기 수평동기신호검출수단에서 출력된 신호를 1수펑동기펄스 주기내에서 소정의 펄스폭으로 조절하기 위한 제1펄스폭조절수단(MM6), 상기 제1펄스폭조절수단(MM6)의 반전출력신호왕 상기 복합도기신호검출수단(7)에서 출력되는 부극성 복합동기신호를 논리합적으로 처리하기 위한 논리소자(OR1)와, 상기 논리소자(OR1)의 출력신호에 의하여 상기 복합영상신호의 수직귀선기간애의 등화펄스중 2번째 등화펄스를 기준으로 수직동기신호가 발생되도록 펄스폭을 조절하기 위한 제2펄스폭조절수단(MM7)으로 이루어짐을 특징으로 하는 동기신호 분리회로.2. The first pulse width adjusting means (MM6) according to claim 1, wherein said vertical synchronizing signal detecting means (9) adjusts a signal output from said horizontal synchronizing signal detecting means to a predetermined pulse width within one multi-synchronous pulse period. And a logic element OR1 for logically processing the negative composite synchronous signal output from the composite ceramic signal detection means 7 by the inverted output signal king of the first pulse width adjusting means MM6, and the logic A second pulse width adjusting means (MM7) for adjusting a pulse width so that a vertical synchronization signal is generated based on a second equalization pulse among the equalization pulses in the vertical retrace period of the composite video signal by the output signal of the element OR1; A synchronization signal separation circuit, characterized in that consisting of.
KR1019920014256A 1992-08-08 1992-08-08 Circuit for separating sync.-signals KR0160615B1 (en)

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Application Number Priority Date Filing Date Title
KR1019920014256A KR0160615B1 (en) 1992-08-08 1992-08-08 Circuit for separating sync.-signals

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Application Number Priority Date Filing Date Title
KR1019920014256A KR0160615B1 (en) 1992-08-08 1992-08-08 Circuit for separating sync.-signals

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KR940005088A true KR940005088A (en) 1994-03-16
KR0160615B1 KR0160615B1 (en) 1999-01-15

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