KR940004777A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940004777A
KR940004777A KR1019920015183A KR920015183A KR940004777A KR 940004777 A KR940004777 A KR 940004777A KR 1019920015183 A KR1019920015183 A KR 1019920015183A KR 920015183 A KR920015183 A KR 920015183A KR 940004777 A KR940004777 A KR 940004777A
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South Korea
Prior art keywords
trenches
semiconductor substrate
trench
forming
manufacturing
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KR1019920015183A
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Korean (ko)
Inventor
이태복
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김광호
삼성전자 주식회사
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Priority to KR1019920015183A priority Critical patent/KR940004777A/en
Publication of KR940004777A publication Critical patent/KR940004777A/en

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Abstract

서로 깊이가 다른 여러개의 트랜치들을 동일한 반도체 기판상에 형성하는 반도체장치의 제조방법에서, 반도체 기판상에 절연층을 형성한 후 트랜치를 형성하고자 하는 부분의 절연층을 트랜치의 깊이에 비례하는 면적만큼 제거하였다. 그다음 상기 절연층을 마스크로하여 반도테 기판을 반응성 이온식각 방법으로 식각한다. 이때 많은 면적이 노출된 반도체 기판은 빨리 제거되고, 적은 면적이 노출된 부분은 천천히 제거되어 서로 깊이가 다른 트랜치들이 형성된다. 또한 가스의 혼합 비율 및 식각각도를 조절하여 트랜치를 U자형으로 형성할 수 있다.In the method of manufacturing a semiconductor device, in which a plurality of trenches having different depths are formed on the same semiconductor substrate, after forming an insulating layer on the semiconductor substrate, an insulating layer of a portion to which the trench is to be formed has an area proportional to the depth of the trench. Removed. Then, the semiconductor substrate is etched by reactive ion etching using the insulating layer as a mask. At this time, the semiconductor substrate exposed to a large area is quickly removed, and the portions exposed to a small area are slowly removed to form trenches having different depths. In addition, the trench may be U-shaped by adjusting the mixing ratio and etching angle of the gas.

따라서 동일한 반도체 기판상에 서로 깊이가 다른 트랜치들을 한번의 식각공정으로 형성하여 반도체장치의 제조공정을 단순화할 수 있다.Therefore, trenches having different depths may be formed on the same semiconductor substrate in one etching process to simplify the manufacturing process of the semiconductor device.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도 (B)∼(D)도는 이 발명에 따른 반도체 장치의 제조공정도이다.3B to 3D are manufacturing process diagrams of the semiconductor device according to the present invention.

Claims (7)

반도체 기판상에 서로 깊이가 다른 적어도 두개의 트랜치를 형성하는 반도체 장치의 제조방법에 있어서, 상기 반도체 기판상에 제1절연막을 형성하는 공정과, 상기 트랜치를 형성하고자 하는 부분들의 제1절연막을 서로 다른 쪽으로 제거하는 공정과, 상기 제1절연막이 제거되어 서로 폭이 다르게 노출된 반도체 기판을 제거하여 서로 깊이가 다른 트랜치들을 형성하는 공정과, 상기 트랜치들의 표면에 제2절연막을 형성하는 공정과, 상기 서로 다른 깊이의 트랜치들이 완전히 메워지도록 상기 구조의 전표면에 단결정 실리콘층을 형성하는 공정과, 상기 트랜치들을 메운 단결정 실리콘층을 제외한 제1절연상막의 단결정 실리콘층을 제거하는 공정을 구비하는 반도체 장치의 제조방법.A method of manufacturing a semiconductor device in which at least two trenches having different depths are formed on a semiconductor substrate, the method comprising: forming a first insulating film on the semiconductor substrate; and forming a first insulating film on portions to be formed in the trench. Removing the other side, removing the semiconductor substrate exposed to different widths by removing the first insulating layer, forming trenches having different depths from each other, forming a second insulating layer on the surfaces of the trenches; Forming a single crystal silicon layer on the entire surface of the structure such that trenches of different depths are completely filled; and removing the single crystal silicon layer of the first insulating layer except for the single crystal silicon layer filling the trenches. Method of manufacturing the device. 제1항에 있어서, 상기 제1절연막을 패드산화막과 질화규소막 및 산화막의 다층으로 형성하고 상기 질화규소막을 다결정 실리콘층의 제거 공정시에 에칭스토퍼로 사용하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is formed of a multilayer of a pad oxide film, a silicon nitride film, and an oxide film, and the silicon nitride film is used as an etching stopper during the removal process of the polycrystalline silicon layer. 제1 내지 제2항에 있어서, 상기 트랜치들의 형성공정시 상기 산화막을 마스크로 하여 트랜치들을 형성하는 반도체 장치의 제조방법.The method of claim 1, wherein the trenches are formed using the oxide layer as a mask during the trench formation process. 제1항에 있어서, 상기 트랜치들의 형성 공정시 상기 제1절연막상에 트랜치를 형성할 부분들이 노출되도록 감광막 패턴을 형성하고 상기 감광막 패턴을 마스크로 하여 트랜치들을 형성하는 반도체 장치의 제조방법.The method of claim 1, wherein a photoresist pattern is formed to expose portions of the trench on the first insulating layer and the trenches are formed using the photoresist pattern as a mask during the formation of the trenches. 제1항에 있어서, 상기 트랜치 형성공정을 반응성 이온식각방법으로 행하는 반도체 장치의 제조방법.The method of claim 1, wherein the trench forming step is performed by a reactive ion etching method. 제1항에 있어서, 상기 트랜치들을 U자형 및 V자형으로 이루어지는 군에서 임의로 선택되는 하나의 형상으로 형성하는 반도체 장치의 제조방법.The method of claim 1, wherein the trenches are formed in one shape arbitrarily selected from a group consisting of a U shape and a V shape. 제1항에 있어서 상기 제1절연막 상의 다결정 실리콘층을 제거하는 공정을 에치백 및 폴리싱으로 이루어지는 군에서 임의 선택되는 하나의 방법으로 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the polycrystalline silicon layer on the first insulating film is any one selected from the group consisting of etch back and polishing. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920015183A 1992-08-24 1992-08-24 Manufacturing Method of Semiconductor Device KR940004777A (en)

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KR1019920015183A KR940004777A (en) 1992-08-24 1992-08-24 Manufacturing Method of Semiconductor Device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414199B1 (en) * 2001-01-05 2004-01-07 주식회사 오랜텍 Method of fabricating a structure of silicon wafer using wet etching
KR100428785B1 (en) * 2001-08-30 2004-04-30 삼성전자주식회사 Semiconductor device having a trench isolation structure and method of fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414199B1 (en) * 2001-01-05 2004-01-07 주식회사 오랜텍 Method of fabricating a structure of silicon wafer using wet etching
KR100428785B1 (en) * 2001-08-30 2004-04-30 삼성전자주식회사 Semiconductor device having a trench isolation structure and method of fabricating the same

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