KR940004261Y1 - Memroy controller - Google Patents

Abstract

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Description

Write-protection device of memory

1 is a conventional memory circuit diagram.

2 is a memory circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1: Setter 2: Comparator

3: decoder 4,5: memory

8: buffer 9: selector

10: multiplexer

The present invention relates to a write-protection device of a storage device for increasing the efficiency of the storage device by subdividing the write-protection area of the storage device into bytes.

1 shows a block diagram of a conventional memory circuit. The conventional memory device has a setter 1 for setting an address value, a comparator 2 for determining whether the address value set in the setter 1 and the address value of the address line are the same, and when the output of the comparator is high. Decoder 3 for chip-selecting memory according to a combination of input values, memory 4 and 5 such as RAM for writing and reading information, and writing or reading of memory 4 and 5 OR gates 6 and 7 for determining. The data bus is connected to the data terminals of each of the memories 4 and 5, and the address bus is connected to the address terminals of each element.

The setter 1 sets the address value by the determination of the internal switch, and the comparator 2 compares the set value with the address value and sends a high signal to the output side when the value is identical to the decoder 3. Let it be. When the decoder 3 is enabled, the decoder 3 outputs the output terminal by combining the values of the input terminals A and B. The memory 4 or 5 is selected by outputting a low signal to only one of the terminals. Read and write signals in the selected memory (4 or 5) (Write or read is performed by means of reading data, but when writing data to memory (4 or 5), one input of each OR gate (6, 7) signal, PROT ₁ or PROT ₂ , must be at the low level. Therefore, when PROT ₁ or PROT ₂ is at the high level, the output of the OR gates 6 and 7 is always at the high level irrespective of the write signal WR. Therefore, writing to the memory becomes impossible.

In such a conventional memory device, since it is necessary to determine whether to write data to the memory device by capacity of one memory device, the remaining area other than the prohibited area cannot be used as a writable area, which reduces the efficiency of the memory device. In order to use it, the write prohibition signal (PROT ₁ , PROT ₂ ) should be changed to high or low every time the memory device is accessed. In addition, in order to subdivide the forbidden region, a memory device having a low integration level must be used, which causes a problem that the degree of integration of the memory device is reduced.

The present invention has been made to solve the above-mentioned problem, and the write prohibition area of the memory is subdivided into byte units to improve the efficiency of the storage device and to improve the degree of integration.

The memory device of the present invention has a setter 1 for determining an access area of the memory device as shown in FIG. 2, and a comparator 2 for comparing the output value set in the setter 1 with an address value on the address bus. ), A decoder 3 for decoding an address value and selecting a device to be accessed, a memory 4 storing data, and bit data storage for judging whether or not to write data to the memory 4 is stored. When the data is written to the memory 4, the memory 5 for outputting a collection of bits for determining whether to write data corresponding to the address to be written to the memory 4 is accessed, and the memory 4 of the address values on the address bus is accessed. Selector 4 for selecting and classifying the address value at the time of access and the address value at the time of accessing the memory 5, and inputting them to the address input terminal of the memory, and the value output from the memory 5; It consists of a multiplexer 10 and a buffer 8 for outputting only one bit corresponding to a byte unit address to write data to the memory 4 to determine whether data write is prohibited. In FIG. 2, the same reference numerals are used for parts similar to those of FIG. 1 or for parts performing similar functions.

In the setter 1, the access area of the storage device, that is, the access address value is set by setting the internal switch. In the comparison (2), it is determined whether or not the storage device is accessible when the value (B ₀ -B ₃ ) set in the setter (1) and the address value (A ₀ -A ₃ ) on the address bus coincide. The decoder 3 generates a high signal to enable the decoder 3. When the decoder 3 is enabled, its output by a combination of both inputs A and B of the decoder 3 One of them goes low level, thereby selecting the device 4 or 5 to be accessed. For example, among the output terminals of the decoder 3 If the output of is low level, the input terminal (A / of the selector 9) ) Value goes low and B ₀ -B ₁₂ input is transmitted to output terminal (y0-y2) of two inputs and is input to address input terminal (A ₀ -A ₁₂ ) of memory (5). Data is written to the memory 5 in synchronization with the write signal WR via the buffer 8. By this principle, data is stored or changed to determine whether data writing is prohibited in units of bytes in the memory 4 at an initial time or at any time.

For example, during the output of the decoder 3 Is low level, the low level is input to the chip select input terminal CS of the memory 4 so that the memory 7 is selected and the value of the address indicated by the value on the address bus is the read signal. In synchronization with the data terminal (D ₀ ~ D ₇₎ of the memory 4 are output to the data bus. Also of the decoder (3) When the output is at the low level, the memories 4 and 5 are simultaneously selected, and the low level is input to the read signal input terminal RD of the memory 5, and the memory 5 is in the read state. At the same time, an address value on the address bus is input to the address terminals A ₀ to A ₁₅ of the memory 4, and a value of the addresses A ₃ to A ₁₅ on the address bus is selected by the selector 9. It is input to the address terminals A ₀ to A ₁₃ .

The contents of the address indicated by the value input to the address terminals A ₀ to A ₁₂ of the memory 5 are outputted through the data terminals D ₀ to D ₇ , and thus the input terminals D ₀ to D of the multiplexer 10. ₇ ) is entered. At this time, the multiplexer 10 selects one of the input terminals D ₀ to D ₇ by interpolating the values of the selection terminals A, B, and C, that is, the values A ₀ to A ₂ on the address bus. It is output to this output terminal y. That is, bit data for writing prohibition determination corresponding to the address to be recorded in the memory 4 is output, and it is determined whether or not to write data to the memory 4.

As described above, according to the memory device of the present invention, since data cannot be written to the memory write prohibited area at ordinary times except for the initial time, the unused area of the memory write prohibited area was not available. By devising the memory write prohibition area by byte unit, the efficiency of the storage device can be improved, and the density of the memory device due to the subdivision of the memory write prohibition area can be prevented.

Claims (1)

By a combination of the setter 1 for setting the access address value of the storage device, the comparator 2 for comparing whether the value set in the setter 1 and the address value match, and the input address value when enabled. In a write-protection apparatus of a storage device having a decoder (3) which outputs a memory chip select signal to one of the outputs, bit data storage for judging whether or not to write data to the memory (4) is stored and data is stored in the memory (4). Memory 5 for outputting a collection of bits for judging whether or not to write data corresponding to the address to be written to the memory 4 when recording the data, and an address value when the memory 4 is accessed from the address values on the address bus. Selector 9 for selecting and classifying address values when accessing the memory 5 and the memory 5 to the address input terminals A ₀ to A _{12 of the} memory 5, and outputting from the memory 5. And a multiplexer for outputting only one bit corresponding to the byte address of the data to be written to the memory (4) to the output terminal to determine whether data write is prohibited. .