KR100195750B1 - A memory which concurrently accesses data of an equal address - Google Patents

Abstract

The present invention relates to an address simultaneous access storage device, which comprises an address buffer (10) for buffering addresses 1, 2 and tags 1, 2 from a central processing unit; A first address generating unit (20) for generating the address 1 with the row address 1 and opening the address 1; A first buffer 30 for buffering the row address 1 and the opened dress 1; A second address generator (40) for generating the address 2 with the row address 2 and opening the address 2; A second buffer 50 for buffering the row address 2 and the open address 2; A cross access preventing unit (60) for demultiplexing the Tag 1 and the Tag 2 so that cross access does not occur when the address 1 and the address 2 are the same, and then outputting a result of the comparison; A first tag generator 70 for generating Tag 1 according to the comparison result; A second tag generator 80 for generating Tag 2 according to the comparison result; A control signal generator 90; A memory (100) for storing data; A first data input / output buffer 110 for inputting / outputting data; And a second data input / output buffer 120 for inputting and outputting data. According to the present invention, as described above, various data having various bit widths are simultaneously accessed to the same address, and data It has an effect that only data is accessed.

Description

A memory which concurrently accesses data of an equal address.

The present invention relates to an address simultaneous access storage device capable of simultaneously accessing data having the same address and accessing data having the same address by dividing it by a predetermined bit unit, Address simultaneous access storage device which simultaneously accesses data having a bit width at the same address and accesses only data to be accessed among the data having the same address.

In general, the data storage device can be classified according to the operation principle and the number of input / output ports. Here, a single-port memory and a dual- port memory.

The single-port memory device is a general memory device, and is a memory device that inputs and outputs one data in accordance with one address input and a control signal input.

On the other hand, the dual port memory device has two input / output terminals and is a memory device capable of accessing independently from both ports. That is, the two ports are all capable of accessing data independently of each other with an address input and a control signal input.

Here, the access refers to all operations (WRITE) of data to or from the data storage device according to a control signal, reading (READ) of data stored in the storage device, or search of data stored in the storage device .

FIG. 1 is a block diagram showing the configuration of a conventional dual port memory device as described above. The conventional dual port memory device shown in FIG. 1 includes an address buffer 2, a first happy memory 4, A first data input / output buffer 16, and a second data input / output buffer 18, a second memory controller 6, a second happy memory 8, a second memory controller 10, a control signal generator 12, a memory 14, .

The address buffer 2 receives addresses transmitted from a central processing unit (not shown) via an address bus in units of address bits (8 bits: A0 to A7 and A0 'to A7'), do.

Here, the address bit is a bit for designating an address. For example, if the address bit is 8 bits, an address from 0 to 255 (28 = 256) can be designated, and the address bus can be designated as a transmission path for address designation , And a unidirectional bus.

The 8-bit address buffered in the address buffer 2 is composed of a row address and an open address. Usually, the lower 4 bits (A0 to A3) of the 8-bit address are row addresses and the upper 4 bits (A4 to A7) Called open dress.

The first happy call section 4 decodes a row address (lower 4 bits: A0 to A3) input from the address buffer 2 and the first thermal protection section 6 inputs (Upper 4 bits: A4 to A7).

The second refresh counter 8 decodes the row addresses A0 'to A3' input from the address buffer 2 and the second refresh counter 10 decodes the row addresses A0 'to A3' And decodes the dresses A4 'to A7'.

The addresses A0 to A7 input to the first happy arbor 4 and the first heating resistor 6 and the addresses A0 to A7 input to the second happy arbor 8 and the second heating resistor 10 '~ A7') are different from each other. That is, the conventional dual port storage device can access data of different addresses independently. Data at the same address can not be accessed at the same time.

The control signal generator 12 generates all the control signals necessary for accessing the data from the memory 14.

The control signal (Row address strobe) signal, (Column address strobe) signal, (Write per bit / Write enable) signal and (Output enable) signal. Usually, the control signal is an active low signal, and an independent control signal is generated for each port, so that the control signal of one port can not control another port.

Here, The signal A signal that causes a row address from the address buffer (2) to be input to the first happy call section (4) or the second happy call section (8) during an active low period of the signal, The signal And an open address from the address buffer 2 is input to the first thermal protection unit 6 or the second thermal protection unit 10 during an active low period of the signal.

In addition, Signal The signal is a signal that enables selective writing to a 4-bit input signal during a write cycle. In the video RAM, since it is often desired to change only a certain bit of one word, Signals are often used. Signal A signal is a signal that enables writing of an input / output signal.

remind The signal is a signal that controls the data output during a read cycle.

The memory 14 stores data input / output from the first or second data input / output buffer 16 or 18 by the control signal.

Here, the memory 14 is implemented as a memory array in which memory cells, which are minimum units of memory, are regularly arranged in the row direction and the column direction. That is, the memory 14 is implemented as a memory array in which 256 memory cells are regularly arranged in 16 rows (R0 to R15) and 16 columns (C0 to C15) as shown in FIG.

The first data input / output buffer 16 outputs the data stored in the memory 14 or inputs data from the outside into the memory 14 according to the control signal and the address.

The second data input / output buffer 18 outputs the data stored in the memory 14 or inputs data from the outside to the memory 14 according to the control signal and the address.

The operation of the conventional dual port memory device configured as described above will be described with reference to FIG. It is assumed that one port (hereinafter referred to as the first port) of the conventional dual port memory device operates in the most basic read cycle and the other port (hereinafter referred to as the second port) operates in the most basic write cycle.

(1) When the first port operates as a read cycle

First, a control signal for informing a read cycle from a central processing unit (not shown) is input to the control signal generating unit 12. [

Next, when the control signal generator 12 is in the active low state 1 signal to the first happy call section 4, and outputs the signal in the active low state 1 signal to the first thermal protection unit 6.

At this time, 1 receives the row address from the address buffer 2 and decodes the row address, 1 signal is received, the first thermal protection unit 6 opens the address from the address buffer 2, and decodes it.

Then, the control signal generator 12 generates a control signal 1 signal to the memory 14. At this time, the memory 14 outputs the data indicated by the decoded address through the first data input / output buffer 16.

The output data is transmitted through a data bus.

(2) When the second port operates as a write cycle

First, a control signal indicating a write cycle from a central processing unit (not shown) is input to the control signal generating unit 12. [

Next, when the control signal generator 12 is in the active low state 2 signal to the second happy call section 8, and outputs the signal of the active low state 2 signal to the second thermal protection unit 10.

At this time, 2 receives the row address from the address buffer 2 and decodes the row address, 2 signal is input, the second thermal protection unit 10 opens the address from the address buffer 2, and decodes it.

Then, the control signal generator 12 generates a control signal And outputs a signal to the memory 14. At this time, the memory 14 stores the data input from the second data input / output buffer 18 in the memory array indicated by the decoded address.

Here, when the memory 12 is in the active low state Output buffer 18 to the memory array pointed to by the decoded address, and when the memory 12 is in the active low state The data is selectively input four bits from the second data input / output buffer 18 and stored in the memory array pointed to by the decoded address.

That is, the input data is written in the memory 14.

However, since the conventional dual port memory device can not access data having the same address at the same time, many areas of the memory 12 should be unnecessarily discarded when accessing data having various bit widths There was a problem.

In addition, although the memory 12 can receive data by 4 bits (half byte) at the time of a write cycle operation, all the data corresponding to the address is output at the same time during a read cycle operation, There is a problem that only one of the data that is held can not be read.

For example, assume that there is one address line per address in the memory 14, and that the bit width per address line is 16 bits. Here, the address line is the number of rows allocated to one address.

When the data (first port) to be input to an arbitrary address 111 has a bit width of 4 bits and the data (second port) to be input at the address 001 has a bit width of 6 bits, the address line of the address 111 12 bits are discarded without being written, and in the address line of the address 001, 10 bits are not written but discarded, and the utilization rate of the memory element is very low.

Further, when the data 111 and the data 112 share the address 111, that is, when the data 111 and the data 112 have the same address 111, there is a problem that only the data 1 or the data 2 can be read.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide an identical address simultaneous access storage device capable of simultaneously accessing data having the same address, The purpose is to do.

In order to attain the above object, the simultaneous access storage device of the same address of the present invention includes a Tag signal 1 including information on an address, an address 1 composed of an actual address 1, and a Tag signal 2, and an address 2 made up of an actual address 2 and accessing data independently, the dual port storage device comprising: an address buffer for buffering an address from the central processing unit; A first address generator for generating an actual address 1 input from the address buffer in a row address and an open address; A first buffer for buffering a row address and an open address from the first address generator; A second address generator for generating an actual address 2 input from the address buffer in a row address and an open address; A second buffer for buffering a row address and an open address from the second address generator; A cross access preventing unit for demultiplexing the Tag signal 1 and the Tag signal 2 from the address buffer and comparing the demultiplexed Tag signal 1 and the Tag signal 2 according to a predetermined crossover access table so as not to cross each other; A first tag generator for decoding the tag signal 1 from the address buffer to generate a tag signal 1 according to the comparison result; A second tag generator for decoding the tag signal 2 from the address buffer to generate the tag signal 2 according to the comparison result; A control signal generator for generating all control signals necessary for data access; A memory for storing the control signal, the decoded Tag, and input / output data according to the address; A first data input / output buffer for outputting data stored in the memory according to the control signal, the decoded Tag and the address, or for inputting data from the outside into the memory; And a second data input / output buffer for outputting the data stored in the memory according to the control signal, the decoded Tag and the address, or for inputting data from the outside into the memory.

According to the present invention as described above, not only data having the same address can be simultaneously accessed, but also data having the same address is accessed by dividing the data in units of certain bits, so that various data having various bit widths are accessed simultaneously to the same address , Only the data to be accessed among the data having the same address can be accessed.

1 is a block diagram showing a conventional dual port memory device,

2 is a block diagram showing the configuration of the same-address simultaneous access storage device according to the present invention;

3 (a) shows an example of a crossover access table,

(b) shows a process of simultaneously accessing the same address data on a 4-bit basis so that cross access does not occur according to the cross access table;

FIG. 4 is a diagram illustrating a process of writing data in a memory of the same address according to the crossover access table shown in FIG. 3 (a)

5 is a diagram illustrating a process of reading data stored in a memory of the same address according to the crossover access table shown in FIG. 3 (a).

Description of the Related Art [0002]

10: address buffer 20: first address generator

22: The First Happiness 24: The First Heavenly Father

30: first buffer 32: first row address buffer

34: first open address buffer 40: second address generator

42: The second happiness fox 44: The second heat fox

50: second buffer 52: first row address buffer

54: First Opening Buffer Buffer 60: Cross Accessing Prevention Unit

70: first tag generating unit 80: second tag generating unit

90: a control signal generator 100; Memory

110: first data input / output buffer 120: second data input / output buffer

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a general data storage device will be described in order to facilitate understanding of the present invention.

In general, the data storage device is classified according to the operation principle and the number of input / output ports. First, according to the operation principle, a random access read write memory (RAM) (Random Access Read Only Memory) (hereinafter referred to as ROM).

As long as the power is turned on, the RAM stores a static RAM (hereinafter referred to as SRAM) that keeps written data and a dynamic RAM (which refreshes the contents of periodically written data) Dynamic RAM: hereinafter referred to as DRAM).

The SRAM is distinguished into a nonvolatile SRAM that retains the written data even when the applied power is turned off, and a volatile SRAM that erases the written data when the power is turned off.

On the other hand, the ROM includes a mask ROM (Mask ROM) which can fix data during device manufacturing and can not be changed later, a fuse ROM (Fuse ROM) which can not change the data twice by once programming the data, An erasable programmable ROM (EPROM) capable of programming data several times, an electrically erasable programmable ROM (EEPROM) capable of electrically programming and erasing data, and a programmable read only memory Respectively.

Table 1 below is a table in which the above-described data storage device is classified according to the operation principle.

The data storage device classified according to the operating principle RAM SRAM Nonvolatile SRAM Volatile SRAM DRAM ROM Mask ROM Fuse ROM EPROM EEPROM

On the other hand, the data storage device is divided into a single port storage device and a dual port storage device according to the number of input / output ports.

The single-port memory device is a general memory device, and is a memory device that inputs and outputs one data in accordance with one address input and a control signal input.

On the other hand, the dual port memory device refers to a device in which two input / output terminals, that is, two ports, have address input and control signal input and can access data independently of each other.

The dual port storage device is divided into a normal dual port storage device and a dual port DRAM according to data access characteristics.

The conventional dual port storage device has an address input and a control signal input in each of two ports (port 1 and port 2), and is a device capable of independently accessing data from the two ports. That is, both ports are capable of data random access.

On the other hand, random access is possible in one port (random port) of the dual port DRAM and serial access is possible in the other port (serial port). That is, the random port side of the dual port DRAM controls all data accesses, and the serial port side executes only serial data input / output.

Although the present invention can be applied to both the conventional dual port storage device and the dual port DRAM, the present invention is applied to the ordinary dual port storage device.

FIG. 3 is a block diagram showing the configuration of the same address simultaneous access storage device according to the present invention. The same address simultaneous access storage device of the present invention is a dual port (port 1, port 2) )Wow; A first address generator 20; A first buffer 30; A second address generator 40; A second buffer 50; A cross access preventing unit (60); A first tag generating unit 70; A second tag generating unit 80; A control signal generator 90; A memory 100; A first data input / output buffer 110 and a second data input / output buffer 120.

Here, the first address generator 20 includes a first happhouctor 22; And a first thermal protection unit (24), wherein the first buffer (30) comprises a first row address buffer (32); And a first open dress buffer 34.

In addition, the second address generator 40 includes a second happy address 42; And a second thermal protection unit (44), wherein the second buffer (50) comprises a second row address buffer (52); And a second open dress buffer 54. [

First, for data access, a central processing unit (not shown) must input the address of the data to be accessed to the storage device in units of address bits. Here, the address bit consists of a Tag bit and an actual address bit.

Here, when the address bit is 10 bits, the address 1 input to the port 1 in units of 10 bits consists of the lower 2 bits Tag signal 1 (A0 ~ A1) and the upper 8 bits address (A2 ~ A9) It is assumed that the address 2 input in the lower 2 bits consists of the Tag signal 2 (A0 '~ A1') of the lower 2 bits and the address (A2 '~ A9') of the upper 8 bits.

Here, the Tag bit is a part of the address bits, and includes information regarding the address, and is a signal capable of identifying the information. That is, assuming that there is one address line per address of the memory 100 and a bit width per address line is 16 bits, the 2-bit Tag signal divides the data of the same address by 4 bits, It contains information that can be done.

For example, when the port 1 accesses data in the first four bits of the address 10001000, the port 2 is accessed twice in the 10001000 address. In this case, the same address simultaneous access means that four different bits of the same address line are simultaneously accessed. Second, data can be accessed in the third and fourth bits.

On the other hand, the address buffer 10 receives and buffers an address bit from the central processing unit, that is, a Tag bit and an actual address.

The first address generating unit 20 receives the actual address 1 (A2 to A9) from the address buffer 10 and outputs the row address (lower 4 bits: A2 to A5) and the open address (upper 4 bits: A6 to A9) Respectively.

That is, the first happy call section 22 decodes the row addresses A2 to A5 inputted from the address buffer 10, and the first thermal protection section 24 reads the row address A2 to A5 inputted from the address buffer 10, (A6 to A9).

The first buffer 30 buffers an address decoded by the first address generator 20.

That is, the first row address buffer 32 buffers the decoded row address from the first happy call section 22, and the first open address buffer 34 buffers the decoded row address from the first thermal protection section 24 Buffer the decoded open dress.

The second address generator 40 generates the address 2 (A2 'to A9') input from the address buffer 10 in a row address (lower 4 bits: A2 'to A5' To A9 ').

That is, the second happy call portion 42 decodes the row addresses A2 'to A5' input from the address buffer 10, and the second write / And opens the dresses (A6 'to A9').

The second buffer 50 buffers an address decoded by the second address generator 40.

That is, the second row address buffer 52 buffers the decoded row address from the second happy call portion 42, and the second open address buffer 54 buffers the decoded row address from the second heating portion 44 Buffer the decoded open dress.

Since the data access must be performed instantaneously even though it takes a long time to decode the address from the central processing unit, even if not at the time of data access, the address inputted according to the control signal of the control signal generating unit 80 Are stored in advance in the buffer (first row buffer 32, first column buffer 34, second row buffer 52, and second column buffer 54).

Here, the buffer is mainly implemented as a tri-state buffer. Because the normal buffer receives a signal according to the buffer capacity and outputs the input signal when it exceeds the capacity, the 3-state buffer operates as a normal buffer at the time of data access, And does not output the decoded signal as if it were not.

The 3-state buffer has a data input terminal, a 3-state enable input terminal and a data output terminal, and has three output states such as a high (1), a low (0) and a high impedance (Hi-Z) .

That is, when the 3-state enable signal is input from the 3-state enable input terminal, the 3-state buffer outputs a high or a low signal according to an input signal like a normal buffer, When the signal is ignored, a high-impedance (Hi-Z) signal is output so that no signal is output as the 3-state buffer does not operate functionally.

If the address 1 decoded by the first address generator 20 and the address 2 decoded by the second address generator 40 are the same, the cross access inhibitor 60 generates the same 4 Thereby preventing cross access to access data of the bit at the same time.

That is, the crossover access preventing unit 60 demultiplexes the Tag signal 1 and the Tag signal 2 from the address buffer 10, then compares the Tag signal 1 with the Tag signal 2 according to a predetermined crossover access table, Do not.

FIG. 3 (a) is an example of the cross access table, and FIG. 3 (b) is a diagram illustrating a process of simultaneously accessing the same address data on a 4-bit basis so that cross access does not occur according to the cross access table.

Referring to the crossover access table shown in FIG. 3 (a), the operation of the crossover access preventing unit 60 will be described below.

First, when the demultiplexed Tag signal 1 is 0, Port 1 accesses the first 4 bits of the address line designated by the address 1, so that Port 2 has 12 bits excluding the first 4 bits Can be accessed.

The first tag generator 70 decodes the tag signal 1 to generate a Tag signal 1 from the address buffer 10 according to the comparison result, and the second tag generator 80 decodes the tag signal 1 according to the comparison result And decodes Tag signal 2 from address buffer 10 to generate Tag signal 2.

The control signal generator 90 generates all the control signals necessary for data access.

The control signal signal, signal, Signal and There is a signal. Usually, the control signal is an active low signal, and an independent control signal is generated for each port, so that the control signal of one port can not control another port.

Here, The signal A signal that causes a row address from the address buffer 10 to be input to the first happy call portion 22 or the second happy call portion 42 during an active low period of the signal, The signal And an open address from the address buffer 10 is input to the first thermal protection unit 24 or the second thermal protection unit 44 during an active low period of the signal.

In addition, Signal The signal is a signal that enables selective writing to a 4-bit input signal during a write cycle. In the video RAM, since it is often desired to change only one bit of one word, Signals are often used. Signal A signal is a signal that enables writing of an input / output signal. remind The signal is a signal that controls the data output during a read cycle.

The memory 100 stores data input and output from the first and second data input / output buffers 110 and 120 according to the control signal.

Here, the memory 100 is implemented as a memory array in which memory cells, which are minimum units of memory, are regularly arranged in a row direction and a column direction. That is, the memory 100 is implemented as a memory array in which 256 memory cells are regularly arranged in 16 rows (R0 to R15) and 16 columns (C0 to C15) as shown in FIG.

The first data input / output buffer 110 outputs data stored in the memory 100 or inputs external data to the memory 100 according to the control signal and the address.

The second data input / output buffer 120 outputs data stored in the memory 100 or inputs external data to the memory 100 according to the control signal and the address.

The operation of the same-address simultaneous access storage device of the present invention constructed as above will be described with reference to FIGS. 2 and 3. FIG.

FIG. 4 is a diagram illustrating a process of simultaneously writing data stored in a memory at the same address according to the crossover access table shown in FIG. 3 (a).

As shown in Fig. 4, the address 1 inputted to the port 1 from the central processing unit is composed of the Tag signal 1 of 2 bits and the address 10101100 of 8 bits, and the address 2 inputted to the port 2 is composed of 2 bits And a 10-bit address 10101100 of 8 bits.

Then, since the Tag signal of the port 1 is 1, 8 bits of the data 1 (0000 1101) input from the data bus are sequentially written into the address 10101100 line of the memory 100 in 4-bit order. 12 bits of data 1 (1101 0101 0010) input from the bus are written into the address 10101100 line of the memory 100 in order of 4 bits in sequence.

However, because cross access is generated in the second 4 bits of the address 10101100 line, it causes great damage to the data access. Therefore, in the present invention, the cross access is prevented through the cross access preventing unit 60,

5 is a diagram illustrating a process of simultaneously reading data stored in a memory at the same address according to the crossover access table shown in FIG. 3 (a).

As shown in Fig. 5, the address 1 input to the port 1 from the central processing unit is composed of a Tag signal 0 of 2 bits and an address 10001010 of 8 bits, and an address 2 input to port 2 is 2 bits Of the Tag signal 10 and an address 10001010 of 8 bits.

The port 1 reads the first 4 bits of data 1001 stored in the address 10001010 line of the memory 100 because the Tag signal is 0. The port 2 reads the data 100011010 of the memory 100 And reads the remaining 12 bits of data (1111 0001 1010), which have been stored in the memory, in units of 4 bits.

That is, the data stored at the same address is normally read out by 4 bits at a time without cross access.

As described above, the same address simultaneous access storage device according to the present invention not only can access data having the same address at the same time, but also accesses data having the same address by dividing it into a certain bit unit, There is an advantage that only a plurality of data are accessed at the same address at the same time and only data to be accessed among the data having the same address is accessed.

Hereinafter, in the claims, the Tag signal 1 is referred to as a first tag signal, the Tag signal 2 is referred to as a second tag signal, the real address 1 is referred to as a first real address, and the real address 2 is referred to as a second real address , The address 1 is referred to as a first address, and the address 2 is referred to as a second address.

Claims (6)

A first tag signal including information on an address from a central processing unit, a first tag signal including a first address composed of a first real address and information on an address, and a second address composed of a second real address A dual port memory device for independently accessing data, comprising: an address buffer (10) for buffering an address from the central processing unit; A first address generator 20 for generating a first real address received from the address buffer 10 in a row address and an open address; A first buffer 30 for buffering a row address and an open address from the first address generator 20; A second address generator (40) for generating a second actual address received from the address buffer (10) in a row address and an open address; A second buffer 50 for buffering the row address and the open address from the second address generator 40; Demultiplexes the first tag signal and the second tag signal from the address buffer 10 and then compares the demultiplexed first tag signal and the second tag signal according to a predetermined crossover access table so as not to cross each other A cross access preventing unit (60); A first tag generator (70) for decoding the first tag signal to generate a first tag signal from the address buffer (10) according to the comparison result; A second tag generator 80 for decoding the second tag signal to generate a second tag signal from the address buffer 10 according to the comparison result; A control signal generator 90 for generating all control signals necessary for data access; A memory (100) for storing the control signal, the decoded tag signal, and data input / output in accordance with an address; A first data input / output buffer 110 for outputting data stored in the memory 100 according to the control signal, the decoded tag signal and an address or for inputting data from the outside into the memory 100; And a second data input / output buffer 120 for outputting the data stored in the memory 100 according to the control signal, the decoded tag signal and the address, or for inputting data from the outside into the memory 100 And the second address is stored in the second memory. The apparatus of claim 1, wherein the first address generator (20) comprises: a first happy caller (22) for receiving and decoding a row address of an actual address from the address buffer (10); And a first refreshing unit (24) for receiving and decoding the open address among the actual addresses from the address buffer (10). The apparatus of claim 1, wherein the first buffer (30) comprises: a first row address buffer (32) buffering a decoded row address from the first address generator (20); And a first open address buffer (34) for buffering the decoded open address from the first address generating unit (20). The apparatus of claim 1, wherein the second address generator (40) comprises: a second happy call section (42) for receiving and decoding a row address of an actual address from the address buffer (10); And a second refreshing unit (44) for receiving and decoding the open address among the actual addresses from the address buffer (10). The apparatus of claim 1, wherein the second buffer (50) comprises: a second row address buffer (52) buffering the decoded row address from the second address generator (40); And a second open address buffer (54) for buffering the decoded open address from the second address generator (40). The apparatus of claim 1, wherein the first buffer (30) and the second buffer (50) are implemented as a three-state buffer.