KR940003605B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

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Description

Semiconductor device and manufacturing method

1 is a cross-sectional view showing the FETs provided in the semiconductor device according to the first embodiment of the present invention in the order of manufacturing process.

FIG. 2 is a plan view of the FET including the section of FIG. 1 at the position indicated by the line A-A '. FIG.

3 is a cross-sectional view illustrating the FETs provided in the semiconductor device according to the second embodiment of the present invention in the order of manufacturing process.

4 is a plan view of the FET including the section of FIG. 2 at the position indicated by the line B-B '.

5 is a plan view showing the FETs provided in the semiconductor device according to the third embodiment of the present invention in the order of manufacturing process.

FIG. 6 is a plan view showing only a partial process of a FET included in a semiconductor device according to a fourth embodiment of the present invention in the order of manufacturing process; FIG.

7 is a sectional view of a conventional MOS transistor.

8 is a plan view of the MOS transistor shown in FIG.

* Explanation of symbols for main parts of the drawings

1: p-type silicon substrate 3: first groove

4 columnar region 5 gate insulating film

6: Gate electrode (polysilicon _{layer) 7 1, 7 2: n} + type impurity layer

8 CVD oxide film 8 'CVD oxide film covering the gate electrode

9 ₁ : 2nd groove part 9 ₃ : 3rd groove part

10 ₁ , 10 ₂ : source / drain diffusion layer 11: aluminum film

11 ₁ to 11 ₃ : wiring 12: interlayer insulating film

13 connection hole 14 columnar region formed by SEG method

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, a semiconductor device and a method for manufacturing the same are provided. In particular, a semiconductor device and a method for manufacturing the same are provided. It relates to a semiconductor device.

[Traditional Technology and Problems]

The structure of a conventional MOS transistor is shown in FIGS. 7 and 8.

7 is a cross-sectional view of a conventional MOS transistor, and FIG. 8 is a plan view of a MOS transistor including the cross section in a line C-C '.

As shown in FIG. 7 (in the drawing, the MOS transistor is, for example, an n-channel type), an isolation region 102 is formed on the surface of the p-type substrate 101, whereby the n-type source / Drain regions 103 ₁ and 103 ₂ are formed. The gate insulating film 104 is formed on the channel region between the source / drain region 103 ₁ and the source / drain region 103 ₂ , and the gate electrode 105 is formed thereon.

Next, when the MOS transistor is viewed in a plan view of FIG. 8, source / drain regions 103 ₁ and 103 ₂ are formed at both sides of the gate electrode 105. At this time, the width L of the gate electrode 105 is referred to as the channel width and the width W of the source / drain region 103 in the direction orthogonal to the channel length direction.

The current driving capability (Id) of the MOS transistor of the above structure is under the condition of V _d > V _G -V _T ,

I _d = (W / 2L) x μCox (V _G -V _T ) ² . … … … … … … … … … … … … … … (2)

Is displayed. Where L is the channel length, W is the channel width, μ is the mobility, and Cox is the capacitance of the gate insulating film, and V _d , V _G , and V _T are the drain voltage, gate voltage, and gate threshold voltage, respectively.

Currently, as a method of obtaining a high output MOS transistor that requires a large current driving capability (Id), as shown in (1), there are many methods of increasing the current driving capability (Id) by increasing the gate width (W). It is used. However, the method of increasing the current driving capability Id has a problem in that the device plane area increases as the gate width W is increased, thereby counteracting the device miniaturization.

References (1) T. Mizuno et al., Symp. VLSI Tech. Dig., P 23 (1988)

[Purpose of invention]

The present invention has been made in view of the above problems, and provides a semiconductor device having a high output FET capable of achieving high integration while increasing current driving capability by increasing the channel width per device plane area of the FET, and a method of manufacturing the same. Has its purpose.

[Configuration of Invention]

The semiconductor device of the present invention for achieving the above object has a first main surface on at least one surface; A second main surface having a height different from this in the substrate thickness direction; A semiconductor substrate having a columnar region consisting of successive side surfaces thereof, the second main surface having at least one curved portion in plan view, and thus the columnar region having a curved portion; First and second regions of opposite conductivity type to the substrate formed in the surface regions of the first and second main surfaces; And a FET having a gate electrode formed to have a curved portion along the side surface of the columnar region.

(1) In the semiconductor device described above, the side surfaces of the columnar regions have locations facing each other, and the relationship between the distance d between the locations facing each other and the thickness T of the gate electrode. end

d> 2T

Work,

(2) When the columnar region has a minimum width b and a gate depletion layer Xj,

b ≤2Xj

At least one of the two terms, such as to be configured to have a size satisfactory, is configured to be satisfied.

In addition, in the method of manufacturing a semiconductor device of the present invention, a semiconductor substrate having a first main surface on at least one side thereof has a first main surface and a second main surface having different heights in the thickness direction of the substrate so as to have side surfaces and curved portions connected to each other. Forming, a step of forming a first insulating film on the first and second main surfaces and a side surface connecting the same, a step of depositing a first conductor film on the first insulating film, and etching the first conductor film along the side surface. A step of retaining a predetermined amount in the form of sidewalls, A step of introducing a first impurity of opposite conductivity to the first and second main surfaces by using the first conductor film remaining in the form of a sidewall as a mask, and a second insulating film on the entire surface. Depositing a second insulating film, etching the second insulating film to cover the first conductor film along the side surface, and leaving a predetermined amount in a sidewall shape; etching the second insulating film to expose the first and second films Forming at least two first and second groove portions by etching a predetermined amount of the semiconductor, which is a material constituting these, on the two main surfaces with a mask, using a second insulating film; and using a second insulating film as a mask. Introducing a second impurity into the first and second grooves; forming a second conductor film on the entire surface; etching the second conductor film until at least the second insulating film is exposed; It is equipped with the process of forming wiring by remaining.

[Action]

In the semiconductor device described above, a columnar region having curved portions exists in the semiconductor substrate, and a channel region is formed along the side surface of the columnar region, thereby forming a FET having a gate electrode having curved portions. . Therefore, the channel width per device plane area in the planar direction is increased and the columnar region is curved, so that the area in the planar direction can be effectively used, and the increase is further increased.

Specific examples of the columnar region having the curved portion include a spiral or zigzag shape.

In addition, when the columnar region is spiral or zigzag-shaped, a place where the curved region of the columnar region is opposite to each other is generated. In this case, the distance between the opposing points is d, and the thickness of the gate electrode formed on the side of the columnar region is T.

d> 2T

In other words, even when the thickness T of the gate electrode is doubled, if the interval d is increased, the columnar region is not buried by the formation of the gate electrode.

In the manufacturing method, a columnar region having a bent portion on the semiconductor substrate is formed by selective vapor growth or digging a groove, and the first insulating film, the gate electrode, and the gate electrode, which are gate insulating films, are insulated from other conductive layers. The second insulating film is sequentially formed. Subsequently, the second insulating film is etched to expose the semiconductor on the ceiling surface of the columnar region and the bottom surface of the columnar region. Subsequently, the semiconductor is etched using the remaining second insulating film as a mask, so that first and second grooves are formed in self-alignment on the ceiling surface and the bottom surface, respectively. Subsequently, a conductor layer to be a wiring is formed, and the conductor layer is etched to leave the conductor layer in the first and second grooves so as to form a wiring self-aligned with respect to the source / drain diffusion layer.

EXAMPLE

EMBODIMENT OF THE INVENTION Hereinafter, with reference to drawings, the semiconductor device which concerns on embodiment of this invention is demonstrated with the manufacturing method.

1A to 1I are sectional views showing the MOS transistor included in the device of the first embodiment of the present invention in the order of manufacturing process, and FIGS. 2A to 2E are top views showing the manufacturing process order. In these top views, the cross section of FIG. 1 is along the line AA ′.

First, as shown in FIGS. 1A and 2A, the field insulating film 2 is formed on, for example, a p-type silicon substrate by, for example, the LOCOS method. Subsequently, the first groove 3 is selectively excavated in the substrate 1 using, for example, a photolithography method using a photoresist. At this time, the helical columnar region 4 is formed by digging the first groove 3 into a helical shape, for example.

At this time, as shown in the plan view of FIG. 2A, for example, the columnar region 4 is formed by being separated into islands by the first groove portion 3. In this case, the parts separated by the first groove 3 in addition to the columnar region 4 are shown by the reference numeral 4 '.

The spiral columnar region 4 is not formed separately from 4 'in the figure, but may be formed to be connected to each other.

Subsequently, as shown in FIG. 1B and FIG. 2B, the gate insulating film 5 is formed on the surface of the columnar region 4 by, for example, thermal oxidation. Subsequently, a polysilicon layer is deposited on the entire surface by, for example, CVD, to a thickness less than half the width of the first groove 3. Subsequently, the polysilicon layer was left on the side of columnar region 4 in the form of a side wall by RIE method, which is indicated by reference numeral 6 in the figure. When remaining in the form of sidewalls, a slight exposed portion is provided on the columnar region 4.

At this time, a mask such as a photoresist is placed on the polysilicon layer to form a region 6b serving as a gate connection portion and a wiring region 6a thereupon, for example, as shown in the drawing. Subsequently, n-type impurities such as arsenic light are ion-implanted into the columnar region 4 and the substrate 1 using the polysilicon layer 6 as a mask to form n ⁺ -type impurity layers 7 ₁ to 7 ₃ .

Subsequently, as shown in FIG. 1C, the VCD oxide film 8 is deposited on the entire surface by, for example, CVD.

Subsequently, as shown in FIG. 1D, the CVD oxide film 8 is etched to remain on the sidewall of the columnar region 4 in the form of sidewalls, and the polysilicon layer 6 covers the CVD oxide film 8. This state is indicated by reference numeral 8 'in the drawings. When the CVD oxide film 8 'is removed, silicon on the ceiling surface (near 7 _{2 in} the figure) and the bottom surface (near 7 _{1 in} the figure) of the columnar region 4 are exposed.

Subsequently, as shown in FIG. 1E and FIG. 2C, the silicon exposed by the etching process of the CVD oxide film 8 is etched to form the second grooves 9 ₁ and the third grooves 9 ₂ .

Subsequently, as shown in FIG. 1f, arsenic is ion-implanted into the second and third grooves 9 ₁ and 9 ₂ to form n ⁺ type source / drain diffusion layers 10 ₁ and 10 ₂ . At this time, the source / drain diffusion layer 10 ₁ is integrated with the n ⁺ type impurity layer 7 ₁ described above.

Subsequently, as shown in FIG. 1G, for example, an aluminum film 11 serving as a wiring layer is deposited on the entire surface by sputtering.

Subsequently, as shown in FIG. 1H and FIG. 2D, the aluminum film 11 is etched to form wirings in the second and third grooves 9 ₁ and 9 ₂ , respectively, and self-aligned. This state is indicated by reference numerals 11 ₁ and 11 ₂ in the drawings.

In addition, the Figure 2d is a region shown by reference numeral 11 _a ~ 11 _c of a connecting portion.

Then, the 1i also, as indicated in claim 2e also, forming depositing the interlayer insulating film 12 over the entire surface, and after the connection portion _{(6b, 11 a ~ 11 c} ) the connection hole 13 that leads to, for example photolithographic method Open using.

Through the above process, the MOS transistor included in the device of the first embodiment is formed.

In this MOS transistor, the columnar region 4 is curved in a spiral shape, and a channel region is formed along the side surface of the columnar region 4, and a gate electrode is formed on the side surface, so that the channel width per device plane area is provided. Is increased.

Thus, a MOS transistor with high driving capability is obtained.

In addition, the manufacturing method is formed by filling the conductor layer serving as the wiring layer with the second and third groove portions 9 ₁ and 9 ₂ obtained by etching the silicon wires to the source / drain diffusion layers 10 ₁ and 10 ₂ . It is advantageous for device miniaturization.

When the thickness of the gate electrode 6 is T and the width of the columnar regions 4 is d, the relationship between them is

d> 2T

Shall be. By doing so, in the bent columnar region 4 as shown in Figs. 1B and 2B, the portions facing each other are not buried by the gate electrode 6, and the diffusion layer 7 ₁ is also formed on the bottom surfaces of the columnar regions. Alternatively, the source / drain diffusion layer 10 ₁ shown in FIG. 1f may be formed.

Furthermore, when the width of the gate depletion layer is Xj and the width of the columnar region 4 is b

b ≤2Xj

When the relationship is satisfied, as described in the above reference, higher driving capability is expected by the gate bias, and a high output MOS transistor having a large current driving capability with a small device plane area can be obtained.

Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4.

3A to 3I are sectional views showing the MOS transistors provided in the device of the second embodiment of the present invention in the order of manufacturing processes, and FIGS. 4A to 4E are top views showing the manufacturing process order. In these top views, the cross section in FIG. 3 is along the line BB ′.

In addition, in FIG. 3 and FIG. 4, the same code | symbol is attached | subjected about the same part as FIG. 1 and FIG.

First, as shown in FIG. 3A and FIG. 4A, the field insulating film 2 is formed on the p-type silicon substrate 1 similarly to the first embodiment, and then subjected to selective epitaxial growth (SEG). The spiral columnar region 14 is formed to protrude from the substrate 1. The conductivity type is, for example, the same p type as the substrate 1.

Next, the process shown in FIG. 3B and FIG. 4B is the same as the process of FIG. 1B and 2B mentioned above, for example.

In this case, as shown in the plan view of Fig. 4B, a mask such as a photoresist is placed on the polysilicon layer, and as shown in the figure, for example, the region 6b serving as the gate connection portion and the wiring region 6a up to it are shown. Form.

The processes shown in FIGS. 3C and 3D are the same as those described in FIGS. 1C and 1D, for example.

However, in the case of forming the columnar region 14 protruding from the substrate 1, a mask such as a photoresist is placed on the wiring regions 6a and 6b made of a polysilicon layer, and these are deposited on the CVD oxide film 8 '. Cover with).

The process shown in FIG. 3E and FIG. 4C is the same as the process demonstrated by FIG. 1E and FIG. 2C, for example.

Here, in the plan view of Fig. 4C, the CVD oxide film 8 'covering the wiring regions 6a and 6b in the above steps is indicated by reference numerals 8'a and 8'b in the drawings, respectively.

The processes shown in FIGS. 3f and 3g are the same as those described in FIGS. 1f and 1g, for example.

The process shown in FIG. 3H and FIG. 4D is the same as the process demonstrated by FIG. 1H and FIG. 2D, for example.

Here, the areas indicated by reference numerals 11a and 11b in FIG. 4d are connected portions.

The processes shown in FIGS. 3i and 4e are the same as those described in FIGS. 1i and 2e, for example.

Here, the connection hole 13 is opened with respect to the connection parts 6a, 11a, 11b.

Through the above steps, the MOS transistor included in the device of the second embodiment is formed.

Thus, even if the region protruding on the substrate 1 is selectively formed, thereby obtaining the columnar region 4, the same effects as in the first embodiment can be obtained. In addition, unlike the first embodiment, the method of obtaining the first groove 3 in the second embodiment is such that the columnar regions 14 face each other, but the first groove 3 in the first embodiment and the same. Role does not change substantially. Therefore, the same reference numerals are given to this second embodiment.

In the above, it demonstrated that the pattern of the columnar area | region which has a curved location is spiral.

Next, although there are many patterns of columnar regions having curved portions, the third and fourth embodiments will be described as examples, taking zigzag shapes as an example.

5A and 5B are plan views in one manufacturing process as the third embodiment, respectively. In FIG. 5, the same reference numerals are given to the same parts as in FIG.

First, as shown in FIG. 5A, the columnar region 4 is formed in a zigzag shape instead of a spiral in the same process as in the first embodiment.

In this third embodiment, the columnar region 4 formed in a zigzag shape is separated into islands by the first groove portion 3, but may be formed so as to be connected to the region marked 4 'separately in the drawing.

Next, as shown in FIG. 5B, the impurity layers 7 ₁ to 7 ₃ of the opposite conductivity type to the gate insulating film 5, the gate electrode 6 and the substrate 1 are prepared in the same manner as in the first embodiment. Form. In addition, for example, the region 6b serving as the gate connection portion and the wiring region 6a up to that shown in the figure were also formed by the limiting method represented by, for example, photolithography.

The subsequent manufacturing steps are not shown separately, but may be the same steps as those in the first embodiment.

As described above, even if the shape of the columnar region 4 is set in a zigzag shape and a curved portion is obtained, the same effect as in the first and second embodiments is, of course.

Next, the semiconductor device according to the fourth embodiment will be described with reference to FIG.

6A and 6B are plan views of one manufacturing process each as the fourth embodiment. In FIG. 6, the same reference numerals are given to the same parts as in FIG.

First, as shown in FIG. 6B, the impurity layers 7 ₁ and 7 ₂ of the opposite conductivity type to the gate insulating film 5, the gate electrode 6 and the substrate 1 are formed in the same manner as in the second embodiment. do. For example, as shown in the drawing, the region 6b serving as the gate connection portion and the wiring region 6a thereupon are also formed by the limiting method represented by, for example, photolithography.

Although subsequent manufacturing steps are not separately shown, the same steps as those in the second embodiment may be used.

As described above, even if the shape of the columnar region 14 is set in a zigzag shape to obtain a curved portion, the same effects as in the first to third embodiments are, of course.

The FETs provided in the semiconductors different from those in the first to fourth embodiments have been described in the case of the MOS type, and the description has been made as to how to obtain a high output MOS transistor and its manufacturing method.

It is a matter of course that the present invention can sufficiently exhibit the effect of any MOS type FET if it is a FET. For example, an MES type FET represented by a FET formed on a GaAs substrate may be used. In this case, of course, it is not necessary to form the gate insulating film, and since GaAs itself is semi-insulating, it is not necessary to form the device isolation region represented by the field insulating film.

[Effects of the Invention]

As described above, the present invention provides a semiconductor device with a high output FET capable of achieving high current driving capability and further high integration by increasing the channel width per device plane area of the FET, and a method of manufacturing the same. .

Claims (4)

A first main surface on at least one side; A second main surface having a height different from this in the substrate thickness direction; These are provided with columnar regions 4, 14 formed of continuous side surfaces, and the second main surface has at least one curved portion in plan view, and thus the columnar regions 4, 14 are formed. A semiconductor substrate 1 having these curved points; First and second regions 10 ₁ and 10 ₂ of opposite conductivity type to the substrate formed on the surface regions of the first and second main surfaces; And a gate electrode (6) formed to have a bent portion along the side surfaces of the columnar regions (4, 14). The side surfaces of the columnar regions 4 and 14 have positions facing each other, and the relationship between the distance d between the portions facing each other and the thickness T of the gate electrode is determined. d> 2T A semiconductor device, characterized in that. The method according to claim 1, wherein the columnar regions 4 and 14 have a minimum width b and a width of the gate depletion layer Xj. b ≤2Xj A semiconductor device having a size that satisfies the relationship. Forming a first main surface and a second main surface having a height different from each other in the thickness direction of the substrate in plan view on the semiconductor substrate 1 having the first main surface on at least one side thereof; Forming a first insulating film 5 on the main surface and side surfaces connecting them; depositing a first conductor film 6 on the first insulating film 5; etching the first conductor film 6 A step of retaining a predetermined amount in a sidewall shape along the side surface, and using a first conductor film 6 remaining in the sidewall shape as a mask, a first impurity of opposite conductivity type to the substrate 1 as a mask. A step of introducing the second insulating film 8 to the entire surface; and etching the second insulating film 8 to cover the first conductor film 6 along the side surface. A step of remaining 8 'is performed on the first and second main surfaces exposed by etching the second insulating film 8. A semiconductor material that generates the in process, the mask of the second insulating film 8 that by the second insulating film (8) etching a predetermined amount as a mask to form at least two first and second grooves _{(91, 92)} Introducing a first impurity of opposite conductivity type to the substrate 1 into the first and second grooves 9 ₁ and 9 ₂ ; forming a second conductor film 11 on the entire surface; And a step of forming the wirings 11 ₁ and 11 ₂ by etching 11) until at least the second insulating film 8 is exposed and remaining in the first and second grooves. Method of manufacturing the device.

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