KR940003038B1 - Noise canceller - Google Patents

Abstract

The circuit is for preventing amplified noise signal from being recognized as a color signal in SECAM type color signal process. The circuit comprises a reset control signal generator (10) for generating reset control signal (P1) according to a positive edge detection signal (P17), a counter (20) for generating signals (P11,P12,P13) having different frequency according to the output of the reset signal generator (10), a gate signal generator (30) for generating signal with a constant pulse width and constant intervals and a positive edge detector (40) for detecting positive edge at the instant of output signal of the gate signal generator (30).

Description

Gate signal generation circuit for noise reduction during horizontal synchronization

1 is a circuit diagram of a gate signal generation circuit according to the present invention.

2 is a signal waveform diagram of each part of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video color signal processing system of a VHS type video tape recorder (VTR). In particular, when processing a video color signal of a SECAM type, a noise signal is amplified through a high amplification amplifier to prevent a signal from being recognized as a color signal. It relates to a gate signal generation circuit for removing noise during a horizontal synchronization period for generating a.

In general, the SECAM broadcasting method transmits two color signals per horizontal scanning period (1H) by FM modulation of a subcarrier, and delays the signals by one horizontal scanning period (1H) on the receiving side on the same scan line. This is how you reproduce colors.

In the Secam method of the VCAM VTR color signal processing system, the color signal is carried on the composite video signal during the horizontal synchronization period. In the absence of the color signal, the noise signal is amplified through a high-amplification amplifier and incorrectly recognized as a color signal. In order to prevent this, the gate signal is generated to prevent the amplification of the noise signal in the absence of the color signal.

As a circuit for generating such a gate signal, a circuit using RC charging and discharging has been conventionally used, which uses a RC (time constant) charging and discharging time. This circuit generates a signal, but this circuit has a problem in that R (resistance) and C (capacitor) integration (IC) is difficult, and the time signal of the gate signal varies considerably according to the RC (time constant) value.

The present invention has been invented to eliminate the problems of the conventional gate signal generation circuit described above, and can be integrated with high-density IC, and can reduce external components to prevent malfunction of the system due to noise. It is an object of the present invention to provide a gate signal generation circuit for noise reduction during a horizontal synchronizing period which can be reduced and highly reliable.

The present invention for achieving the above object is a reset control signal generating means 10 for generating a reset control signal in accordance with a positive edge detection signal applied by inputting a mixed synchronization signal (CS), for example, A counter means 20 for outputting signals P11, P12, P13 of a predetermined frequency in accordance with an output signal of the reset control signal generating means, with an input of a 4.43 MHz oscillation (VCO) signal; Positive by inputting the output signal of the gate signal generating means 30 and the gate signal generating means 30 to generate a signal having a pulse width of a predetermined time at regular intervals based on the horizontal synchronization signal It characterized in that it consists of a positive edge detection means 40 for detecting an edge (positive edge).

The reset control signal generating means 10 specifically includes an inverter 11 for inverting the mixed synchronous signal CS, a NAND gate ND1 having the output of the inverter 11 as one input, and the positive edge detection signal. And a NAND gate ND2 having one input, and the counter means 20 includes T flip-flops TFF1 and TFF2, D flip-flops DFF1-DFF7, and an AND gate to output a signal of a predetermined frequency. AD1-AD4).

In addition, the gate signal generating means 30 receives the output signal of the AND gates AD2-AD4 of the counter means 20 and outputs a gate signal having a pulse width of a predetermined time (ND3-ND6). It consists of.

Hereinafter, the operation and effects of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram according to the present invention, and FIG. 2 is a signal waveform diagram of each part of FIG. 1, and the output signal P1 of the reset control signal generating means 10 including the NAND gates ND1 and ND2 and the inverter I1. ) Is changed from the "high" level state to the "low" level state when the mixed synchronous signal CS changes from the "low" level to the "high" level state, and the output signal from the positive edge detection means 40 again becomes " When the state changes from the "high" level to the "low" level, the state falls from the "high" level to the "low" level.

Counter means for generating the output signal after a predetermined time on the basis of the horizontal synchronous signal by the reset control signal generating means 10 is input to the output signal (P1) and 4.43MHz Voltage Controlled Osillator (VCO) signal (CK) 20 is operated from the moment when the output signal P1 of the reset control signal generating means 10 falls from the "high" level to the "low" level, and then again changes to the "high" level state. In the means 20, the T flip-flop TFF1 outputs a two-divided signal P2 at the output terminal TQ with the VCO signal CK of 4.43 MHz as the input of the clock terminal CK, and then the D flip-flop DFF1. The signal is input to the clock terminal CK of DFF2 and to one input terminal of the AND gate AD2.

Therefore, the D flip-flop DFF1, which uses the output signal of the T flip-flop TFF1 as the clock signal CK, converts the output signal of the D flip-flop DFF2 output terminal FQ into the input signal of the data input terminal D. A signal obtained by dividing the output signal P2 of the T flip-flop TFF1 into four is output from the output terminal TQ, and the output signal is input to the data input terminal D of the D flip-flop DFF2. The signal output from the output terminal FQ of the D flip-flop DFF1 is an inverted signal P3 of the signal output from the output terminal TQ of the flip-flop DFF1, and this signal P3 is the AND gate AD3. It becomes one input signal of. The output signal P2 of the D flip flop DFF2 and the T flip flop TFF1 is used as a clock signal, and the signal output from the output terminal TQ of the D flip flop DFF1 is input to the data input terminal D. The signal is delayed by a quarter cycle from the output signal output from the output terminal TQ of the D flip-flop DFF1, and is input to the clock terminal CK of the D flip-flops DFF3 and DFF4. Input to one input terminal of).

The output signal of the output terminal FQ, which is a signal inverted from the output signal P4 of the D flip-flop DFF2 output terminal TQ, is input to the data input terminal D of the D flip-flop DDF1.

The D flip-flop DDF3 divides the quadrant of the D flip-flop DFF2 output signal P4 by using the output signal of the D flip-flop DDF4 output terminal FQ as an input signal of the data input terminal D. The signal is input to the data input terminal D of the D flip-flop DFF4.

The D flip-flop DFF4 converts the output signal P4 of the D flip-flop DFF2 into a clock signal CK, and outputs an output signal of the output terminal TQ of the D flip-flop DFF3 into a data input terminal D. ) And outputs a signal P5 obtained by delaying the output signal of the output terminal TQ of the D flip-flop DFF3 by a quarter cycle, and the signal P5 is a clock of the D flip-flop DFF5-DFF7. In addition to being a signal, it becomes a one input signal of the AND gate AD2.

Therefore, the D flip-flop DFF5 operates by using the output signal of the AND gate AD1 as the input signal of the data input terminal D. The output signal of the AND gate AD1 is initially maintained at a "high" level. When the signal input to the clock terminal CK of the D flip-flop DFF5 changes from the "high" level to the "low" level, the signal output from the output terminal TQ of the D flip-flop DFF5 is It will change from the initial "low" level to the "high" level. This output signal is input to the data input terminal D of the D flip-flop DFF6, and after the signal changes from the "low" level to the "high" level, the signal input to the clock terminal CK is "high". When the level is changed from the "low" level to the "low" level, the output signal P7 of the output terminal TQ of the D flip-flop DFF6 changes from the initial "low" level to the "high" level, and this signal P7 One input of the gate AD4 is simultaneously input to the data input terminal D of the D flip-flop DFF7. The output signal FQ of the D flip-flop DFF6 is an inverted signal of the output signal TQ of the D flip-flop DFF6, and becomes one input of the AND gate AD1.

Therefore, after the signal P7 input to the data input terminal D of the D flip-flop DFF7 is changed from the "low" level to the "high" level, the signal input to the clock terminal CK is at the "high" level. When changing to the "low" level, the output signal P8 of the output terminal TQ of the D flip-flop DFF7 changes from the "low" level to the "high" level and is output. This signal P8 is a T flip-flop. It becomes a clock signal of TFF2 and becomes an input signal of the AND gate AD4. The output signal of the output terminal FQ of the D flip-flop DFF7 becomes one input signal of the AND gates AD1 and AD3 as an inverted signal of the output terminal TQ output signal.

After dividing the output signal P8 of the D flip-flop DFF7 as the clock signal of the T flip-flop TFF2, the output signal P9 is output from the output terminal TQ of the T flip-flop TFF2. The signal P9 is input to one input terminal of the AND gate AD4, and the output signal P6 of the output terminal FQ of the T flip-flop TFF2 is an inverted signal of the output signal P9. It is input to the one input terminal of AD3.

The AND gate AD2 is an output signal P2 at the output terminal TQ of the T flip-flop TFF1, an output signal P4 at the output terminal TQ of the D flip-flop DFF2, and the D flip-flop. The output signal P5 is combined, and the AND gate AD3 includes the output signal P3 of the D flip-flop DFF1 output terminal FQ and the D flip-flop DFF7 output terminal FQ. The output signal P10 and the T flip-flop TFF2 output terminal FQ output signal P6 are combined, and the AND gate AD4 is the D flip-flop DFF6 output terminal TQ output signal P7. ) And the output signal P8 of the D flip-flop DFF7 output terminal TQ and the output signal P9 of the T flip-flop TFF2 output terminal TQ are combined.

The output signal P11 of the AND gate AD2 is input to one terminal of the NAND gate ND3 and one terminal of the NAND gate ND4 in the gate signal generating means 30, and The output signal P13 is input to the other terminal of the NAND gate ND4, and the output signal P12 of the AND gate AD4 becomes a type force signal of the NAND gate ND3.

In addition, the output signal P14 of the NAND gate ND3 is used as one input of the NAND gate ND5 of the gate signal generating means 30, and the output signal P16 of the NAND gate ND6 is set as a type force. The combination of the input signals P14 and P16 changes from the "high" level to the "low" level after 5.2 μSec at the moment when the horizontal synchronization signal CS changes from the "low" level to the "high" level. Generates an output signal OUT that changes from a "low" level to a "high" level.

The positive edge detection stage 40 inputs an inverted signal of the output signal OUT, which is the output signal P16 of the NAND gate ND6, to input the inverter when the output signal P16 changes from a high level to a low level. By using the gate delay time of (13-17), the gate delay time is changed from the "high" level to the "low" level by the gate delay time, when the output P16 of the NAND gate ND6 is high level. The output of the inverter I2 becomes the "low" level, is applied to the inverter I3, and becomes the one input of the NAND gate ND7, and the signal input to the inverter I3 passes through the inverters I4-I7. Since the NAND gate ND7 becomes a type force, the output signal P17 of the NAND gate ND7 becomes a "high" level, so that one input of the NAND gate ND2 in the reset control signal generating means 10 do.

In this state, the instant when the output signal P16 of the NAND gate ND6 changes to the "low" level, the output of the inverter I2 becomes the "high" level, and this "high" level signal becomes the inverter I3 ,. While passing through I7), both inputs of the NAND gate ND7 are at the "high" level, and the output signal P17 is changed to the low level. When the output of the inverter I7 is at the "low" level, the NAND gate ND7 is input. Output signal P17 is changed from the low level to the high level. This output signal P17 becomes one input of the NAND gate ND2 of the reset control signal generating means 10.

This operation is repeated on the basis of the horizontal synchronization signal so that the level is changed from the "low" level to the "high" level at 5.2μSec and 62.8μSec, respectively, based on the moment when the horizontal synchronization signal changes from the low level to the high level. You can create a gate signal that changes to the "low" level at.

The present invention, which operates as described above, is composed of only digital elements, which enables high integration and reduces the use of external components to prevent malfunctions, thereby reducing the overall configuration of the image color signal processing system. There is an advantage that the reliability is improved.

Claims (4)

Reset control signal generating means 10 for generating the reset control signal P1 according to the positive edge detection signal P17 applied with the mixed synchronization signal CS as an input, and the oscillation signal VCO. A counter means 20 for outputting signals P11, P12 and P13 of a predetermined frequency in accordance with the output signal P1 of the reset control signal generating means as the input clock signal CK, The gate signal generating means 30 and the gate for generating signals OUT and P16 having a pulse width of a predetermined time at regular intervals based on the horizontal synchronization signal according to the output signals P11, P12, and P13 of (20). A gate signal generation circuit for noise removal in a horizontal synchronizing period comprising a positive edge detection means (40) for detecting a positive edge by inputting an output signal (P16) of the signal generation means (30). 2. The inverter according to claim 1, wherein the reset control signal generating means (10) inverts the mixed synchronous signal (CS), the NAND gate (ND1) using the output of the inverter (I1) as one input, and the A gate signal generation circuit for removing noise during a horizontal synchronization period comprising a NAND gate (ND2) whose output signal (P17) of the positive edge detection means (40) is one input. 2. The horizontal synchronization period as set forth in claim 1, wherein the counter means (20) comprises a T flip-flop (TFF1, TFF2), a D flip-flop (DFF1-DFF7), and an AND gate (AD1-AD4) to output a signal of a predetermined frequency. Gate signal generation circuit for noise reduction. The NAND gate of claim 1, wherein the gate signal generating means 30 is connected to the AND gates AD2-AD4 of the counter means 20, and outputs a gate signal having a pulse width of a predetermined time. A gate signal generation circuit for noise removal during the horizontal synchronization period consisting of ND6).