KR940002691A

KR940002691A - Adaptive input scanning method

Info

Publication number: KR940002691A
Application number: KR1019920012170A
Authority: KR
Inventors: 노경태
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1992-07-08
Filing date: 1992-07-08
Publication date: 1994-02-19
Also published as: KR940009744B1

Abstract

본 발명은 논리입력을 스캐닝 하는 방법에 관한 것으로서, 특히, 불안정한 논리 입력을 안정된 논리로 변환시켜 스캐닝하는 적응형 입력 스캐닝 방법에 관한 것이다.The present invention relates to a method for scanning a logic input, and more particularly, to an adaptive input scanning method for scanning by converting an unstable logic input into a stable logic.

본 발명은, 논리 입력을 샘플링 하여 레지스터에 시프트(shift)하여 시프트된 비트의 상태를 점검하는 제1 단계(40,41)와, 상기 제1 단계(40,41) 수행후, 모든 비트가 0이면, 바로 전의 입력상태가 논리적으로 '하이(H)'일 경우는 입력논리는 '로우' 상태로 파악하고 하강에지가 발생된 것으로 처리하고, 바로 전의 입력상태가 논리적으로 '하이(H)'가 아닐 경우는 현재의 논리 상태로 입력논리를 파악하고 제2 단계(42,43)와, 상기 제1 단계(40,41) 수행후, 모든 비트가 1이면, 바로 전의 입력상태가 논리적으로 '로우(L)'일 경우는 입력논리를 '하이' 상태로 파악하고 상승에지가 발생된 것으로 처리하고, 바로 전의 입력상태가 논리적으로 '로우(L)'가 아닐 경우는 현재의 논리 상태로 입력논리를 파악하는 제3 단계(44,45)와, 상기 제1 단계(40,41) 수행후, 비트가 0과 1 이 혼재된 경우는 현재의 논리 상태로 입력논리를 파악하는 제4 단계를 구비한다.According to the present invention, a first step (40, 41) of sampling a logic input and shifting to a register to check the state of the shifted bit, and after performing the first step (40, 41), all bits are zero. If the previous input state is logically 'high', the input logic is regarded as 'low' and the falling edge is generated, and the previous input state is logically 'high'. If not, the input logic is determined according to the current logic state, and if all bits are 1 after the second steps 42 and 43 and the first steps 40 and 41 are performed, the previous input state is logically ' Low (L) ', the input logic is regarded as' high' state and treated as rising edge. If the previous input state is not logically 'low', the current logic state is entered. After the third steps 44 and 45 of grasping the logic and the first steps 40 and 41 are performed, bits 0 and 1 are mixed. Case has a fourth step of identifying the input logic to the current logic state.

Description

Adaptive input scanning method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 6 도는 중앙제어부의 전체 제어방법에 따른 처리절차의 개략적인 흐름도.6 is a schematic flowchart of a processing procedure according to the overall control method of the central control unit.

제 7 도는 본 발명에 따른 논리검출방법의 세부 흐름도.7 is a detailed flowchart of a logic detection method according to the present invention.

제 8 도는 본 발명에 따른 작용을 세부적으로 나타내기 위한 신호 파형도.8 is a signal waveform diagram for showing in detail the operation according to the present invention.

Claims

Logical input applied to an apparatus having a signal generating means (1) for generating a logic input signal and a central control means (3) connected to the signal generating means (1) for removing chattering and scanning the logical input signal. In the scanning method, if a logic input is sampled and shifted to a register to check the state of the shifted bits, and after performing the first steps 40 and 41, if all bits are zero, In case the previous input state is logically 'high', the input logic is regarded as 'low' state and treated as falling edge, and the previous input state is logically 'high'. If not, the low logic (L) is used to identify the input logic as the current logic state. If the input logic is considered high, the rising edge is treated as if a rising edge is generated. (L) 'if not the current logic A third step (44,45) of grasping the input logic as a state, and a case in which bits 0 and 1 are mixed after performing the first step (40,41), the input logic is grasping the current logic state. Adaptive input scanning method characterized in that performed by having four steps.

※ Note: The disclosure is based on the initial application.