KR940001732U - 데이타 입출력장치의 엑세스 시간 제어회로 - Google Patents

데이타 입출력장치의 엑세스 시간 제어회로

Info

Publication number
KR940001732U
KR940001732U KR2019920009728U KR920009728U KR940001732U KR 940001732 U KR940001732 U KR 940001732U KR 2019920009728 U KR2019920009728 U KR 2019920009728U KR 920009728 U KR920009728 U KR 920009728U KR 940001732 U KR940001732 U KR 940001732U
Authority
KR
South Korea
Prior art keywords
control circuit
output device
data input
time control
access time
Prior art date
Application number
KR2019920009728U
Other languages
English (en)
Other versions
KR970007156Y1 (ko
Inventor
이쌍수
Original Assignee
Lg전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg전자 주식회사 filed Critical Lg전자 주식회사
Priority to KR92009728U priority Critical patent/KR970007156Y1/ko
Publication of KR940001732U publication Critical patent/KR940001732U/ko
Application granted granted Critical
Publication of KR970007156Y1 publication Critical patent/KR970007156Y1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
KR92009728U 1992-06-02 1992-06-02 데이타 입출력장치의 엑세스 시간 제어회로 KR970007156Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92009728U KR970007156Y1 (ko) 1992-06-02 1992-06-02 데이타 입출력장치의 엑세스 시간 제어회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92009728U KR970007156Y1 (ko) 1992-06-02 1992-06-02 데이타 입출력장치의 엑세스 시간 제어회로

Publications (2)

Publication Number Publication Date
KR940001732U true KR940001732U (ko) 1994-01-03
KR970007156Y1 KR970007156Y1 (ko) 1997-07-19

Family

ID=19334212

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92009728U KR970007156Y1 (ko) 1992-06-02 1992-06-02 데이타 입출력장치의 엑세스 시간 제어회로

Country Status (1)

Country Link
KR (1) KR970007156Y1 (ko)

Also Published As

Publication number Publication date
KR970007156Y1 (ko) 1997-07-19

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