KR940000464B1

KR940000464B1 - Improved definition tv

Info

Publication number: KR940000464B1
Application number: KR1019880004805A
Authority: KR
Inventors: 조현덕
Original assignee: 삼성전자 주식회사; 안시환
Priority date: 1988-04-27
Filing date: 1988-04-27
Publication date: 1994-01-21
Also published as: KR890016848A

Abstract

The ID television by using a motion compensator includes means for digitally converting video signal and sending the converted signal to an even/odd field memory, means for 1V-delaying the output of the even/odd field memory, adding it to a previous signal, and amplifying the added signal into half, means for low-pass filtering and amplifying the output of the even/odd field memory, means for subtracting the output of the even/odd field memory and the previous signal and level-quantizing the output signal, and means for outputting the outputs of two mixers according to the operation of a selection switching circuit, thereby preventing noise.

Description

ID-TV using motion compensation circuit

제1도는 본 발명의 블럭도.1 is a block diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

101 : A/D 변환회로 102, 116, 117, 121, 122 : 버퍼101: A / D conversion circuit 102, 116, 117, 121, 122: buffer

103, 115, 120, 124, 128 : 선택 스위칭 회로103, 115, 120, 124, 128: selective switching circuit

104 : 짝수필드메모리 107 : 홀수필드메모리104: Even field memory 107: Odd field memory

105, 106 : 감산비교기 108, 112 : 1 수직지연 회로105, 106: Subtraction comparator 108, 112: 1 vertical delay circuit

111, 119 : 저역여파기 109, 113 : 가산기111, 119: Low filter 109, 113: Adder

110, 114 :

승산증폭기 118, 123 : 혼합기110, 114:

Multiplier amplifiers 118, 123: Mixers

125 : 고립점제거기 126 : 레벨양자화기125: isolation point remover 126: level quantizer

127 : 절대치기127: absolute stroke

본 발명은 ID-TV(Improved Definition Television)에 관한것으로 정지부화상에 대해서는 필드(Field)간 보완을 하고 운동부화상에 대해서는 필드네 보완을 하여 엘리어싱(Aliasing)을 최소화시킨 운동보상회로를 이용한 ID-TV에 관한 것이다.The present invention relates to an ID-TV (Improved Definition Television), which complements a field for a stationary image and complements a field for an image of an athletic image, thereby minimizing aliasing. It's about TV.

종래의 ID-TV는 운동부화상과 정지부화상을 구분하여 처리하지 않고 일반적인 저역여파기를 사용하여 필드내 보완만하여 화상을 보상하였으므로 운동부신호의 오차가 잡음신호에 의하여 화상의 열화가 심한 문제점이 있었다.In the conventional ID-TV, the image compensation is performed only by complementing the field using a general low pass filter without processing the moving part image and the stationary image separately. Therefore, the error of the moving part signal is severely degraded due to the noise signal. .

본 발명은 상기와같은 문제점을 해결하기 위하여 창안한 것인바, 기존의 비월주사 방식의 525라인을 2 : 1로 인터페이스 하던것을 순차주사 방식으로 바꾸어 525라인으로 처리한것으로 이와같이 하여 화상의 명멸현상(Flicker)을 최소화할 수 있을뿐만 아니라 동영역과 정지영역을 구분하여 동영역일때는 필드내 보완을 하고 정지영역일때는 필드간 보완을 해주어 화상의 질을 높이는데 그 목적이 있는것으로 이하 첨부된 도면에 의하여 본 발명을 상세히 설명하면 다음과같다.The present invention has been devised to solve the above problems, the existing interlaced scanning method of the 525 lines of 2: 1 interface was changed to the sequential scanning method to process the 525 lines in this way flickering image (Flicker In addition to minimizing), the dynamic and still areas can be distinguished to complement the field in the case of the moving area and to complement the field in the case of the stationary area. By the present invention will be described in detail as follows.

제1도는 본 발명의 블럭도로서 아날로그 영상신호를 디지탈신호로 변환시키는 A/D 변환회로(101)는 증록작용을 하는 버퍼(102)를 통하여 신호를 선택하고 60HZ의 클럭으로 동작하는 선택스위칭회로(103)에 접속시키고 상기 선택스위칭회로(103)는 짝수/홀수(EVen/odd), 필드메모리(104)(107)와 감산비교기(105)(106)를 거쳐 60HZ의 클럭으로 동작하는 선택스위칭회로(128)에 접속시킴과 아울러 1수직지연회로(108)와 가산기(109)및

승산증폭기(110)를 통하여 정지영역을 감지하도록하고 31.5KHZ의 클럭으로 동작하는 선택스위칭 회로(120)에 각각 접속시킨다.1 is a block diagram of the present invention, an A / D conversion circuit 101 for converting an analog video signal into a digital signal selects a signal through a buffer 102 that performs a write operation, and selects a switching circuit operating with a clock of 60 Hz. A select switching circuit 103 is connected to (103), and the select switching circuit 103 is operated with a clock of 60HZ through an even / odd (EVen / odd) field memory (104) (107) and a subtractive comparator (105) (106). One vertical delay circuit 108, an adder 109,

The multiplier amplifier 110 senses the still area and connects to the selection switching circuit 120 operating with a clock of 31.5 KHZ, respectively.

상기 짝수/홀수 필드메모리(104)(107)에 각각 접속된 저역여파기(111)와 1수직지연회로(112)는 동영역을 감지하도록하여 버퍼(117)를 거쳐 혼합기(118)에 접속시키고 가산기(113)와

승산증폭기(114) 및 31.5KHZ의 클럭으로 동작하는 스위칭회로(115)와 버퍼(116)를 통하여 상기 혼합기(118)에 접속시키며 또한 상기 짝수필드메모리(107)에 접속된 저역여파기(119)와 스위칭회로(120)는 각각 버퍼(122)(121)를 거쳐 혼합기(123)에 접속시킨다.The low pass filter 111 and the 1 vertical delay circuit 112 respectively connected to the even /

odd field memories

104 and 107 are connected to the mixer 118 via a buffer 117 to sense the same area. With 113

A low pass filter 119 connected to the mixer 118 through a switching circuit 115 and a buffer 116 operating at a multiplier amplifier 114 and a clock of 31.5 KHZ and also connected to the even field memory 107. The switching circuit 120 is connected to the mixer 123 via buffers 122 and 121, respectively.

한편 상기 스위칭회로(128)에 접속된 절대치기(127)는 레벨양자화기(126)와 저역여파기로 구성된 고립점(에러) 제거기(125)를 통하여 상기 혼합기(118)(123)에 각각 접속시키며 상기 혼합기(118)(123)는 60HZ의 클럭으로 동작하는 선택스위칭회로(124)를 통하여 출력신호를 내보내도록 접속시킨다.On the other hand, the absolute stroke 127 connected to the switching circuit 128 is connected to the mixers 118 and 123 through an isolation point (error) remover 125 composed of a level quantizer 126 and a low pass filter. The mixers 118 and 123 are connected to output an output signal through a selection switching circuit 124 operating with a clock of 60 Hz.

이하 이들의 작용효과를 설명한다.The effect of these will be described below.

제1도의 A/D변환기(101)에 아날로그 영상신호가 입력되면 디지탈신호로 바뀌어 버퍼(102)를 통하여 증폭된후 선택스위칭 회로(103)에 인가되며 이 선택 스위칭회로(103)에 입력된 신호가 짝수필드신호 일때는 짝수필드메모리(104)로 신호가 인가되고 홀수필드신호 일때는 홀수필드메모리(107)에 신호가 인가된다. 상기 짝수필드메모리(104)에 입력된 신호는 1수직지연회로(108)를 거친 신호가 거치지 않은 신호와 가산기(109)에서 가산된후

승산증폭기(110)를 통하여 진폭(Amplitude)이 반감된후 선택스위칭회로(120)에 인가된다.When an analog video signal is inputted to the A / D converter 101 of FIG. 1, the analog image signal is converted into a digital signal, amplified through the buffer 102, and then applied to the selection switching circuit 103 and input to the selection switching circuit 103. When is an even field signal, a signal is applied to the even field memory 104, and when it is an odd field signal, a signal is applied to the odd field memory 107. The signal input to the even field memory 104 is added by the adder 109 and the signal which has not passed through the signal passing through the 1 vertical delay circuit 108.

Amplitude is halved through the multiplier amplifier 110 and then applied to the selection switching circuit 120.

상기 짝수필드메모리(104)를 통과한 신호는 통과전신호와 감산비교기(105)에서 비교된후 그 차신호가 선택스위칭회로(128)에 인가된다.The signal passing through the even-field memory 104 is compared with the pre-pass signal in the subtraction comparator 105 and the difference signal is applied to the selection switching circuit 128.

한편 상기 홀스필드메모리(107)에 입력된 출력신호가 전신호와 감산비교기(106)에서 비교된후 차신호는 상기 선택스위칭회로(128)에 인가됨과 동시에 상기 선택스위칭회로(120) 및 1수직지연회로(112)에 인가되며 상기 선택스위칭회로(120)에 입력된 두 신호는 31.5KHZ의 주기로 번갈아가며 각 신호를 선택하여 받아들이게 되어 이 신호는 버퍼(121)를 통하여 혼합기(123)에 입력되는데 이렇게해서 구성된 신호는 일반 TV의 수평주파수보다 2배가 되므로 수평주파수가 31.5KHZ이고 수평주사선수가 525라인 순차주사신호가 된다.On the other hand, after the output signal inputted to the horsefield memory 107 is compared with all signals and the subtraction comparator 106, the difference signal is applied to the selection switching circuit 128 and at the same time the selection switching circuit 120 and one vertical line. The two signals that are applied to the delay circuit 112 and input to the selection switching circuit 120 alternately receive and select each signal at a cycle of 31.5 KHZ, and the signals are input to the mixer 123 through the buffer 121. The signal composed in this way is twice the horizontal frequency of a normal TV, so the horizontal frequency is 31.5KHZ and the horizontal scan player is a 525-line sequential scan signal.

즉 262 라인의 홀수필드가 수평주사선수가 525라인 프레임화된 두배의 정보량으로 증가된다.In other words, an odd field of 262 lines is increased by twice the amount of information framed by a 525 lines of horizontal scan athletes.

상기 홀수필드메모리(107)의 출력신호는 저역여파기(119)를 거쳐서 버퍼(122)를 통해 상기 혼합기(123)에 인가됨과 동시에 1수직지연회로(112)를 통한 신호와 함께 가산기(113)에서 합해진 후

승산증폭기(114)를 거쳐 선택스위칭회로(115)에 인가된다.The output signal of the odd field memory 107 is applied to the mixer 123 through the buffer 122 via the low pass filter 119 and at the same time in the adder 113 together with the signal through the one vertical delay circuit 112. After combined

The multiplier amplifier 114 is applied to the selection switching circuit 115.

상기 혼합기(123)는 운동보상기에 의해 제어를 받아 정지신호인 경우에는 상기 버퍼(121)를 통한신호를, 동신호인 경우에는 상기 버퍼(122)를 통한신호를 받는다.The mixer 123 receives a signal through the buffer 121 when the stop signal is controlled by the motion compensator and a signal through the buffer 122 when the motion signal is the same.

이렇게 혼합기(123)에서 출력된 신호는 선택 스위칭회로(124)에 인가되며 상기 선택스위치 회로(124)에 인가되며 상기 선택스위칭회로(124)에 인가되는 다른 신호는 상기 스위칭 선택회로(120)에 처리된 방법과 같은 방법으로 상기 선택스위칭회로(115)와 버퍼(116) 혼합기(118)를 통하여 입력되는데 단지 차이점은 상기 처리는 홀수필드로 홀수 프레임화 시킨것이고, 이번처리는 짝수필드를 짝수프레임화 시킨것이다.The signal output from the mixer 123 is applied to the selection switching circuit 124, the other signal is applied to the selection switch circuit 124, and the other signal applied to the selection switching circuit 124. It is input through the selection switching circuit 115 and the buffer 116 mixer 118 in the same manner as the processed method. The only difference is that the processing is odd-framed into odd fields, and this process is even-numbered frames. It is mad.

상기 선택스위칭회로(124)는 상기 혼합기(118)(123)의 출력신호를 60HZ의 주기로 선택하여 출력하는데 이는 짝수프레임화된 짝수필드와 홀수 프레임화된 홀수필드의 정보가 교대로 각각 30HZ의 주파수로 입력되기 때문에 결국은 60HZ의 주기로 선택하여 출력하는 것이다.The selection switching circuit 124 selects and outputs the output signals of the mixers 118 and 123 at a period of 60 HZ, in which information of an even-framed even field and an odd-framed odd field is alternately 30HZ, respectively. In the end, it is selected and output in the period of 60HZ.

한편 상기 선택스위칭회로(128)는 상기 짝수/홀수 필드메모리(104)(107)와 감산비교기(105)(106)를 거쳐서 입력된 두신호를 짝수일때는 짝수쪽으로 홀수일때는 홀수쪽으로 선택하여 출력시키며 이 출력신호는 절대치기(127)를 거치면서 양의 값을 갖는 신호가 되고 레벨양자화기(126)를 통하여 레벨이 8이 넘으면 모두 "1"의 신호가 되어 고립점 제거기(125)를 거쳐 상기 혼합기(118)(123)를 제어하게 된다.On the other hand, the selection switching circuit 128 outputs the even / odd field memory 104, 107 and the subtractor comparator 105, 106 by inputting the two signals evenly to the odd side and to the odd side to the odd side. The output signal is a signal having a positive value through the absolute stroke 127, and if the level is greater than 8 through the level quantizer 126, all the signals become "1" and go through the isolation point remover 125. The mixers 118 and 123 are controlled.

이상에서 설명한 바와같이 본 발명은 종래의 비월주사 방식을 순차주사 방식화 함으로써 화상의 명멸현상을 최소화하였으며 동영역과 정지영역을 구분하여 처리를 함으로써 잡음현상을 방지하고 화질을 향상시키는 효과가 있는것이다.As described above, the present invention minimizes the flickering of images by sequential scanning method of the conventional interlaced scanning method, and has the effect of preventing noise phenomenon and improving image quality by processing the moving and still areas separately. .

Claims

An apparatus for processing a video signal, comprising: means for digitally converting an input video signal, amplifying the same, and inputting it into an even / odd field memory, and adding an output signal of the even / odd field memory by one vertical delay to all signals;

Means for connecting to another selective switching circuit after multiplying amplification; means for low-pass filtering the output signal of the even / odd field memory and connecting it to the two mixers after amplification or connecting to the selective switching circuit; Means for removing the two mixers by eliminating the error by subtracting the output signal and all the signals and quantizing the output signal according to the operation of the selection switching circuit to level quantization; and selecting the output signals of the two mixers. ID-TV using a motion compensation circuit, characterized in that consisting of means for outputting according to the operation of the switching circuit.

The signal passing through the even field memory 104 is added by the one vertical delayed signal and the adder 109.

ID-TV using a motion compensation circuit, characterized in that the multiplied amplification means for detecting the still area, and means for detecting the same area using the low-pass filter (111).

The output signal of the odd field memory 107 is equal to the adder 109.

ID-TV using a motion compensation circuit, characterized in that the signal is passed through the multiplier amplifier 110 and selected by the selection switching circuit 120.

The mixer 118, 123 is controlled by the motion compensator receives a signal through the selection switching circuit 115, 120 or low-pass filter in accordance with the stop signal and the case of the same signal. ID-TV using the exercise compensation circuit, characterized in that to receive a total signal.