KR940000154B1 - Planerizing method of inter metal layer for semiconductor device - Google Patents

Planerizing method of inter metal layer for semiconductor device Download PDF

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KR940000154B1
KR940000154B1 KR1019900012464A KR900012464A KR940000154B1 KR 940000154 B1 KR940000154 B1 KR 940000154B1 KR 1019900012464 A KR1019900012464 A KR 1019900012464A KR 900012464 A KR900012464 A KR 900012464A KR 940000154 B1 KR940000154 B1 KR 940000154B1
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metal
layer
medium
mask
etching
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KR920005348A (en
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정양희
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

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Abstract

(A) forming a metal layer for inhibiting it from etching, mediating metal, and a metal mask layer (4) sequentially after the formation of a buried metal (1) on the fixed area of the substrate, (B) spreading a photoresist film and patterning photoresist film (5) on the buried metal, (C) 1st etching the mask layer of mediating metal (4) and mediating metal (3) by using the patterned photoresist film and removing photoresist film, (D) evaporating a photoresist film on the whole surface and forming a micro-pattern on the top of the mediating buried metal (1) and removing exposed metal layer (2) for inhibiting it from etching, (E) forming an insulating layer (7) on the whole area, spreading photoresist film (8) over the insulating layer, and leveling the insulating layer (7), (F) removing the mask layer (4), and (G) evaporating the 2nd metal (9) on the whole surface of resulting material and patterning it for connection with mediating material.

Description

반도체 소자의 금속층간 평탄화 방법Planarization method between metal layers of semiconductor device

제1도는 종래의 공정을 나타낸 단면도.1 is a cross-sectional view showing a conventional process.

제2도는 본 발명의 공정을 나타낸 단면도.2 is a sectional view showing a process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 하층금속 2 : 식각저지용 금속1: lower layer metal 2: etch stop metal

3 : 매개물금속 4 : 질화막3: medium metal 4: nitride film

5,6,8,11 : 감광제 7,10 : 절연막5,6,8,11 photosensitive agent 7,10 insulating film

9 : 상층금속9: upper layer metal

본 발명은 반도체 소자의 금속층간 평탄화 방법에 관한 것으로, 특히 소자가 고집적화됨에 따른 금속층간의 심한 굴곡현상을 매개물(Pillar)을 이용하여 평탄화시키기 위한 반도체 소자의 금속층간 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method between metal layers of a semiconductor device, and more particularly, to a planarization method between metal layers of a semiconductor device for planarizing a severe bending phenomenon between metal layers as a device is highly integrated using a pillar.

종래 반도체 소자의 금속층간의 접합방법은 제1도(a)에 도시된 바와 같이 기판의 소정부분에 제1금속(1)을 형성한후, 후속공정에서 형성될 제2금속과 격리시키기 위해 (b)와 같이 절연막(10)을 형성한다.In the conventional method of bonding between metal layers of a semiconductor device, as shown in FIG. 1 (a), a first metal 1 is formed on a predetermined portion of a substrate and then separated from the second metal to be formed in a subsequent process ( As shown in b), the insulating film 10 is formed.

이어서, 제1금속(1)과 제2의 금속을 접합시키기 위한 접합홀(Hole)을 형성하기 위해 감광제(5)를 사용하여 제2금속층을 형성할 부분의 감광제를 선택적으로 식각한다.Subsequently, in order to form a bonding hole (Hole) for joining the first metal 1 and the second metal, the photosensitive agent 5 is selectively etched using the photosensitive agent 5 to form the second metal layer.

다음에 (c)와 같이 상기 감광제(5)를 마스크로 하여 절연막(10)을 건식식각한후 (d)와 같이 제2금속(9)을 증착하고 다시 감광제(6)를 사용하여 제1금속(1)과 제2금속(9)이 연결될수 있도록 한후 (e)와 같이 제2금속(9)을 형성하였다.Next, dry etching the insulating film 10 using the photosensitive agent 5 as a mask as shown in (c), and depositing the second metal 9 as shown in (d), and using the photosensitive agent 6 again, using the first metal. After (1) and the second metal (9) can be connected to form a second metal (9) as shown in (e).

그러나 상기와 같은 종래기술에 있어서는 제1금속(1)과 제2금속(9)을 접합시키기 위하여 접합홀을 형성하고 이 접합홀에 금속을 채워야 하기 때문에 금속을 균일하게 형성하기 어려웠고, 이에 따른 반도체 소자 표면의 심한 굴곡으로 인하여 제품의 신뢰성이 저하되는 결점이 있었다.However, in the prior art as described above, it is difficult to uniformly form a metal because a junction hole must be formed in order to join the first metal 1 and the second metal 9 and the metal must be filled in the junction hole. Due to the severe bending of the device surface, there was a defect that the reliability of the product is reduced.

본 발명은 이와 같은 종래기술의 결점을 해결하기 위한 것으로, 이와 같은 목적을 달성하기 위한 본 발명을 금속층간에 매개물을 형성하여 금속층간의 글곡현상을 완화시키고 평탄화시키는데 그 목적이 있다.The present invention is to solve the drawbacks of the prior art, the present invention for achieving the above object is to form a medium between the metal layer to mitigate and planarize the phenomenon of the phenomenon between the metal layer.

먼저 제2도는 본 발명의 반도체 소자의 금속층간 평탄화 공정단면도로서, 제2도(a)와 같이 반도체기판의 소정부분에 하층금속(1)을 형성하고, 상기 결과물 전면에 식각저지 역할을 할수 있는 타이타늄(Ti) 혹은 타이텅스텐(TiW)등의 식각저지용 금속(2)을 증착한다.First, Figure 2 is a cross-sectional planarization process between the metal layer of the semiconductor device of the present invention, as shown in Figure 2 (a) to form a lower layer metal (1) on a predetermined portion of the semiconductor substrate, it can act as an etch stop on the entire surface Etch-stopping metals 2 such as titanium (Ti) and titanium tungsten (TiW) are deposited.

그리고 식각저지용금속(2) 위에 알루미늄 등의 매개물 금속(3)을 증착한다.Then, the intermediate metal 3 such as aluminum is deposited on the etch stop metal 2.

여기서, 매개물 금속(3)은 하층금속(1)과 차후에 형성할 상층금속간의 전도적 역할을 하며, 상하금속층간의 굴곡을 완화시키는 평탄화 역할을 하기 위한 것이다.Here, the intermediate metal 3 serves to conduct a conductive role between the lower layer metal 1 and the upper metal layer to be formed later, and to serve as a planarization role to alleviate the bending between the upper and lower metal layers.

이어서 상기 매개물 금속(3) 위에 상기 매개물금속의 마스크 역할을 할수 있는 물질로서 매개물 금속(3)보다 식각 선택비가 높은 질화막(4)(혹은 산화막)을 증착한다.Subsequently, a nitride film 4 (or an oxide film) having a higher etching selectivity than that of the intermediate metal 3 is deposited as a material capable of acting as a mask of the intermediate metal on the intermediate metal 3.

이후 질화막(4) 위에 감광제(5)를 도포, 감광, 현상하여 하층금속(1) 상부영역에 매개물 금속 마스크 영역을 정의한 다음 제2도(b)와 같이 상기 정의된 감광제(5)를 마스크로 하여 질화막(4)과 매개물금속(3)을 1차 건식식각한후 감광제(5)를 제거한다.Thereafter, the photoresist 5 is applied, photosensitive, and developed on the nitride film 4 to define the intermediate metal mask region in the upper region of the lower layer metal 1, and then, using the photoresist 5 defined above as a mask as shown in FIG. After the first dry etching of the nitride film (4) and the medium metal (3) to remove the photosensitive agent (5).

이때, 상기 식각저지용 금속(2)으로서 증각된 타이타늄, 타이텅스텐에 의해 상기 건식식각시 매개물 금속(3)까지 식각이 행해지고 그 이하로는 식각이 행해지지 않게 된다.At this time, etching is performed to the intermediate metal 3 during the dry etching by titanium and titanium tungsten, which are augmented as the etching preventing metal 2, and etching is not performed thereafter.

다음에 제2도(c)와 같이 감광제(6)를 상기 결과물 전면에 도포한 다음 제2도(d)에 도시한 바와 같이 감광제 역상법(Image reversal)을 이용하여 매개물 금속(3)이 하측금속(1) 상부에서 정확히 남도록 매개물이 정의하는 미세패턴을 형성한후 제2도(e)와 같이 상기 미세 패터닝된 감광제(6)을 마스크로 하여 질화막(4)을 건식식각하고 상기 선택적으로 식각된 매개물금속(3)을 마스크로 이용하여 식각저지용 금속(2)을 선택적으로 건식식각한 다음, 감광제(6)를 제거한다.Next, the photosensitive agent 6 is applied to the entire surface of the resultant product as shown in FIG. 2 (c), and then the intermediate metal 3 is lowered by using the photoresist image reversal as shown in FIG. 2 (d). After forming a fine pattern defined by the medium so as to remain exactly on the metal (1), dry etching the nitride film (4) using the fine patterned photosensitive agent (6) as a mask as shown in Figure 2 (e) and selectively etching The etch stop metal (2) is selectively dry etched using the prepared intermediate metal (3) as a mask, and then the photosensitive agent (6) is removed.

이어서 제2도(f)와 같이 상기 질화막(4)을 마스크로 하여 그 하부의 매개물금속(3)을 2차 식각하여 하층금속(1)층에서 얼라인 먼트(aligu ment)되도록 매개물을 형성한다.Subsequently, as shown in FIG. 2 (f), the intermediate metal 3 under the lower portion of the intermediate metal 3 is etched using the nitride film 4 as a mask to form an alignment in the lower metal 1 layer. .

이때 상기와 같이 사진식각공정을 2회에 걸쳐 매개물금속(3)을 패터닝함은 고집적 소자에 알맞은 미세패턴의 매개물을 형성하기 위함이다.In this case, the medium metal 3 is patterned twice in the photolithography process as described above to form a medium having a fine pattern suitable for a highly integrated device.

제2도(g)와 같이 결과물 전면에 절연막(7)을 형성하고 그 위에 감광제(8)을 도포한다.As shown in FIG. 2 (g), an insulating film 7 is formed on the entire surface of the resultant, and a photosensitive agent 8 is applied thereon.

이어서 제2도(h)와 같이 상기 매개물까지만 돌출되도록 절연막(7)과 감광제(8)을 에치백 공정하여 상기 절연막(7)을 평탄화시키고 제2도(i)와 같이 상기 매개물 마스크층인 질화막(4)을 제거한 다음, 결과물 전면에 상층 금속(9)을 증착하여 이 상층금속(9)이 상기 매개물을 통하여 하층금속(1)과 연결되도록 한후, 감광제(11)를 도포하고 상기 매개물 금속(3)을 1차 식각하기 위해 사용한 마스크를 사용하여 노광 및 현상한 다음(j)와 같이 상기 현상된 감광제(11)를 마스크로 이용 상층금속(9)을 건식식각하여 하층금속과 식각 저지용 금속 및 매개물 금속(3)을 통해 연결되도록 한다.Subsequently, the insulating film 7 and the photoresist 8 are etched back so as to protrude only to the medium as shown in FIG. 2 (h) to planarize the insulating film 7 and the nitride film as the medium mask layer as shown in FIG. (4) is removed, and then the upper layer metal 9 is deposited on the entire surface of the resultant so that the upper layer metal 9 is connected to the lower layer metal 1 through the medium, and then a photosensitive agent 11 is applied and the medium metal ( After exposure and development using a mask used for primary etching 3), the upper layer metal 9 is dry-etched using the developed photosensitive agent 11 as a mask as shown in (j), and the lower layer metal and the metal for etching And via the medium metal 3.

이상에서 설명한 바와 같은 본 발명의 반도체 소자의 금속층간의 평탄화 방법에 있어서는 매개물 금속을 이용함으로써 하층금속과 상층금속의 연결이 용이해지며, 매개물 금속으로 인해 상하 금속층간의 굴곡을 완화시켜 줌으로써 금속층간의 평탄화를 이룰수 있어 반도체 소자의 신뢰성을 증대시킬수 있고, 금속층간의 평탄화로 인해 상층금속을 균일하게 증착할수 있으며 상층금속의 식각에 있어서도 평탄화된 금속의 식각이라는 점에서 수율의 증대를 가져올수 있는 장점이 있다.In the planarization method between the metal layers of the semiconductor device of the present invention as described above, by using the intermediate metal, the connection between the lower metal and the upper metal is facilitated, and the bending between the upper and lower metal layers is alleviated due to the intermediate metal. It is possible to increase the reliability of the semiconductor device by flattening of the device, and evenly depositing the upper layer metal due to the planarization between the metal layers, and to increase the yield in that the etching of the flattened metal is also performed in the etching of the upper layer metal. There is this.

또한 하층금속상에 매개물 금속을 정확하게 형성한후, 이 매개물 금속상에 상층금속을 형성하게 되므로 매개물 금속으로 인하여 상층 금속의 패터닝시, 보다 정확한 패턴을 형성할수 있게 된다.In addition, since the intermediate metal is accurately formed on the lower metal, and the upper metal is formed on the intermediate metal, the pattern metal can form a more accurate pattern when the upper metal is patterned.

Claims (4)

기판위의 소정부분에 하층 금속(1)을 형성하고 결과물 전면에 식각저지 금속층(2)과 매개물 금속(3)과 매개물 금속 마스크층(4)을 차례로 형성하는 공정; 감고아제(5)를 도포하고 패턴마스크를 이용 하층금속(1) 상부영역에 남도록 감광, 현상하여 감광제(5)를 패터닝하는 공정; 상기 패터닝된 감광제(5)를 마스크로 이용하여 매개물 금속마스크층(4)과 매개물금속(3)을 1차 식각하고 감광제(5)를 제거하는 공정; 전면에 감광제(6)를 증착하는 감광제 역상법을 이용하여 매개물 하층금속(1) 상부에만 남도록 식각하여 미세패턴을 형성하고 노출된 상기 식각저지금속층(2)을 제거하는 공정; 상기 미세패턴닝된 매개물 마스크층(4)을 마스크로하여 매개물금속(3)을 2차 식각하여 매개물을 형성하는 공정; 결과물 전면에 절연막(7)을 형성하고 이 위에 감광제(8)를 도포한후 상기 매개물이 돌출되도록 절연막(7)을 평탄화하는 공정; 상기 매개물 마스크층(4)을 제거하는 공정; 결과물 전면에 제2금속(9)을 증착한후 상기 매개물에 연결되도록 소정패턴으로 패터닝하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 금속층간 평탄화방법.Forming a lower layer metal (1) on a predetermined portion on the substrate and sequentially forming an etch stop metal layer (2), an intermediate metal (3), and an intermediate metal mask layer (4) on the entire surface of the resultant; Applying a photosensitive agent (5) and photosensitive and developing the photosensitive agent (5) so as to remain in the upper region of the lower layer metal (1) using a pattern mask; First etching the intermediate metal mask layer (4) and the intermediate metal (3) by using the patterned photosensitive agent (5) as a mask and removing the photosensitive agent (5); Etching to leave only the upper portion of the medium underlayer metal (1) by using a photoresist reverse phase method of depositing a photosensitive agent (6) on the front surface to form a fine pattern and removing the exposed etch stop metal layer (2); Forming a medium by second etching the medium metal (3) using the fine patterned medium mask layer (4) as a mask; Forming an insulating film 7 on the entire surface of the resultant, applying a photosensitive agent 8 thereon, and then flattening the insulating film 7 to protrude the medium; Removing the intermediate mask layer (4); And depositing a second metal (9) on the entire surface of the resultant and patterning the second metal (9) into a predetermined pattern to be connected to the medium. 제1항에 있어서, 상기 식각저지금속층(2)으로 타이타늄이나 타이텅스텐을 사용함을 특징으로 하는 반도체 소자의 금속층간 평탄화 방법.The method of claim 1, wherein titanium or tungsten is used as the etch stop metal layer (2). 제1항에 있어서, 상기 매개물 금속(3)으로는 알루미늄을 증착시킴을 특징으로 하는 반도체 소자의 금속층간 평탄화 방법.A method according to claim 1, wherein aluminum is deposited as the intermediate metal (3). 제1항에 있어서, 상기 매개물 금속마스크층(4)으로는 산화막 혹은 질화막을 특징으로 하는 반도체 소자의 금속층간 평탄화 방법.The method of claim 1, wherein the intermediate metal mask layer (4) comprises an oxide film or a nitride film.
KR1019900012464A 1990-08-13 1990-08-13 Planerizing method of inter metal layer for semiconductor device KR940000154B1 (en)

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