KR930023936A

KR930023936A - Device for reducing bit error rate of recording data of compact disc

Info

Publication number: KR930023936A
Application number: KR1019920008213A
Authority: KR
Inventors: 진영철
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1992-05-15
Filing date: 1992-05-15
Publication date: 1993-12-21
Also published as: KR100286281B1

Abstract

본 발명은 콤팩트 디스크에 디지탈 데이타를 기록 및 재생함에 있어 그 비트 에러율(Bit Error Rate)을 감소시키기 위한 인코딩/디코딩 장치에 관한 것으로 종래에 오디오 데이타를 콤팩트 디스크에 기록하는 DIRC 기법을 콤팩트 디스크용 ROM에 적용하여 화상, 문자정보를 정밀하게 기록, 재생(화면표시)하기 위하여는 오디오용 디지탈 신호처리에 ROM용 디지탈 신호처리기를 추가해야되는 문제점을 해결하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding / decoding device for reducing the bit error rate in recording and reproducing digital data on a compact disc. In order to precisely record and reproduce (screen display) image and text information by applying to the above, it is to solve the problem of adding a digital signal processor for ROM to digital signal processing for audio.

본 발명은 디지탈 데이타를 콤팩트 디스크에 기록함에 있어 인코딩 포맷의 지연량을 가변시켜 에러 분산량을 증가시켜주고 디코딩시에는 기존의 포맷과 가변제어된 포맷의 디코딩을 선택적으로 실행시키므로 문자, 화상 데이타의 콤팩트 디스크 기록(재생)에 정밀을 기하고 디지탈 신호처리의 추가없이 데이타 처리가 가능하도록 한 것으로 콤팩트 디스크의 오디오, 화상, 문자 데이타 기록/재생장치에 적용한다.The present invention increases the error variance by varying the delay amount of the encoding format in recording digital data on a compact disc, and selectively decodes the existing format and the variable-controlled format in decoding the character and image data. The compact disc recording (playback) is precise and data processing is possible without the addition of digital signal processing. The compact disc audio / image and character data recording / reproducing apparatus is applied.

Description

Device for reducing bit error rate of recording data of compact disc

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 비트 에러율 감소장치의 인코더/디코더 회로도, 제4도는 본 발명의 비트 에러율 감소장치의 프레임 동기신호 타이밍도, 제5도는 인코딩할 정보의 예.3 is an encoder / decoder circuit diagram of the bit error rate reducing apparatus of the present invention, FIG. 4 is a frame synchronization signal timing diagram of the bit error rate reducing apparatus of the present invention, and FIG. 5 is an example of information to be encoded.

Claims

A variable delay / rearrangement circuit 11 for rearranging and rearranging the delay amount with respect to the input data to be encoded and a parity generating unit for adding Q and P parity to the variable delayed and rearranged data (12), a modulator 13 for parsing the delayed and rearranged data including parity, a recording unit 14 for recording the modulated data, and an EFM PLL unit for adjusting the bit synchronization to the recorded data. (15), a shift register 16 for storing the EFM PLL unit output data, and a first delay / rearrangement circuit 17A for inverse delay and rearrangement processing for the fixed delay amount processing at the time of encoding the shift output data. ) And a second delay / rearrangement circuit 17B for inverse delay and rearrangement for variable delay amount processing at the time of encoding shift output data, and an error correction unit for error correction of delay / rearrangement processing. 18 and the shift register A synchronization detector 19 for detecting frame synchronization signals corresponding to fixed and variable delay amounts from the data stored in the controller 16, and a timing controller 20 for controlling the delay and rearrangement processing timing based on the detected synchronization signals. And an inverter (21) for inverting the synchronous signal and supplying it to the second delay / rearrangement circuit (17B).

※ Note: The disclosure is based on the initial application.