KR930019018A

KR930019018A - Clock phase adjustment circuit

Info

Publication number: KR930019018A
Application number: KR1019920003181A
Authority: KR
Inventors: 여권
Original assignee: 강진구; 삼성전자 주식회사
Priority date: 1992-02-28
Filing date: 1992-02-28
Publication date: 1993-09-22
Also published as: KR950001567B1

Abstract

이 발명은 정확한 샘플링포인트가 요구되는 주파수 폴딩 기법을 응용한 영상신호처리 시스템에서 정확한 신호처리가 이루어질 수 있도록 한 것으로서, 영상신호의 디지탈 신호처리를 위하여 아날로그신호를 디지탈 신호로 변환시킬때 클럭위상 조정 및 기준신호 검출회로(20)를 구성시켜 정확한 포인트에서 데이타를 샘플링할 수 있게 하며, 어느 특정한 방식으로으 신호처리가 요구되어질때 미리 영상신호에 삽입되어진 특정패턴을 검출하여 기준신호(M1)및 처리모드 제어신호(M2),(M3)를 발생시켜 그에 다른 신호처리로의 전환이 가능케 함으로써, 잘못된 클럭위상을 조정하고 특별한 신호 처리방식에 대한 신호처리가 되도록 하여 시스템의 정확한 신호처리가 가능토록 한 것이다.The present invention allows accurate signal processing in a video signal processing system using a frequency folding technique that requires an accurate sampling point, and adjusts a clock phase when converting an analog signal into a digital signal for digital signal processing of a video signal. And a reference signal detecting circuit 20 to sample data at an accurate point, and when a signal processing is required in any specific manner, the specific signal inserted in the video signal is detected in advance so that the reference signal M1 and By generating the processing mode control signals M2 and M3 and switching to other signal processing, it is possible to adjust the wrong clock phase and make the signal processing for the special signal processing system so that the accurate signal processing of the system is possible. It is.

Description

Clock phase adjustment circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 이 발명에 따른 클럭위상 조정회로도.1 is a clock phase adjustment circuit diagram according to the present invention.

제2도는 이 발명에 다른 엔코더에서 삽입되는 인식패턴의 일예도.2 is an example of a recognition pattern inserted in an encoder according to the present invention.

제3도는 제1도의 클럭위상 조정 및 기준신호 검출회로의 상세 블럭도.3 is a detailed block diagram of the clock phase adjustment and reference signal detection circuit of FIG.

제4도는 제2도에 따른 제3도의 출력파형도.4 is an output waveform diagram of FIG. 3 according to FIG.

제5도는 인식패턴 샘플링메 따른 파형도이다.5 is a waveform diagram according to a recognition pattern sampling method.

Claims

An analog digital converter (ADC1) and an image signal processing circuit (10) are provided to convert a video signal into which a specific pattern is inserted during encoding and convert the signal into a digital signal, which is connected to the analog digital converter (ADC1) and clocked. (CLK) and the correlation detection control signal (LINE) in order to output a clock having the correct sampling point according to the inserted pattern when encoding, to adjust the clock phase by detecting the correlation of the pattern, and read the pattern to read the reference signal And a clock phase adjustment circuit and a reference signal detection circuit (20) for generating and causing the image signal processing circuit (10) to perform signal processing corresponding thereto.

According to claim 1, wherein the clock phase adjustment and reference signal detection circuit 20, according to the correlation detection control signal (LINE), the correlation detection unit 21 for outputting a peak value when the pattern inserted during encoding is correctly detected at decoding And the adjacent three pixels (A), (B), and (C) of the signals connected to the correlation detector 21 and output from the correlation detector 21, and the positive and negative threshold values Th1 and Th2. A comparator 22 for comparing the magnitudes of the signals and a positive peak connected to the comparator 22 to count a positive peak of the output of the comparator 22 to adjust a clock phase and output a clock down and clock up signal; The encoder 23 is connected to the comparator 22 and counts negative peaks of the output of the comparator 22 to generate a reference signal M1 and a processing mode control signal M2, M3. A negative peak coefficient unit 24 for outputting information of a signal processing method according to the inserted pattern, and A clock adjustment control unit 25 connected to the positive peak coefficient unit 23 to adjust the clock phase 1 when the clock down up signal of the positive peak coefficient unit 23 is input three or more times in succession; A clock phase control signal PCLK generated by the analog digital converter ADC1 according to the output of the clock adjustment control unit 25 so that the clock phase is matched to the clock adjustment unit 26. Clock phase adjustment circuit provided.

3. The clock phase adjustment circuit as set forth in claim 2, wherein said positive threshold (Th2) is a value slightly smaller than the maximum value of the positive peak.

3. The clock phase adjustment circuit as set forth in claim 2, wherein said negative threshold value (Th2) becomes a value slightly larger than the maximum value of the negative peak.

3. The relationship between the three positive pixels (A), (B), and (C) adjacent to a predetermined number of positive peaks output from the comparison unit 22 is A>. If the relationship between the three pixels (A), (B), (C) adjacent to a predetermined number or more of the positive peak output from the comparison unit 22 becomes A < Clock phase adjustment circuit for generating a signal.

The clock phase adjustment circuit according to claim 5, wherein the predetermined or more means 13 or more sides when the unit of the basic pattern is 28 bits when encoding.

3. The clock phase adjustment circuit as set forth in claim 2, wherein said negative peak coefficient section (24) counts negative peaks only when B among adjacent three pixels (A), (B), and (C) is smaller than a negative threshold.

The clock phase adjustment circuit according to claim 2, wherein the clock adjustment section (26) generates a plurality of clocks having different phases by using a plurality of delay elements and outputs them to a suitable clock by a clock phase control signal.

※ Note: The disclosure is based on the initial application.