KR930019018A - Clock phase adjustment circuit - Google Patents
Clock phase adjustment circuit Download PDFInfo
- Publication number
- KR930019018A KR930019018A KR1019920003181A KR920003181A KR930019018A KR 930019018 A KR930019018 A KR 930019018A KR 1019920003181 A KR1019920003181 A KR 1019920003181A KR 920003181 A KR920003181 A KR 920003181A KR 930019018 A KR930019018 A KR 930019018A
- Authority
- KR
- South Korea
- Prior art keywords
- clock phase
- signal
- clock
- phase adjustment
- output
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/12—Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
- Analogue/Digital Conversion (AREA)
- Picture Signal Circuits (AREA)
- Television Systems (AREA)
Abstract
이 발명은 정확한 샘플링포인트가 요구되는 주파수 폴딩 기법을 응용한 영상신호처리 시스템에서 정확한 신호처리가 이루어질 수 있도록 한 것으로서, 영상신호의 디지탈 신호처리를 위하여 아날로그신호를 디지탈 신호로 변환시킬때 클럭위상 조정 및 기준신호 검출회로(20)를 구성시켜 정확한 포인트에서 데이타를 샘플링할 수 있게 하며, 어느 특정한 방식으로으 신호처리가 요구되어질때 미리 영상신호에 삽입되어진 특정패턴을 검출하여 기준신호(M1)및 처리모드 제어신호(M2),(M3)를 발생시켜 그에 다른 신호처리로의 전환이 가능케 함으로써, 잘못된 클럭위상을 조정하고 특별한 신호 처리방식에 대한 신호처리가 되도록 하여 시스템의 정확한 신호처리가 가능토록 한 것이다.The present invention allows accurate signal processing in a video signal processing system using a frequency folding technique that requires an accurate sampling point, and adjusts a clock phase when converting an analog signal into a digital signal for digital signal processing of a video signal. And a reference signal detecting circuit 20 to sample data at an accurate point, and when a signal processing is required in any specific manner, the specific signal inserted in the video signal is detected in advance so that the reference signal M1 and By generating the processing mode control signals M2 and M3 and switching to other signal processing, it is possible to adjust the wrong clock phase and make the signal processing for the special signal processing system so that the accurate signal processing of the system is possible. It is.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 이 발명에 따른 클럭위상 조정회로도.1 is a clock phase adjustment circuit diagram according to the present invention.
제2도는 이 발명에 다른 엔코더에서 삽입되는 인식패턴의 일예도.2 is an example of a recognition pattern inserted in an encoder according to the present invention.
제3도는 제1도의 클럭위상 조정 및 기준신호 검출회로의 상세 블럭도.3 is a detailed block diagram of the clock phase adjustment and reference signal detection circuit of FIG.
제4도는 제2도에 따른 제3도의 출력파형도.4 is an output waveform diagram of FIG. 3 according to FIG.
제5도는 인식패턴 샘플링메 따른 파형도이다.5 is a waveform diagram according to a recognition pattern sampling method.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920003181A KR950001567B1 (en) | 1992-02-28 | 1992-02-28 | Clock phase adjustment circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920003181A KR950001567B1 (en) | 1992-02-28 | 1992-02-28 | Clock phase adjustment circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930019018A true KR930019018A (en) | 1993-09-22 |
KR950001567B1 KR950001567B1 (en) | 1995-02-25 |
Family
ID=19329651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920003181A KR950001567B1 (en) | 1992-02-28 | 1992-02-28 | Clock phase adjustment circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950001567B1 (en) |
-
1992
- 1992-02-28 KR KR1019920003181A patent/KR950001567B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950001567B1 (en) | 1995-02-25 |
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