KR930016771U - ASIC Signal Debugging Circuit - Google Patents

ASIC Signal Debugging Circuit

Info

Publication number
KR930016771U
KR930016771U KR2019910023664U KR910023664U KR930016771U KR 930016771 U KR930016771 U KR 930016771U KR 2019910023664 U KR2019910023664 U KR 2019910023664U KR 910023664 U KR910023664 U KR 910023664U KR 930016771 U KR930016771 U KR 930016771U
Authority
KR
South Korea
Prior art keywords
debugging circuit
signal debugging
asic signal
asic
circuit
Prior art date
Application number
KR2019910023664U
Other languages
Korean (ko)
Other versions
KR940005878Y1 (en
Inventor
경 류
Original Assignee
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 금성사 filed Critical 주식회사 금성사
Priority to KR2019910023664U priority Critical patent/KR940005878Y1/en
Publication of KR930016771U publication Critical patent/KR930016771U/en
Application granted granted Critical
Publication of KR940005878Y1 publication Critical patent/KR940005878Y1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
KR2019910023664U 1991-12-23 1991-12-23 Signal debugging circuit of asic KR940005878Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910023664U KR940005878Y1 (en) 1991-12-23 1991-12-23 Signal debugging circuit of asic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910023664U KR940005878Y1 (en) 1991-12-23 1991-12-23 Signal debugging circuit of asic

Publications (2)

Publication Number Publication Date
KR930016771U true KR930016771U (en) 1993-07-29
KR940005878Y1 KR940005878Y1 (en) 1994-08-26

Family

ID=19325358

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910023664U KR940005878Y1 (en) 1991-12-23 1991-12-23 Signal debugging circuit of asic

Country Status (1)

Country Link
KR (1) KR940005878Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100388494B1 (en) * 2001-05-07 2003-06-25 한국전자통신연구원 System for function analyzing of codec ASIC chip and its method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100388494B1 (en) * 2001-05-07 2003-06-25 한국전자통신연구원 System for function analyzing of codec ASIC chip and its method

Also Published As

Publication number Publication date
KR940005878Y1 (en) 1994-08-26

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19961230

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee