KR930016745U - Digital signal delay circuit - Google Patents

Digital signal delay circuit

Info

Publication number
KR930016745U
KR930016745U KR2019910023615U KR910023615U KR930016745U KR 930016745 U KR930016745 U KR 930016745U KR 2019910023615 U KR2019910023615 U KR 2019910023615U KR 910023615 U KR910023615 U KR 910023615U KR 930016745 U KR930016745 U KR 930016745U
Authority
KR
South Korea
Prior art keywords
digital signal
delay circuit
signal delay
circuit
digital
Prior art date
Application number
KR2019910023615U
Other languages
Korean (ko)
Other versions
KR950000205Y1 (en
Inventor
김예태
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019910023615U priority Critical patent/KR950000205Y1/en
Publication of KR930016745U publication Critical patent/KR930016745U/en
Application granted granted Critical
Publication of KR950000205Y1 publication Critical patent/KR950000205Y1/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
KR2019910023615U 1991-12-23 1991-12-23 Digital delay circuit KR950000205Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910023615U KR950000205Y1 (en) 1991-12-23 1991-12-23 Digital delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910023615U KR950000205Y1 (en) 1991-12-23 1991-12-23 Digital delay circuit

Publications (2)

Publication Number Publication Date
KR930016745U true KR930016745U (en) 1993-07-29
KR950000205Y1 KR950000205Y1 (en) 1995-01-12

Family

ID=19325316

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910023615U KR950000205Y1 (en) 1991-12-23 1991-12-23 Digital delay circuit

Country Status (1)

Country Link
KR (1) KR950000205Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000045127A (en) * 1998-12-30 2000-07-15 김영환 Data variable delay circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000045127A (en) * 1998-12-30 2000-07-15 김영환 Data variable delay circuit

Also Published As

Publication number Publication date
KR950000205Y1 (en) 1995-01-12

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Legal Events

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A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
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FPAY Annual fee payment

Payment date: 20021223

Year of fee payment: 9

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